US 4,922,138 AGrant
Scan Circuit Using a Plural Bootstrap Effect for Forming Scan Pulses
Issue Date:1990-05-01
•19 Claims
•9 Drawing Sheets
Abstract
There is provided a scan circuit in which a plurality of unit circuits are connected and scan pulses are sequentially output from the unit circuits in response to drive pulses. In this circuit, the potential at an output terminal of the unit circuit is raised by one drive pulse. The potential at the output terminal is further increased by use of the bootstrap effect by the other drive pulse, thereby forming a scan pulse.
Metadata
Assignee
- Canon Kabushiki Kaisha
Inventors
- Seiji Hashimoto
- Tadanori Harada
Application Information
Application Number:US 1964798
Filing Date:1988-05-20
Priority Date:1987-05-25
Art Unit:254
Classifications
IPC:
H03K 19096
Field of Search:
307377443;448;453;480;481-482;578;26976-79
Patent Drawings (9 sheets)
Description
Background of the Invention
1. Field of the Invention
The present invention relates to a scan circuit in which a plurality of unit circuits are connected and scan pulses are sequentially output from the unit circuits in response to drive pulses.
2. Related Background Art
FIG. 1 is a schematic circuit diagram of a drive section in a solid state image pickup apparatus using a conventional scan circuit.
In the diagram, respective output terminals of a scan circuit 401 are connected to horizontal lines HDL.sub.1, HDL.sub.2, and HDL.sub.3, and to horizontal lines HDL.sub.3, HDL.sub.4, HDL.sub.5, . . . through transistors Qy.sub.1 to Qy.sub.4.
A signal F.sub.1 to select odd number fields is input to gate electrodes of the transistors Qy.sub.1 and Qy.sub.2. A signal F.sub.2 to select even number fields is input to gate electrodes of the transistors Qy.sub.3 and Qy.sub.4. Namely, the transistors Qy.sub.1 to Qy.sub.4 constitute an interlacing circuit.
When the signal F.sub.1 is input, scan pulses Qy.sub.1, Qy.sub.2, . . . are sequentially output to the horizontal lines HDL.sub.1 and HDL.sub.2, horizontal lines HDL.sub.3, and HDL.sub.4, through the transistors Qy.sub.1 and Qy.sub.2.
On the other hand, when the signal F.sub.2 is input, the scan pulses Oy.sub.1, Oy.sub.2, . . . are sequentially output to the horizontal lines HDL.sub.2 and HDL.sub.3, the HDL.sub.4 and HDL.sub.5, . . . through the transistors Qy.sub.3 and Qy.sub.4.
However, in the foregoing image pickup apparatus using the conventional scan circuit, the signals F.sub.1 and F.sub.2 are transferred to the horizontal lines HDL through the transistors Qy.sub.1 and Qy.sub.2 and the transistors Q.sub.3 and Qy.sub.4 of the interlacing circuit. Therefore, there are problems such that a voltage drop due to a threshold value voltage Vth of the transistor Qy occurs and the dynamic range is narrowed, so that the picture quality deteriorates.
To solve this problem, in Japanese Patent Gazette No. 61-61586, a vertical buffer circuit to compensate a voltage level of the scan pulse Oy is provided. However, since the buffer circuit is separately provided, the number of elements constituting the vertical scan circuit increases and also the buffer circuit has a bootstrap capacitance. Thus, there is a problem such that it is difficult to reduce the area of the elements.
On the other hand, since two horizontal lines are simultaneously driven, the conventional drive circuit cannot be used in the image pickup devices in which a signal is readout by every one vertical line. Namely, the conventional constitution has problems such that there is a limitation in driving manner and this constitution can be applied to only the limited driving method.
Summary of the Invention
It is an object of the present invention to provide a scan circuit which can output scan pulses of a sufficiently high level without providing any special circuit to compensate a voltage level of the scan pulses.
According to one embodiment of the present invention, there is provided a scan circuit in which a plurality of unit circuits are connected and scan pulses are sequentially output from the unit circuits in response to drive pulses, wherein a potential at an output terminal of the unit circuit is raised by one drive pulse and the potential at the output terminal is further increased by use of the bootstrap effect by another drive pulse, thereby forming the scan pulses.
In this manner, since the scan pulse at a high voltage can be output by use of the bootstrap effect, the voltage drop by the interlacing circuit or the like can be sufficiently compensated. Any special compensating circuit like the conventional circuit is unnecessary. The constitution of the circuit can be simplified and the area of the devices can be easily reduced.
On the other hand, according to another embodiment of the invention, there is provided a drive circuit of a solid state image pickup apparatus for supplying a drive signal to a plurality of drive lines to drive image pickup elements, wherein switching means are provided for each output of the scan circuit and the drive signals can be supplied to desired ones of the drive lines through the switching means, and the drive signals can be supplied to the drive lines in a desired mode by a desired combination of the scan output of the scan circuit and the drive signals.
With this constitution, even when a plurality of drive lines are scanned, each line can be independently driven and various kinds of driving modes such as interlacing scan, non-interlacing scan, and the like of a plurality of lines can be easily realized. The above and other objects and features of the present invention will become apparent from the following detailed description and the appended claims with reference to the accompanying drawings.
Brief Description of the Drawings
FIG. 1 is a schematic circuit diagram of a drive section in a solid state image pickup apparatus using a conventional scan circuit;
FIG. 2A is a partial circuit diagram in the first embodiment of a scan circuit according to the present invention;
FIG. 2B is a voltage waveform diagram in the respective sections for explaining the operation of the embodiment;
FIG. 3 is a partial circuit diagram of the second embodiment of the invention;
FIG. 4 is a voltage waveform diagram for explaining the operation of the circuit in FIG. 3;
FIG. 5 is a schematic circuit diagram of a drive section using a scan circuit of the embodiment;
FIG. 6 is a timing chart for explaining the operation of the drive section of FIG. 5;
FIG. 7 is a schematic circuit diagram of another example of a drive section using the scan circuit of the embodiment;
FIG. 8 is a timing chart for explaining the operation of the drive section of FIG. 7;
FIG. 9 is a schematic cross sectional view showing an example of a photoelectric converting cell which is used in a solid state image pickup apparatus;
FIG. 10A is an equivalent circuit diagram of the photoelectric converting cell;
FIG. 10B is a voltage waveform diagram for explaining the operation of the circuit of FIG. 10A;
FIG. 11 is a schematic circuit diagram of the image pickup apparatus using the photoelectric converting cell; and
FIG. 12 is a timing chart for schematically explaining the operation of the image pickup apparatus of FIG. 11.
Detailed Description of the Preferred Embodiments
An embodiment of the present invention will be described in detail hereinbelow with reference to the drawings.
FIG. 2A is a partial circuit diagram of the first embodiment of a scan circuit according to the invention. FIG. 2B is a voltage waveform diagram in the respective sections for explaining the operation of the embodiment.
In this embodiment, n unit circuits are connected and scan pulses .phi..sub.1 to .phi..sub.n are sequentially output from the unit circuits. It is assumed that a potential of each section in FIG. 2A is expressed as V(i) using the number (i) added to each section.
In the diagrams, in the unit circuit at the first stage, when a pulse .phi..sub.v1 rises after a pulse P.sub.s is applied, a transistor M.sub.1 is made conductive and the potential V(4) rises. Since the potential V(4) is the gate potential of a transistor M.sub.2, the transistor M.sub.2 shows a conductance corresponding to the potential V(4).
Subsequently, when the pulse .sub.v1 falls and a pulse .phi..sub.v2 rises, the potential V(5) increases through the transistor M.sub.2. The increase in the potential V(5) is fed back to a gate of the transistor M.sub.2 via a capacitor C.sub.1, thereby increasing the potential V(4) due to the bootstrap effect. The increase in the potential V(4) acts so as to raise a conductance of the transistor M.sub.2. Therefore, the pulse .phi..sub.v2 passes, while a voltage drop hardly occurs due to the transistor M.sub.2. This pulse is transmitted through a transistor M.sub.3, thereby increasing the potential V(6).
Since the potential V(6) is the gate potential of a transistor M.sub.6, a conductance of the transistor M.sub.6 rises in correspondence to the potential V(6).
When the pulse .phi..sub.v1 subsequently rises, the potential V(7) increases through the transistor M.sub.6. The potential V(6) further rises due to the bootstrap effect owing to the increase in the potential V(7). Since the increase in the potential V(6) acts so as to enhance the conductance of the transistor M.sub.6, the pulse .phi..sub.v1 allows the potential V(8) to be raised through the transistors M.sub.6 and M.sub.7 (refer to FIG. 2B). Therefore, a transistor M.sub.10 exhibits the conductance corresponding to the gate potential V(8).
Next, when the pulse .phi..sub.v2 rises, the transistor M.sub.8 is turned on and the potential V(7) is reset to the earth potential and the transistor M.sub.7 is turned off. Thus, the portion of the potential V(8) is set into the floating state.
At the same time, since the pulse .phi..sub.v2 rises, the potential V(9) rises through the transistor M.sub.10. The increase in the potential V(9) further increases the potential V(8) by the bootstrap effect.
If such a change in the potential V(8) is used as a scan pulse .phi..sub.1, a scan pulse at a high voltage can be obtained.
Next, the potential V(8) is reset by the pulse .phi..sub.v1 and at the same time, the potential V(12) rises and, further, increases by the subsequent pulse .phi..sub.v2. The potential V(12) is used as a scan pulse .phi..sub.2. In a manner similar to the above, scan pulses .phi..sub.3 to .phi..sub.n at a high voltage level are successively output synchronously with the pulses .phi..sub.v2.
In FIG. 2B, by properly setting the timings for the drive pulses .phi..sub.v1 and .phi..sub.v2, the waveforms of the scan pulses .phi..sub.1 to .phi..sub.n can be made approach a square shape.
FIG. 3 is a partial circuit diagram of the second embodiment of the invention. FIG. 4 is a voltage waveform diagram for explaining the operation thereof.
In this embodiment, first, the transistor M.sub.1 is turned on and the potential V(A) rises by the start pulse P.sub.s and drive pulse .phi..sub.v1. Thus, the transistors M.sub.2 and M.sub.3 exhibit a certain conductance.
Subsequently, since the drive pulse .phi..sub.v1 falls, an output of an inverter 501 rises. Consequently, a voltage is applied to a capacitor C.sub.p through the transistor M.sub.3 and the potential V(A) further rises by the bootstrap effect.
Therefore, if such a change in the potential V(A) is used as a scan pulse .phi..sub.1, the scan pulse at a high voltage can be derived in a manner similar to the first embodiment. In a manner similar to the above, scan pulses .phi..sub.2 to .phi..sub.n at a high voltage level can be successively output synchronously with the drive pulses .phi..sub.v1 and .phi..sub.v2.
Therefore, even when the interlacing circuit shown in FIG. 1 is provided, the voltage drop can be sufficiently compensated and the high level drive voltage can be transferred to the horizontal lines HDL.
FIG. 5 is a schematic circuit diagram of a drive section using the scan circuit of the embodiment. FIG. 6 is a timing chart for explaining the operation thereof.
As shown in FIG. 5, the image pickup device comprises photoelectric converting cells C.sub.11, C.sub.12, . . . and the like which are arranged like an area and driven every row by the horizontal lines HDL.sub.1, HDL.sub.2, HDL.sub.3, . . . . The photoelectric conversion signals are read out through the vertical lines and transistors Q.sub.1 and Q.sub.2.
In this embodiment, gate electrodes of three transistors Q.sub.v1 to Q.sub.v3 are connected to output terminals of a scan circuit 101, respectively.
Each transistor Q.sub.v1 transfers a drive voltage V.sub.r1 to the horizontal lines HDL.sub.1, HDL.sub.3, HDL.sub.5, . . . . Each transistor Q.sub.v2 transfers a drive voltage V.sub.r2 to the horizontal lines HDL.sub.2, HDL.sub.4, HDL.sub.6, . . . . Each transistor Q.sub.v3 transfers a drive voltage V.sub.r3 to the HDL.sub.3, HDL.sub.5, HDL.sub.7, . . . .
In such a circuit arrangement, the scan circuit 101 sequentially outputs the scan pulses .phi..sub.1, .phi..sub.2, . . . in response to pulses .phi..sub.v1 and .phi..sub.v2. Therefore, by applying the drive voltages V.sub.r1 to V.sub.r3 by a proper combination, the image pickup device can be scanned in a desired mode.
For example, as shown in FIG. 6, by applying the drive voltage V.sub.r1 and V.sub.r2 in the odd number fields, the horizontal lines HDL.sub.1 and HDL.sub.2, and HDL.sub.3 and HDL.sub.4, . . . are driven and by applying the drive voltage V.sub.r2 and V.sub.r3 in the even number fields, the HDL.sub.2 and HDL.sub.3, and HDL.sub.4 and HDL.sub.5, . . . are driven. In this manner, the interlacing scan of the two line driving type can be accomplished.
On the other hand, if the drive voltages V.sub.r1 and V.sub.r2 and the drive voltages V.sub.r2 and V.sub.r3 are applied at different timings which are deviated from each other, the vertical line of the image pickup device can be also set to a single vertical line.
Even when such a vertical buffer circuit is provided, since the output of the scan circuit 101 according to the embodiment is set to the high voltage level, the transistors Q.sub.v1 to Q.sub.v3 can be set to enough high conductances. The drive voltages V.sub.r1 to V.sub.r3 can be transferred to the horizontal lines HDL without reducing the drive voltages V.sub.r1 to V.sub.r3.
FIG. 7 is a schematic circuit diagram of another example of a drive section using the scan circuit of the embodiment. FIG. 8 is a timing chart for explaining the operation thereof.
In this manner, by providing the transistors Q.sub.v1 to Q.sub.v4 at the respective output terminals of the scan circuit 101 and by combining the drive voltages V.sub.r1 to V.sub.r4 as shown in the timing chart, the interlacing scan of the three-line driving type can be also accomplished.
A practical example of a solid state image pickup apparatus using the embodiment will now be explained.
FIG. 9 is a schematic cross sectional view of an example of photoelectric converting cells which are used in the solid state image pickup apparatus.
In the diagram, an n.sup.- layer 202 serving as a collector region is formed on an n type silicon substrate 201 by the epitaxial growth. A p base region 203 is formed in the n.sup.- layer 202. An n.sup.+ emitter region 204 is further formed in the p base region 203. In this manner, a bipolar transistor is constituted.
The p base region 203 is two-dimensionally arranged. The cells in the horizontal direction are separated from the cells in the vertical direction by a device separating region. Although not shown, the device separating region comprises an oxide film formed by the LOCOS Oxidation and an n.sup.+ region formed under the oxide film.
On the other hand, a gate electrode 208 is formed between horizontally neighboring p base regions 203 through an oxide film 207. Therefore, a p channel MOS transistor in which the adjacent p base regions 203 are used as source and drain regions is constituted.
This MOS transistor is the normally OFF type and is set to the OFF state when the potential of the gate electrode 208 is the earth potential or positive potential. Therefore, the p base regions 203 between the adjacent cells are electrically isolated. On the contrary, when the potential of the gate electrode 208 is a negative potential which exceeds a threshold value potential V.sub.th, the MOS transistor is set to the ON state, so that the p base regions 203 of the respective cells are mutually made conductive.
The gate electrodes 208 are commonly connected to the drive line every row in the horizontal direction. Further, capacitors 209 to control the potentials of the p base regions 203 are also similarly connected to the drive line. The drive line extends in the horizontal direction on the oxide film serving as the device separating region.
Further, after a transparent insulative layer 211 was formed, an emitter electrode 212 is formed. The emitter electrodes 212 are connected to a vertical line 213 every column. A collector electrode 214 is formed on the back surface of the substrate 201 through an ohmic contact layer.
FIG. 10A is an equivalent circuit diagram of the photoelectric converting cell. FIG. 10B is a voltage waveform diagram for explaining the operation thereof.
It is now assumed that carriers (in this case, holes) as much as the incident light amount are accumulated in the p base region 203. It is also assumed that a negative voltage V.sub.c is applied to a terminal of a transistor Q.sub.c and a positive voltage is applied to the collector electrode 214.
In this state, pulses .phi..sub.d of a positive voltage are applied to a drive line 210 for only a period of time T.sub.rd. Thus, the potential of the p base region 203 rises through a capacitor C.sub.ox and the signal is read out to the emitter electrode 212 as mentioned above.
Subsequently, pulses .phi..sub.d of a negative voltage are applied to the drive line 210 for only a period of time T.sub.rh. Thus, the p channel MOS transistor Q.sub.c is turned on and the base potential is reset to the voltage V.sub.c and the refreshing operation is completely performed. On the other hand, by setting a pulse .phi..sub.r to the high level, the transistor Q.sub.r is turned on, thereby resetting the vertical line 213.
As already mentioned above, as the refreshing operation, after the MOS transistor Q.sub.c was turned on, the pulse .phi..sub.d of a positive voltage can be also applied while the emitter electrode 212 is grounded. In this case, there is no need to set the voltage V.sub.c to a negative voltage but can be set to the earth voltage or positive voltage.
After completion of the foregoing refreshing operation, the accumulating operation is started. The similar operations are repeated hereinafter.
FIG. 11 is a schematic circuit diagram of an image pickup apparatus using the foregoing photoelectric converting cells.
In this apparatus, m.times.n photoelectric converting cells are arranged like an area.
In the cells C.sub.11 to C.sub.1n, C.sub.2l to C.sub.2n, . . . on the horizontal lines, the gate electrodes 208 of the MOS transistor Q.sub.c are commonly connected to the drive lines HDL.sub.l to HDL.sub.m, respectively.
The drive lines HDL.sub.l to HDL.sub.m are connected to a vertical buffer circuit 301. The scan pulses .phi..sub.1 to .phi..sub.m are input to the vertical buffer circuit 301 from the vertical scan circuit 101 as the embodiment.
The MOS transistors Q.sub.c in each of which the p base regions 203 in each cell are used as source and drain regions are serially connected every horizontal line. The p regions to form the MOS transistor Q.sub.c are respectively formed in the cells C.sub.ll to C.sub.ml arranged at the edge line. On the other hand, MOS transistors Q.sub.x1 to Q.sub.xm are respectively serially connected to the cells C.sub.ln to C.sub.mn. A constant voltage V.sub.c is applied to both ends.
The emitter electrodes in the cells C.sub.11 to C.sub.m1, C.sub.12 to C.sub.m2, . . . in the vertical direction are commonly connected to vertical lines VL.sub.1 to VL.sub.n, respectively. The vertical lines are grounded through reset transistors Q.sub.rl to Q.sub.rn. A reset pulse .phi..sub.r is commonly input to the gate electrodes of the transistors Q.sub.rl to Q.sub.rn.
The vertical lines VL.sub.l to VL.sub.n are connected to capacitors C.sub.1 and C.sub.2 through transistors Q.sub.t1 and Q.sub.t2, respectively. The pulses .phi..sub.1 and .phi..sub.2 are input to the gate electrodes of the transistors Q.sub.t1 and Q.sub.t2.
Further, the capacitors C.sub.1 and C.sub.2 are connected to signal lines 303 and 304 through the transistors Q.sub.1 and Q.sub.2, respectively. Scan pulses .phi..sub.11 to .phi..sub.nl of a horizontal scan circuit 302 are input to the gate electrodes of the transistors Q.sub.1 and Q.sub.2, respectively.
Various kinds of pulses .phi., voltages V, and the like to drive the image pickup apparatus are supplied from a driver 305. The driver 305 is controlled by a controller 306.
FIG. 12 is a timing chart for schematically explaining the operation of the image pickup apparatus.
In the odd number fields F.sub.o, when the pulses .phi..sub.v1 and .phi..sub.v2 are input to the vertical scan circuit 101, the scan pulse .phi..sub.1 rises. The scan pulse .phi..sub.1 is set to the high voltage since it uses the bootstrap effect as mentioned above.
Thus, the vertical buffer circuit 301 outputs input voltages V.sub.r1 and V.sub.r2 to the horizontal lines HDL.sub.1 and HDL.sub.2, respectively.
Simultaneously with the rising of the pulse .phi..sub.v2, the pulses .phi..sub.tl and .phi..sub.r rise and the transfer transistor Q.sub.t1 and reset transistor Q.sub.r are turned on, thereby clearing the vertical lines VL and capacitor C.sub.1.
Subsequently, after the reset transistor Q.sub.r was turned off, the input voltage V.sub.r1 is set to a positive voltage and the reading operations of the cells C.sub.ll to C.sub.ln on the horizontal line HDL.sub.1 are executed. The readout signals are stored into the capacitor C.sub.1 through the transfer transistor Q.sub.t1, respectively.
Next, when the pulses .phi..sub.t2 and .phi..sub.r rise, the transfer transistor Q.sub.t2 and reset transistor Q.sub.r are turned on, thereby clearing the capacitor C.sub.2 and vertical lines VL.
Subsequently, the input V.sub.r2 is set to a positive voltage and the reading operations of the cells C.sub.21 to C.sub.2n on the horizontal line HDL.sub.2 are executed. The readout signals are stored into the capacitor C.sub.2 through the transfer transistor Q.sub.t2.
The foregoing operations are performed within a horizontal blanking period HBLK. Next, the sensor signals of the first and second rows which were accumulated in the capacitors C.sub.1 and C.sub.2 within the effective horizontal period are scanned and output.
Namely, the transistors Q.sub.1 and Q.sub.2 are sequentially turned on by the scan pulses .phi..sub.11 to .phi..sub.n1 which are successively output from the horizontal scan circuit 302. The signals stored in the capacitors C.sub.1 and C.sub.2 are read out and output to the signal lines 303 and 304.
In parallel with those operations, the pulse .phi..sub.r rises and the transistor Q.sub.r is turned on, thereby grounding the vertical lines VL. On the other hand, the input voltages V.sub.r1 and V.sub.r2 are set to a negative voltage, thereby refreshing the cells of the first and second rows. That is, the MOS transistor Q.sub.c of each cell are turned on and each base potential is set to a constant value.
Next, the input voltages V.sub.r1 and V.sub.r2 are set to a positive voltage, thereby refreshing the base regions 203 which were reset to a constant potential. In other words, since the emitter electrodes of the cells are grounded through the vertical lines VL, when a positive voltage is applied to capacitors C.sub.ox, the circuit between the base and emitter is forwardly biased, so that the carriers accumulated in the base region 203 are extinguished in a manner similar to the reading operations.
After completion of the refreshing operation in this manner, the cells of the first and second rows start the accumulating operation.
In a manner similar to the above, the reading and refreshing operations of the third and fourth rows, the fifth and sixth rows, . . . in the odd number fields F.sub.o are sequentially executed by the pulses .phi..sub.v1 and .phi..sub.v2.
In the event number fields F.sub.e, the reading and refreshing operations of the second and third rows, the fourth and fifth rows, . . . are successively performed by the input V.sub.r2 and V.sub.r3.
By using the scan circuit 101 according to the embodiment of invention in the drive section of the image pickup apparatus, the good picture quality can be derived without providing any special voltage level compensating circuit or the like.
As explained in detail above, according to the scan circuit of the invention, the scan pulse can be set to a high voltage level by use of the bootstrap effect. Thus, even when the interlacing circuit or the like is provided, the scan can be performed by a high voltage.
Thus, there is no need to compensate the output level by adding the bootstrap capacitance as in the conventional apparatus. The circuit constitution is simplified and the area of the elements can be easily reduced.
According to the drive circuit of the invention, since the drive signals are supplied to the drive lines in a desired mode on the basis of the scan output of the scan circuit and a desired combination of the drive signals, even when a plurality of drive lines are scanned, they can be independently driven. Various kinds of driving modes such as interlacing scan, non-interlacing scan, and the like of a plurality of lines can be easily performed.
Claims
What is claimed is:
1. A scan circuit comprising a plurality of stages of interconnected unit circuits, in which scan pulses are sequentially output from said unit circuits in response to drive pulses; a first one of said unit circuits including a first input terminal, a first output terminal and first bootstrap means, and a second one of said unit circuits including a second input terminal, a second output terminal and second bootstrap means; wherein a first potential at said first output terminal is raised by said first bootstrap means when a drive pulse is input to said first input terminal of said first unit circuit, said first output terminal of said first unit circuit being connected to said second input terminal of said second unit circuit so as to apply said first potential thereto; and wherein the raised first potential at the first output terminal is further raised by raising a second potential at said second output terminal of said second unit circuit by said second bootstrap means in response to a further drive pulse, the further raised first potential being output as one of said scan pulses.
2. A scan circuit according to claim 1, wherein each said unit circuit has a plurality of transistors.
3. A scan circuit according to claim 2, wherein said unit circuits respectively have input terminals and each of said unit circuits has a first transistor whose gate is connected to said input terminal.
4. A scan circuit according to claim 3, wherein a capacitor is connected between the gate and source of said first transistor.
5. A scan circuit according to claim 3, wherein the first unit circuit is at a front stage and the second unit circuit is at a next stage connected thereto.
6. A scan circuit comprising a plurality of stages of interconnected unit circuits, said unit circuits being used in a shift register, a unit circuit of each stage comprising: an input terminal; a first field effect transistor whose gate electrode is connected to said input terminal of said unit circuit; a capacitor connected between said gate electrode and a source electrode of said first transistor; a first signal source connected to a drain electrode of said first transistor; a second field effect transistor whose drain electrode is connected to said source electrode of the first transistor, a source electrode of said second transistor being connected to ground and a gate electrode of said second transistor being connected to a second signal source; a third field effect transistor whose gate electrode and drain electrode are connected to said source electrode of the first transistor, a source electrode of said third transistor being connected to a drain electrode of fourth field effect transistor of a unit circuit of a stage preceding the stage of said unit circuit, a source electrode of the fourth transistor being connected to ground and a gate electrode of the fourth transistor being connected to a third signal source; and a signal output terminal for outputting a signal at the gate electrode of said first transistor to the outside of the shift register, said signal at said signal output terminal being applied to a drain electrode of the fourth transistor.
7. A scan circuit comprising: at least two bootstrap means for raising potentials of respective drive pulses; and an output terminal connected at an interconnection point between said two bootstrap means; wherein a scan pulse is provided at said output terminal by adding the drive pulses whose potentials are respectively raised by said bootstrap means.
8. A scan circuit according to claim 7, wherein each of said bootstrap means includes a capacitor.
9. A scan circuit according to claim 7, wherein each of said bootstrap means is disposed in a unit circuit including a plurality of transistors.
10. A scan circuit according to claim 9, wherein each of said unit circuits has an input terminal and a first field effect transistor whose gate electrode is connected to the respective input terminal.
11. A scan circuit according to claim 10, wherein a capacitor is provided between the gate electrode and a source electrode of said first transistor.
12. A scan circuit according to claim 11, wherein said output terminal is at a front stage and is connected to the input terminal of the unit circuit at a next stage.
13. A scan circuit comprising: at least two bootstrap means for raising potentials of respective drive pulses; an output terminal connected at an interconnection point between said two bootstrap means; and switching means connected between one of said two bootstrap means and said output terminal; wherein a potential of one of said drive pulses is raised by said one bootstrap means and said switching means is thereby opened, and wherein a potential of the other drive pulse is raised by the other bootstrap means and said switching means is thereby closed, thereby providing a scan pulse at said output terminal.
14. A scan circuit according to claim 13, wherein said switching means includes a transistor.
15. A scan circuit according to claim 13, wherein each of said bootstrap means includes a capacitor.
16. A scan circuit according to claim 13, wherein each of said strap means is connected in a respective unit circuit including a plurality of transistors.
17. A scan circuit according to claim 16, wherein each of said unit circuits has an input terminal and a first field effect transistor whose gate electrode is connected to the respective input terminal.
18. A scan circuit according to claim 17, wherein a capacitor is connected between the gate electrode and a source electrode of said first transistor.
19. A scan circuit according to claim 18, wherein said output terminal is at a front stage and is connected to the input terminal of a unit circuit at a next stage.