US 4,907,225 AGrant
Data Protocol Controller
Issue Date:1990-03-06
•44 Claims
•21 Drawing Sheets
Abstract
An integrated data protocol controller (IDPC)(10) is disclosed which includes on a single chip a data link controller (DLC)(52), a universal asynchronous receiver-transmitter (UART)(54) and a dual port timing controller (DPTC)(56). The IDPC is designed to support bit-oriented protocols such as is used in integrated services digital networks (ISDN). A microprocessor interface (50) on the IDPC chip permits a user to control and monitor the IDPC functions via a local microprocessor (18). The IDPC can be connected to a host processor (595) which shares a random access memory (RAM)(22a) with the local processor, allowing interprocessor communication via memory-resident buffers and mailboxes. A set of control and status registers is available within each of the main blocks of the IDPC--the DLC, the UART and the DPTC--to permit user access and control of the respective blocks. The DLC, the UART and the DPTC provide enhanced functions beyond those available in individual chips realizing a DLC, a UART or a DPTC.
Metadata
Assignee
- Advanced Micro Devices, Inc.
Inventors
- Dale E. Gulick
- Terry G. Lawell
- Charles Crowe
Application Information
Application Number:US 3680835
Filing Date:1989-06-16
Priority Date:1987-04-03
Art Unit:263
Classifications
IPC:
H04J 324
Field of Search:
37037585;94;84;24;297;8
Patent Drawings (21 sheets)
Description
Co-pending applications of particular interest to the instant application are U.S. Ser. No. 759,622 filed July 26, 1985, on behalf of Alan T. Clark, Hadi Ibrahim and Arthur F. Lange, now U.S. Pat. No. 4,635,255 entitled "Digital Subscriber Controller"; U.S. Ser. No. 07/035,684, filed Apr. 3, 1987, on behalf of D. Gulick, T. Lawell and C. Crowe, entitled "Enhanced Universal Asynchronous Receiver-Transmitter"; U.S. Ser. No. 07/035,817, filed Apr. 3, 1987, on behalf of D. Gulick, T. Lawell and C. Crowe, entitled "Packet-At-A-Time Reporting in a Data Link Controller"; U.S. Ser. No. 07/035,683, filed Apr. 3, 1987, on behalf of D. Gulick and T. Lawell, entitled "Data Link Controller with Flexible Multiplexer"; and U.S. Ser. No. 07/035,687, filed Apr. 3, 1987, on behalf of D. Gulick, and entitled "Dual-Port Timing Controller", all assigned to the assignee of the instant application.
FIELD OF THE INVENTION
This invention concerns integrated service digital telecommunication networks and, more particularly, to an integrated circuit data protocol controller including a data link controller, an enhanced universal asynchronous receiver-transmitter and a dual-port timing controller.
BACKGROUND OF THE INVENTION
An Integrated Services Digital Network (ISDN) provides voice and data communications between an originating endpoint, through a combination of one or more private branch exchanges (PBX's) and/or telephone company central and regional offices, to a destination endpoint. Evolving ISDN standards being developed by the International Telephone and Telegraph Consultative Committee (CCITT) define signaling (call setup) and data transfer protocols for each interface (reference point) in this link.
The `S` interface is the point at which computers and terminals attach to the ISDN. The `S` interface is supported on the Network Terminating (NT) equipment side by the AMD DEC chip (79C31) and on the Terminal Equipment (TE) side by the AMD DSC chip (79C30). In large installations, the NT equipment may be a PBX; in smaller installations (e.g., homes), a single TE may be connected to a single telephone line NT. Terminals which communicate using pre-ISDN standards (e.g., RS232) attached at a reference point `R` and a Terminal Adaptor (TA) is used for protocol conversion/rate adaption.
In the initial ISDN scheme, signaling (D-channel) and voice/data (B-change) bit streams are time division multiplexed on the same `S` interface telephone line. (The voice phone analogy for what takes place on the D-channel is the dial-ringing-answer sequence; the analogy for the B-channel is the conversation that takes place once the call is answered.)
Data rates on the ISDN will be substantially higher than those possible today in the public telephone network. In order to provide reliable error-controlled data transmission on the ISDN, members of the Bit-Oriented Protocol (BOP) family of protocols (e.g., LAPD, LAPB) will be used on both D- and B-channels.
Two major `S` interface types, Primary Rate Interface and Basic Rate Interface, are being defined in initial ISDN specifications.
The Primary Rate Interface consists of 23 64 Kbps and one 64 Kbps D-channel used for call/teardown for all of the B-channels. It is anticipated that this 23B+D interface will be used to connect relatively large minicomputers, mainframes, and internetwork gateways to the ISDN.
The Basic Rate Interface consists of two 64 Kbps B-channels and one 16 KBPS D-channel used for call setup/teardown for both of the B-channels. This 2B+D interface will be used to connect "dumb" terminals, integrated voice/data workstations (IVDW's) and personal computers (PC's) to the ISDN.
Each of the B-channels in a 2B+D interface may be used for either digitized voice or data calls. Data calls may be made to either 2B+D or 23B+D endpoints. A given data call may be setup for file transfer between computers or for an interactive session between a human user and a computer.
SUMMARY OF THE INVENTION
The integrated Data Protocol Controller (IDPC) of the instant invention is intended to support data calls on one B-channel in a 2B+D interface. The IDPC can support multiple simultaneous logical data calls on the one physical B-channel.
The IDPC provides an external bus for attachment of a microprocessor (the "local processor"), dedicated memory, `S` interface transceiver hardware, and other ISDN interface support hardware. An optional "host" microprocessor communicates with the local processor via memory on the IDPC external bus and via interprocessor interrupts using hardware supplied by the IDPC. In applications where there is no host processor, the IDPC supplies an enhanced UART for exchanging data between ISDN and user.
The IDPC of the instant invention provides a bit-oriented protocol (BOP) data controller fabricated as a single integrated circuit having an internal bus, bidirectional port means for high-speed serial receipt and transmission of data signals, full-duplex means for low-speed serial receipt and transmission of data signals and interface means connected to said internal bus for the connection of a microprocessor. The BOP data controller includes a data link controller (DLC) connected to the internal bus and to the microprocessor interface means and to the serial port means, comprising transmitter means for parallel reception of data on said internal bus for parallel-to-serial conversion thereof and for serial generation thereof at said serial port means, and receiver means for serial reception of data on said serial port means, for serial-to-parallel conversion thereof and for parallel generation thereof on said internal bus.
The IDCP further includes a universal asynchronous receiver-transceiver (UART) connected to the microprocessor interface means, to the internal bus, and to the full-duplex means, comprising transmitter means for parallel reception of data on said internal bus, for parallel-to-serial conversion thereof, and for serial generation thereof at said full-duplex means, and receiver means for serial reception of data on said full-duplex means, for serial-to-parallel conversion thereof and for parallel generation thereof on said internal bus.
The IDPC also includes a dual-port timing controller (DPTC) connected to the internal bus, to the microprocessor interface, to a host processor and to a shared RAM and bus arbitration means for connecting the microprocessor and the host processor to the BOP data controller for generating timing and control signals whereby said shared RAM and said BOP data controller is accessible to both said microprocessor and said host processor.
In another aspect of the invention, the IDPC has a memory map wherein the DLC portion, the UART portion and the DPTC portion have predetermined addresses and a memory map provides microprocessor access to the various portions of the IDPC.
A UART, compatible with the 8250 standard, is provided on the IDPC which can be selectably operated in a synchronous or an asynchronous mode. A user-accessible register within the enchanced UART of the present invention has a bit position which can be set by the microprocessor controlling the UART to determine the mode of operation. In the synchronous mode data is placed into a receive shift register on every clock cycle. Furthermore, the clock signal can be selected from either an internally-generated clock signal or a clock signal applied to the UART from an external source. Normally, in synchronous operation, only the latter signal would be used for reception of data, which would be equal to, and in synchronization with, the rate at which data is received.
For transmission of data in the synchronous mode, data is transmitted from a transmit shift register at a rate clocked by either the internal or external clock. Data is transmitted as a steady stream of bits with no start or stop framing bits required.
The enchanced UART of the IDPC of the instant invention provides a receiver-side first-in, first-out (FIFO) elastic buffer capable of storing four ten-bit words. Each ten-bit word consists of an eight-bit character portiion, a 1-bit parity error flag and a 1-bit special character flag.
Data is received by the UART by a serial-to-parallel shift register and stored in the receive FIFO. An interrupt signal is generated when the number of characters stored in the FIFO has reached a threshold level specified by a user-accessible register. Data is read out of the receive FIFO under control of the microprocessor.
A parity, special character, frame and break checker monitors characters received by the UART and sets the parity-error and special character flags accordingly. The checker employs a random access memory (RAM) present on the enchanced UART to determine whether received characters are special, in the sense that the user, via the microprocessor, has stored in a location in the RAM an eight-bit pattern which is to be flagged as special. The presence of a character that either has a parity error or is a special character is reported in a user-accessible register as an interrupt signal can be generated which allows the user to identify which character caused the interrupt.
A transmit-side FIFO buffer is employed in the UART of the IDPC of the instant invention. A transmit parallel-to-serial shift register is loaded from the transmit FIFO. When the number of characters in the FIFO falls to a threshold number, programmed into a user-accessible register, an interrupt signal can be generated.
The enchanced UART of the IDPC of the instant invention provides the synchronous mode, transmit and receive FIFOs, parity and special character recogniton while being completely software compatible with the industry standard 8250 UART. Twelve user-accessible registers include registers which have bit positions permitting enablement and control of these enhanced functions while maintaining complete compatibility with the 8250.
A data link controller (DLC) is provided which is suitable for use in ISDN applications, employing bit-oriented protocols. In one aspect of the DLC of the instant invention, the DLC can be operated in a time-division multiplexed mode or a non-multiplexed mode. In the multiplexed mode, data in one of up to thirty-one selectable time slots is received by the DLC under control of a microprocessor. One of the time slots can be selected via the microprocessor which allows a lengthened contiguous number of bits to be received, effectively increasing the reception rate. In the non-multiplexed mode, data is received as a continuous stream. In the multiplexed mode up to thirty-one time slots are available for transmission of data. Time slot selection is user-controlled via the microprocessor. One of the time slots can be selected which allows a lengthened continuous number of bits to be transmitted, effectively increasing the transmission rate. In the lengthened configuration, by doubling the length of the time slot, two 64 KBPS B-channels can act as a single 128 KBPS channel.
Control of the mode of operation of the DLC of the present invention is provided by various Status and Control Registers accessible by the user via a microprocessor. Particular registers have bit positions monitoring status conditions in such a manner that the most-probable one of a set of conditions occupies the least-significant bit position, while the least-probable condition occupies the most-significant bit position. In this aspect of the invention, a user can efficiently test conditions; both in terms of real-time monitoring and programming ease.
A data link controller of the IDPC of the instant invention employs first-in, first-out (FIFO) buffers on the transmit and receive sides. A number of 9-bit words are stored in the buffer, each word comprising the 8-bit character portion and a ninth "last byte of a packet" bit. A transmit byte count register stores the length of the packet to be transmitted. A transmit byte counter is used in conjunction with the transmit FIFO to count the number of characters loaded into the FIFO for a given packet. When the transmit byte count reaches zero, the character's ninth bit is set to ONE; all other characters' ninth bit are ZERO.
Data request logic generates a data request signal whenever the transmit FIFO contains less than a selectable "threshold" number of characters and it does not contain an end of packet character and the byte count is greater than zero. In this way, when the level of the FIFO falls to the threshold and there is more characters in the packet, the data request signal is generated.
A receive byte counter is used in conjunction with the receive FIFO to monitor the number of characters that have been placed in the FIFO from the current packet. A ninth bit in the receive FIFO contains an "end-of-packet" tag.
A receive byte count register reports the length of the receive packet to the microprocessor. A receive frame status register and an Interrupt Source Register permit high data rate of reception, reducing the overhead in moving back-to-back packets by removing microprocessor intervention.
The Receive Frame Status Register and Receive Byte Count Registers and a Receive Link Address Bit portion of the Interrupt Source Register are implemented as a four-stage mechanism which provides delayed reporting of the status of packets. In this manner, they support the reception of multiple contiguous frames (back-to-back frames). This is necessary because of the need to maintain a history of the status (good or bad frame) and byte count of up to three previously received frames while a fourth frame is being received. A stage 1 register reflects the current status of the frame being received on the link. A "holding" stage 2, a "master" stage 3 and a "slave" stage 4 are serially connected to stage 1 and their contents is synchronously passed from one stage to the next. Received frame status can "back up" if the microprocessor has not read the status from the last stage, no transfer of information is effected between stages.
Control of the operation of the DLC of the IDPC of the present invention is provided by various Status and Control Registers accessible by the user via a microprocessor. Particular registers have bit positions monitoring status conditions in such a manner that the most-probable one of a set of conditions occupies the least-significant bit position, while the least-probable condition occupies the most-significant bit position. In this aspect of the invention, a user can efficiently test conditions; both in terms of real-time monitoring and programming ease through shift and test instructions.
In another aspect of the invention, the DLC status registers include a FIFO status register, a Receive Frame Status Register and a Receive Link Status Register, are organized to group status information according to type. For example, status information that pertains to the real time condition of communications link is reported separately from information specific to a particular received frame of data. This is a significant advantage since the user is generally only interested in the status of packets--not portions of packets--and the DLC of the instant invention reports status to the user only after the packet has received in its entirety.
In yet another aspect of the invention, the DLC status registers include an Interrupt Source Register which contains three bit fields, a packet address identification field, a valid packet field, and an interrupt source field. The interrupt source field has one bit for each of the DLC status registers. When a bit in the interrupt source field is set, the associated status register contains the interrupting condition. Accordingly, a user can efficiently locate the cause of the interrupt. Furthermore, to identify that a valid packet has been received by the DLC, the user need only read the Interrupt Source Register, shift the value read right and test the least-significant bit in shifted value.
A dual port timing controller (DPTC) which can be used with an interprocessor communication register, provides a shared RAM (S-RAM) used in conjunction with an integrated circuit integrated services data protocol controller. The S-RAM can be accessed either by the local processor or the host processor. The DPTC provides control signals allowing an ordinary RAM to be operated as an S-RAM. These signals include: memory cycle timing signals, control signals for buffers and latches required to isolate the host's system bus from the local processor's system bus and generation of interrupt signals permitting interprocessor communication via the semaphore register.
In another aspect of the invention arbitrating access to the S-RAM, the DPTC includes the semaphore register, storing bidirectional interprocessor interrupts, that provides coordination for the passing of high level messages between the local and host processors.
The IDPC can be used in two major configuration classes:
(1) Terminal Adaptor (TA)
(2) Personal Computer (PC) or Integrated Voice/Data Workstation (IVDW)
The major difference between the two classes is in the number of microprocessors in the system. In the TA case, there is only one processor ("local processor") which controls all system functions. The TA is a dedicated system which runs a specialized software program to allow user terminal equipment with a non-ISDN communications interface (e.g., dumb terminal attached to the TA's IDPC UART via RS-232) to make ISDN data calls.
The PC/IVDW application puts most of the TA hardware, including its dedicated processor running dedicated ISDN software, on a PC expansion board. This IDPC-based ISDN board subsystem is used by the main PC/IVDW processor ("host CPU") as a data transport utility for file transfer and terminal emulation on the ISDN network. The ISDN subsystem local processor exchanges data received/transmitted on the ISDN with the host CPU via shared memory and interprocessor hardware interrupts (instead of via the UART as in the TA application). The IDPC contains hardware to provide for cost effective memory sharing and interprocessor interrupts.
The local processor can access any device on the IDPC external bus; the host processor can only access the RAM on the IDPC external bus. Any contention between the local processor and the host CPU is arbitrated by a bus arbitration unit inside the IDPC. This arrangement provides for transparent access to shared memory by both the local processor and the host processor, allowing interprocessor communication via memory resident data buffers and mailboxes. A combination of IDPC interrupt related pins and IDPC register bits (which can be read and written only by the local processor) implement the interprocessor interrupt mechanism. Once the local processor or host processor has written data to a buffer or a command to a mailbox, it uses the interprocessor interrupt mechanism to notify the other processor.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 shows an illustrative case of an ISDN Protocol Controller (IDPC) of the instant invention in a terminal adapter (TA).
FIG. 2 is a block diagram of the IDPC 10 of the instant invention.
FIG. 3 is a functional block diagram of the IDPC 10 focusing on the interrelationship between the DLC 52 and the remaining portions of the IDPC.
FIG. 4 is a block diagram of the transmitter portion of the DLC 52 of the IDPC 10.
FIG. 5 illustrates the structure of the transmitter first-in, first-out (FIFO) 100 of the DLC 52.
FIG. 6 illustrates the serial-to-parallel shift register 110 of the transmitter 102 portion of DLC 52.
FIG. 7A illustrates the structure of the Zero Bit Insertion Unit 124 of the DLC 52 transmitter 102.
FIG. 7B illustrates the structure of the Flag/Abort Insertion Unit 134 of the transmitter 102 portion of DLC 52.
FIG. 8 is a block diagram of the transmitter portion of the Serial Bus Port 104.
FIG. 9 shows the timing of the transmitter portion of SBP 104.
FIG. 10 is a block diagram of the receiver portion of the DLC 52 of the IDPC 10.
FIG. 11 is a block diagram of the receiver portion of the Serial Bus Port 104 of DLC 52.
FIG. 12 shows the timing of the receiver portion of SBP 104.
FIG. 13 is a block diagram of the Flag/Abort Detection Unit 214 of the receiver 108 portion of DLC 52.
FIG. 14 is a block diagram of the Zero Bit Deletion Unit of element 218 of the DLC receiver 108.
FIG. 15 is a block diagram of the Short Frame Byte Counter 260 of element 218 of the DLC receiver 108.
FIG. 16 is a block diagram of the Serial-to-Parallel Shift register 208 and 210 and related element of the DLC receiver 108.
FIG. 17 is a block diagram of the address detection unit 226 of the DLC receiver 108.
FIG. 18 illustrates the structure of the receive FIFO 106 within the DLC 52.
FIG. 19 is a state diagram of the operation of the DLC 52 transmitter 102 portion.
FIG. 20 is a state diagram of the operation of the DLC 52 receiver 108 portion.
FIG. 21 is a functional block diagram of the UART 54 employed in the IDPC 10 of the present invention.
FIG. 22 is a block diagram of the parity checker and special character recognizer 412 of the UART 54 employed in the IDPC 10.
FIG. 23 is a block diagram showing interconnection of the Dual-Port Timing Controller (DPTC) 56 of the IDPC 10 of the instant invention to a host processor and a local processor.
FIG. 24 is a functional block diagram of the DPTC 56 of the IDPC 10 of the instant invention.
FIG. 25 is a timing diagram showing the timing relationship among the control signals received by the DPTC 56 and then subsequently generated thereby.
FIG. 26 illustrates the interprocessor interrupt scheme employed by the IDPC 10 of the present invention.
FIG. 27 is a diagram of the four-stage "delayed status" apparatus employed for the Receive Frame Status and Receive Byte Count Register and the Receive Link Address Bit Field of the Interrupt Source Register of the DLC 52.
DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT
With reference to FIG. 1, an illustrative use of an integrated Data Protocol Controller (IDPC) 10 in a terminal adapter (TA is shown). A Digital Subscriber Controller (DSC) 12 such as that described in the related, cross-referenced, co-pending patent application U.S. Ser. No. 759,622 filed July 26, 1985 and entitled "Digital Subscriber Controller" assigned to the assignee of the instant application, which application is incorporated herein by reference, is shown in FIG. 1 connected by a bidirectional bus 14 to the IDPC 10: the serial port of DSC 12 to a serial bus port of the IDPC 10. (The numeral "4" appears adjacent to bus 14 indicating that four signals are conducted in parallel on bus 14; this notational practice is used henceforth in the various drawings employed in describing the invention.) As described in the related, co-pending application, the DSC 12 interconnects the TA at an "S" interface to network terminating (NT) equipment. As such, the various D- and B-channels are demultiplexed off the telecommunications network and passed to the TA, and conversely, the separate B- and D-channels are multiplexed for transmission over the network. A bidirectional data bus 16 interconnects the DSC 12 and the IDPC 10; the data bus 16 carries B- and D-channel information between these elements as well as between a microprocessor 18, a read-only memory (ROM) 20 and random access memory (RAM) 22.
The microprocessor 18 generates lower-byte address signals conducted also on bus 16 (time-division multiplexed with the data signals) to an address latch 24 and generates upper-byte address signals conducted on a bus 26 to the latch 24. The latch then conveys this address signal via a bus 28 to the IDPC 10, the DSC 12, the ROM 20 and the RAM 22. Clock (CLK), chip select (CS), read (RD) write (WR) signals generated by the microprocessor 18 are conducted to the IDPC 10, and the DSC 12, the ROM 20 and RAM 22 via signal lines 30, 32a-d, 34 and 36, respectively. An address latch enable (ALE) signal generated by microprocessor 18 is conducted to an enable (E) terminal of the address latch 24 via a signal line 36. The meaning and operation of these signals is well known to those skilled in the art and will not be described herein.
Finally, a data link controller interrupt (DLCINT) signal and a Universal asynchronous receiver transmitter (UART) interrupt (UARTINT) signal are conducted via signal lines 38 and 40, respectively, from IDPC 10 to INT0 and INT1 terminals of microprocessor 18. Their meaning and operation will be described hereinafter.
Two line drivers 42 and 44 are shown connected to the IDPC 10 providing full duplex serial data transmit and receive functions, respectively, coupled to a UART section of IDPC 10. Various control signals are required to be conducted between the elements illustrated in FIG. 1, as will be understood by those skilled in the art, but are not shown in the interests of clarity.
The IDPC 10 is controlled by internal status and control registers which are read and written by software running on the microprocessor 18 ("local processor") connected to the IDPC 10. While the IDPC registers can be mapped into either memory 20 or 22 or to input/output devices. The IDPC 10 registers occupy a 64 byte block located in the microprocessor 18 address space. The starting address of this block is determined by address decode logic external to the IDPC 10 which is used to generate the IDPC chip select signal.
In systems containing more than one microprocessor (e.g., Personal Computer with a FPU ("host processor") and a local processor), only the local processor can access the IDPC registers. Although the IDPC 10 contains bus arbitration hardware to allow two processors to share RAM 22 on the IDPC external bus 16, there is no corresponding built-in arbitration to allow a processor other than the local processor to access the IDPC registers. Similarly, the IDPC 10 does not provide a mechanism for the local processor to access devices (including host RAM) not connected to the IDPC external bus 16.
A "host" processor can control IDPC operation indirectly, however, by issuing requests to the local processor 18. This is accomplished via Bus Arbitration (memory sharing) and Interprocessor Interrupt facilities supplied by the IDPC 10. A description of this arrangement is given below in connection with FIG. 23.
Briefly, the host processor writes a command (e.g., "Send Data on the B-Channel" and associated parameters to a set of contiguous locations of RAM 22 on the IDPC external bus 16;. This portion of RAM 22 (referred to as a "mailbox") is no different from the rest of the RAM on the IDPC external bus 16 except that the local processor 18 software "knows" that commands from the host processor will be placed at that particular address. The operation of the IDPC Bus Arbitration that allows either processor to access the mailbox is totally transparent to software. The host processor uses the IDPC Interprocessor Interrupt facility to notify the local processor that there is a command present in the mailbox. The local processor notifies the host processor of command results and status in a similar fashion, writing to pre-arranged locations in RAM on the IDPC external bus and interrupting the host processor using the IDPC Interprocessor Interrupt facility.
The four major elements internal to the IDPC 10 are shown in FIG. 2 comprising microprocessor interface (MPI) 50, a data link controller (DLC) 52, a universal asynchronous receiver-transmitter (UART) 54 and a dual-port timing controller (DPTC) 56. A signal line 57 conducts the clock signal generated by the MPI 50 to the DLC 52, the UART 54 and the DPTC 56. Bidirectional Busses 58, 60 and 62 interconnect all major blocks of the IDPC 10; the DLC 52, the UART 54 and the DPTC 56. Bus 58 conducts address signals received on a 6-conductor address signal line by MPI 50. Bus 60 conducts data signals received at an 8-conductor data signal line by MPI 50. Bus 62 conducts control signals generated by MPI 50 upon reception thereby of chip select (CS), write (WR), read (RD) signals and power down/reset (PD, RESET) signals. A more complete description of the UART 54 and the DPTC 56, including the various signal lines shown in FIG. 2 will be given in connection with FIGS. 21-25.
The MPI 50 connects the DLC 52 and UART 54 to the external microprocessor 18. The design and construction of the MPI 50 is conventional and understood by those skilled in the art. Accordingly, it will not be elaborated on herein. As will be explained hereinbelow, the DLC 52, UART 54, and DPTC 56 have user accessible registers. A 64 byte address space is subdivided by the MPI 50 into a 31 byte UART space, a 32 byte DLC space, and a 1 byte DPTC space. The address decoding of the individual spaces is performed internal to the UART 54, DLC 52, and DPTC 56. The 64 byte space is allocated as follows:
The DLC portion 52 of the IDPC 10 has the task of providing a full duplex interface (simultaneous transmit and receive) between the Serial Bus Port (SBP 104) and three internal parallel busses 58, 60 and 62 of the IDPC 10. Through the use of separate 16-byte receive and transmit first-in first-out FIFOs buffers and two external direct memory access (DMA) channels, the DLC 52 provides movement of data to and from external memory 20 and 22 and the SBP. The DLC performs low level (ISO layer 2-) bit oriented protocol processing on this data. The major protocols supported are SDLC, HDLC, LAPB (X.25), and LAPD.
FIG. 3 represents a functional block diagram of the IDPC 10 highlighting the major functional blocks of the DLC 52. The MPI 50 is shown interconnecting the external data and address busses 16 and 28 (FIG. 1) as well as the control lines 30, 32a,, 34, 36 and 38 with the internal busses 58, 60 and 62 (FIG. 2). The DPTC 56, UART 54 and DLC 52 sections of the IDPC 10 are connected to busses 58, 60 and 62. The DLC 52 portion of the IDPC 10 is shown in FIG. 3 as comprising five major functional blocks. A transmit first-in, first-out (XMIT FIFO) register 100 connected to the internal busses 58, 60 and 62. A transmitter 102 is connected to XMIT FIFO 100 and to the internal busses 58, 60 and 62 and to the Serial Bus Port (SBP) 104. A receive first-in-, first-out (RECV FIFO) register 106 is connected to the internal busses 58, 60 and 62. A receiver 108 is connected to RECV FIFO register 106 and to the internal busses 58, 60 and 62 and to the SBP 104. The transmitter 102 and receiver 108 each include status, command and control registers. All programmable registers and a portion of the FIFOs called data registers can be accessed via the busses 58, 60 and 62. These registers are mapped directly into microprocessor 18 memory space, and are described in detail hereinafter.
The Serial Bus Port (SBP) 104 receives a serial clock (SCLK) signal, a serial frame synchronization (SFS) time-multiplexed with a transmit clock (XMITCLK) and generates a serial bus output (SBOUT) signal. The description of operation of DLC 52 transmitter and receiver portions requires an understanding of bit-oriented protocols (BOPs) such as SDLC, HDLC, LAPB (X.25) and LAPD.
Bit oriented protocols provide a set of rules and techniques that facilitate the transfer of data over a communications network. This discussion will not concern the workings of the upper level of the protocols--sequence numbers, acknowledges, and the like--since these are the responsibility of the software that runs on the local processor 18. The present description concentrates on the aspects of the protocols that affect the hardware of the DLC 52.
The BOPs call for transmission of data in packets. Packets are delimited by unique Flag characters and contain an address, some control information, the data itself, and an error detection code. The address identifies the sender or the receiver of the data. The control information is used by higher levels of the protocol to manage the flow of data. The data, which is contained in the information field, is user information. Packets that are used for protocol control often omit the information field (this is the only optional field). The error detection code is a Cyclical Redundancy Check (CRC) and the DLC 52 uses the CCITT-CRC code. In addition to addresses, control, data, and error checking, the BOPs employ such mechanisms as Flags, Bit Stuffing, and Abort characters. The following section is a glossary of BOP terms and functions. These items will be used throughout the description of the DLC 52.
In the bit oriented protocol environment data is transmitted in frames. Protocols such as SDLC, HDLC, LAPB (X.25), and LAPD share the same basic frame format: ##STR1##
The eight bit Flag character is identical for all of the above mentioned protocols. It is exactly 01111110. Its bit pattern is unique within a packet because the "bit stuffing" technique (described later) used does not allow six contiguous ONEs to be present in the packet portion of a Frame. The Flag character can perform three functions: as an Opening Flag, as a Closing Flag, and as an inter-packet fill character.
The Opening Flag is defined as the last (perhaps only) Flag prior to a non-Flag, non-Abort character. (The Abort character is defined below.) All valid packets must begin with a Flag. The Opening Flag indicates the beginning of a packet. When Flags are being used as interframe fill characters, a non-Flag, non-Abort character must be received before the preceding Flag can be identified as an Opening Flag.
The principal difference between the lower levels of the various BOPs is the address field. All addresses are of an integer number of bytes in length. In general an address can be one, two, or N bytes long.
The length of an N byte long address is determined by the value of the least significant bit in each byte of the address. This bit, called the Extended Address bit (EA), identifies the last byte of the address. All of the bytes of an N byte long address will have the EA bit cleared to a ZERO except the last byte of the address. The presence of an EA bit set to a ONE indicates that the byte is the last byte of the address. The length of the address field affects the detection of a Short Frame.
In some protocols the second bit (bit 1) of the first byte of the address is used to indicate whether the frame is a command or a response. This bit, called the command/response bit (C/R), can be either a one or a ZERO without invalidating the address.
The control field immediately follows the address field. The DLC 52 treats the control field as packet data. That is, the DLC 52 does not take any action in response to the contents of the control field. The control field can be either one or two bytes long. The length of the control field has an impact on the detection of a Short Frame.
The information field, when present, follows the control field and precedes the Frame Check Sequence. The information field contains the data that is being transmitted between users. The information field contains an integer number of bytes, and can be up to 64K bytes long (minus address and control lengths) for the IDPC 10.
The Frame Check Sequence (FCS) is a 16 bit word that is produced by a CRC generator and checked by a CRC checker. Mathematically it is the ONEs complement of the sum [modulo 2] of the following: The remainder of X.sup.K [X.sup.15 +X.sup.14 +X.sup.13 + . . . +X.sup.2 +X+1] divided [modulo 2] by the generator polynomial X.sup.16 +X.sup.12 +X.sup.5 +1, where K is the number of bits in the frame existing between, but not including, the final bit of the Opening Flag and the first bit of the FCS, excluding bits inserted for transparency.
-AND-
The remainder after multiplication by X.sup.16 and then division [modulo 2] by the generator polynomial X.sup.16 +X.sup.12 +X.sup.5 +1, of the content of the frame, between but not including the last bit of the Opening Flag and the first bit of the FCS, excluding bits inserted for transparency.
The Closing Flag is the last field in the frame. It indicates the end of the frame and signals that the FCS should be checked.
A packet is a frame minus the Opening and Closing Flags.
When frames are not being transmitted over the link provided by DLC 52, the link is said to be idle. When the link is idle the DLC transmitter 102 can be programmed by microprocessor 18 to send an all ONEs pattern. This is referred to as a Mark Idle (MI) condition. Specifically, an MI is defined as at least 15 contiguous ONEs.
Prior to and between frames, back to back Flags can be transmitted over the link. This is referred to as a Flag Idle (FI) condition and is selected by microprocessor 18 program control.
The DLC receiver 108 is said to be In-frame when it is enabled and the first non-Flag, non-Abort character is received after the receipt of at least one flag. In-frame is valid until the Closing Flag is detected, an Abort character is received or an error is detected. The DLC transmitter 102 is said to be In-frame from the time that it starts to send an Opening Flag until the last bit of the Closing Flag has been transmitted, assuming that the transmitter 102 is not commanded to send an Abort sequence.
The DLC receiver 108 or transmitter 102 is said to be Out of Frame any time it is enabled and no In-frame.
Any pattern of at least seven contiguous ONE bits is said to be an Abort character. An Abort character is a physical entity, not to be confused with the Abort condition--which is an action. The Abort condition, simply called an Abort, is described below. It is important to note that there is a subtle difference between an Abort character and a Mark Idle condition. Back to back Abort characters do not necessarily constitute a Mark Idle condition. A repeating pattern of seven ONEs followed by a ZERO (111111101111111011111110 . . . ) is a series of Abort characters, but not a Mark Idle. The DLC sends at least one "01111111" when commanded by microprocessor 18 to send an Abort.
The Abort condition is an action that takes place in response to the detection of an Abort character while the DLC receiver 108 is In-frame. An Abort causes the termination and discarding of the packet being received. Aborts are asynchronous events in that they can be detected on bit boundaries as well as byte boundaries.
Zero Bit Insertion/Deletion, often referred to as Bit Stuffing, is a technique used to provide data transparency. By this is meant a method by which packet data patterns are prevented from appearing as Flags, Aborts, or Mark Idles when they appear in the received data stream. Flags, Aborts, and the Mark Idle condition all consist of six or more contiguous ONE bits. The Bit Stuffing technique examines the contents of a packet to be transmitted by transmitter 102, on a bit by bit basis, (from the first bit after the Opening Flag to the last bit of the FCS) and inserts a ZERO in the bit stream after any pattern of five contiguous ONEs, thus insuring that six or more ONEs do not appear in the data stream. The receiver 108, in turn, examines the data stream and removes the inserted ZEROs that follow five contiguous ONE bits. The implication of this is that Flag, Abort, and Mark Idle generation and detection must take place on the network side of the zero insertion and deletion units.
The BOPS specify minimum lengths for valid packets. This is usually four, five, or six bytes. Any frame that is received with fewer than this legal minimum number of bytes in its packet is called a Short Frame and is considered an error which should be discarded.
On a theoretical basis a frame can be any length greater than the specified minimum. As a practical matter, however, a maximum packet length must be set to prevent FIFOs 100 and 106 buffer overrun. This length is dynamic, and can vary on a data call by data call basis. Any received frame whose packet exceeds this maximum length is referred to as a Long Frame, and is considered an error. The detection of a Long Frame error takes place as soon as the maximum legal number of bytes has been exceeded, not when the entire frame has been received.
If a Closing Flag is detected and a non-integer number of bytes has been received, (that is to say that the character preceding the Flag contained fewer than eight bits) a Non-Integer Number of Bytes Error condition exists.
The bytes are transmitted in ascending numerical order; inside a byte, the least significant bit (bit 0) is transmitted first. However, the FCS is numbered and transmitted in reverse to this convention.
As shown in FIG. 3, the transmitter portions sections 100 and 102 of the DLC 52 reside between the off-chip memory 22 and the serial port 104 to the data communications network. The microprocessor 18, under software control, builds a data block in memory 22 that contains the address, control, and information portions of a packet. This block of data is moved, byte at a time, into the transmit FIFO 100 via either DMA or programmed I/O. The transmitter section 102 sends the Opening Flag, transmits the block of data, generates and sends the FCS (if selected), and transmits the Closing Flag. The polarity of the data stream can be inverted as it is being transmitted, if desired. Between packets the transmitter section 100 can be programmed to output an all ONEs pattern (Mark Idle), or back to back Flags (Flag Idle). The transmission of a packet can be terminated by sending an Abort sequence in response to the Send abort bit being set in the Command/Control Register (bit 0).
With reference to FIG. 4, a block diagram of the transmitter sections 100 and 102 of the DLC 52, shows the 16-byte XMIT FIFO 100 interconnecting the internal busses 58, 60 and 62 and a parallel-to-serial shift register 110. Status and control registers 112 within transmitter 102 are connected to busses 58, 60 and 62. Control signals are conducted to and from the various elements of the transmitter 102 and the status and control registers 112 on lines not shown in FIG. 4. Appendix A contains a full description of DLC status and control register.
Data signals generated by shift register 110 are conducted on line 114 to a 2:1 multiplexer (MUX) 116 which also receives via a signal line 118 signals generated by a cyclic redundancy code (CRC) generator 120 via an inverting amplifier 122. The CRC generator 120 receives the data signals on line 14 generated by shift register 110. The signals selected by 2:1 MUX 116 are conducted to a Zero Bit Insertion unit 124 via a signal line 126. The Zero Bit Insertion unit 124 generates shift clock signals conducted to shift register 110 and CRC generator 120 via a signal line 128.
A 2:1 multiplexer (MUX) 130 receives the signals generated by Zero Bit Insertion unit 124 via signal line 132 and receives a signal generated by a Flag, Abort Generator 134 via signal line 136. The signal selected by 2:1 MUX 130 is conducted to the Serial Bus Port 104 via a signal line 138. SBP 104 generates timing signals conducted on a signal line 140 to the Zero Bit Insertion unit 124 and the Flag, Abort generator 134.
The major elements of the transmitter sections 100 and 102, shown in block form in FIG. 4, will be described in greater detail in conjunction with FIGS. 5-9. With reference to FIG. 5, the transmit FIFO 100 consists of a FIFO buffer 150, a Transmit Byte Count Register 152, a Transmit Byte Counter 154, a DMA Data Request Generation logic 156 and threshold comparison logic 158.
The Transmit Byte Counter Register 152 is a read/write register and is connected to the internal busses 58, 60 and 62 and receives a LOAD signal generated by the FIFO buffer 150 via a signal line 162. It also receives a SEND ABORT signal generated by Flag, Abort generator 134 via a signal line 164. The transmit Byte Counter 154 also receives the LOAD and SEND ABORT signals and is connected to register 152 via a bus 166. Counter 154 receives a COUNT signal generated by FIFO buffer 150 via signal line 168 and a SET TAG signal generated by counter 154 is conducted to FIFO buffer 150 via signal line 170. A Transmit Byte Counter equals zero (TBC=0) signal generated by Counter 154 is conducted to Data Request Generation Logic 156 via line 170 and a threshold reached (THLD RCHD) signal generated by the threshold comparison logic 158 is conducted to logic 156 via line 172. Logic 158 is connected to the FIFO buffer 150 via a signal line 174, and is also connected to the internal busses 58, 60 and 62.
The FIFO buffer 150 is 16 bytes deep and nine bits wide (8 data bits and one tag bit, the tag indicating "the last byte of a transmit packet"). Data is loaded into the "bottom" of the buffer termed a FIFO Data Register 160 programmed by the microprocessor 18, via I/O or DMA. Data is moved therefrom up to the highest unfilled FIFO location on buffer 150 at a clock rate supplied by the microprocessor 18.
Data is unloaded from the buffer 150 by the Parallel to Serial Shift Register 110. Both loading and unloading operations are asynchronous to the microprocessor clock. The buffer 150 is cleared on Reset or when an Abort is transmitted. Associated with the buffer 150 is a Threshold Reached signal generated by the threshold comparison logic 158. This signal is active whenever the number of bytes in the buffer is at or below the threshold level stored in a FIFO Thrshold Register within status and control registers 112. The Threshold Reached signal is conducted to the Data Request Generation logic 156 as an indication that the buffer 150 should be reloaded. The Threshold Reached signal is reported in the FIFO Status Register, bit 2. A Data Request One (DRQ1) interrupt signal is generated by Data Request Generation Logic 156 when the level in the FIFO buffer 150 falls to the threshold level. DRQ1 is conducted to an external terminal of IDPC 10.
A user accessible location of the FIFO buffer 150 is termed the Data Register 160. The buffer 150 generates a status signal that reflects whether or not the Data Register is empty (available). This signal, Buffer Available, is reported in bit 3 of the Transmit FIFO Status Register (App. A). The bit is set anytime the Data Register 160 is empty, and cleared when the Data Register 160 is written AND the buffer location directly above the Data Register 160 is full. This last stipulation on the clearing of the Buffer Available bit prevents the bit from clearing, only to be reset when the Data Register is emptied on the next clock cycle.
If the Parallel To Serial Shift Register 110 attempts to unload a byte from an empty buffer, an Underrun condition exists. This causes an error to be reported via bit 4 of the Transmit FIFO Status Register. A maskable interrupt is generated by the setting of this bit. In response to the Underrun, an Abort is generated elsewhere in the DLC 52. This causes the Transmit Byte Count Register 152 and the Transmit Byte Counter 154 to be reset to ZERO as well as the FIFO buffer 150 to be cleared.
The Transmit Byte Count Register (TBCR) 152, holds the length of the packet to be transmitted (exclusive of the Opening Flag, FCS, and Closing Flag). This value is loaded into the TBCR 152 by microprocessor 18 software via the Internal Bus 58, 60 and 62. The TBCR 152 is cleared when the DLC 52 is reset or when an Abort is transmitted. When the DLC transmitter 102 is Out of Frame the contents of the TBCR 152 is loaded into the Transmit Byte Counter 154 at the same time it is written into the TBCR 152. The contents of the TBCR is also loaded into the Transmit Byte Counter when the last byte of a packet (tagged as such) is removed from the FIFO buffer 150. (This also insures that the correct value is loaded into the TBC 154 if the TBCR 152 is updated while the transmitter is In-frame). Loading of the TBCR 152 is delayed if the TBCR 152 is being written at this time.
The Transmit Byte Counter (TBC) 154 is used to count the number of bytes loaded into the buffer 150 for a given packet. The TBC 154 is loaded from the Transmit Byte Count Register 152 and decremented once for each byte loaded into the buffer 150. When the contents of TBC 154 reaches ZERO, the byte that caused the TBC 154 to reach ZERO is tagged as the last byte of the packet. This tag is created by setting the ninth bit position of that byte to a ONE. Recall that the buffer 150 159 is nine bits wide. The ninth bit position is used to hold this tag, which travels with the last data byte through the buffer 150. The tag is used to load the TBC 154 from the TBCR 152, and indicated the end of a packet to the DLC 52.
The Data Request Generation Logic 156 generates the Data Request (DRQ1) signal. DRQ1, when active, indicates to the DMA that the buffer 150 is available for the loading of data. The DRQ1 signal is activated when the TBC 154 is not ZERO -AND- the FIFO buffer 150 does not contain a tagged byte -AND- the level in the buffer 150 is below the programmed threshold (bits 3-0 of the FIFO Threshold Register). DRQ1 remains active until the TBC=0 signal is generated -OR- the buffer 150 becomes full. In this manner when the level in the buffer 150 falls to the threshold and there is more data in the packet to be loaded into the buffer 150, DRQ1 will go active. DRQ1 will remain active until the buffer 150 is completely full or the last byte of the packet is loaded into the buffer. This insures that there can never be data from more than one packet in the buffer 150 at any one time since even if the TBCR 152 is written before the last byte of the packet has been transmitted, DRQ1 will remain inactive until the tagged byte is removed from the buffer. DRQ1 is indirectly made inactive by Reset since the TBC 154 is cleared to ZERO on Reset. DRQ1 will become active in this case as soon as the TBCR 152 is written (non-ZERO).
With reference to FIG. 6, data is conducted from the Transmit FIFO 100 to the eight bit shift register 110, one byte at a time. Each byte is shifted out of the shift register 110 serially by reception of the Shift Clock, which is provided by the Zero Bit Insertion Unit 124. The signals generated by shift register 110 is conducted to the CRC generator 120, and to the 2 to 1 multiplexor 116.
The shift register 110 is responsible for generating the load control signals that effect the movement of data from the FIFO buffer 150 into the shift register 110. The first load is enabled automatically after an IDPC or DLC Reset or after the last byte of a frame (tagged as such) has left the shift register 110. The load will take place as soon as a byte of data reaches the top of the FIFO buffer. Thereafter, the shift register 110 will attempt to load itself every eighth shift clock cycle by virtue of the divide-by-eight counter 110a which generates a LOAD signal conducted to register 110, until the last byte of the packet has been loaded.
The counter 110a is held in Reset when the DLC 52 is in Reset, the transmitter 102 is Idle, transmitting an Abort, a Flag, or the FCS. When the first byte of a packet reaches the top of the FIFO buffer 150 it is automatically loaded into the shift register 110. This action is the indication to the Zero Bit Insertion Unit 124 to gate the shift clock through to the shift register 110, and remove the Reset control from the divide by eight counter 110a.
Data is shifted out of the shift register 110 on the falling edge of the Shift Clock. The Shift Clock is generated by the Zero Bit Insertion Unit 124 and runs at approximately the transmitter data rate: the Zero Bit Insertion Unit 124 increases the length of the shift clock cycle that follows five consecutive ONE bits, by a full bit time. This allows for a ZERO to be inserted in the data stream (the insertion takes place past the Serial to Parallel Shift Register 110). With the exception of changing the duty cycle of an occasional Shift Clock cycle, the zero insertion process has no effect on the operation of the shift register 110. The Shift clock is synchronous to the transmitter clock (XMITCLK). When the transmitter 102 is not shifting data out of the shift register (i.e., when the transmitter is either in Reset, Idle, sending a Flag, sending an Abort, or sending the FCS), the shift clock is blocked at the Zero Bit Insertion Unit.
The shift register 110 is cleared by a Reset or an Abort.
Referring again to FIG. 4, the CRC generator 120 produces a 16 bit word referred to as the Frame Check Sequence (FCS). The mathematical equation describing this operation is described hereinabove. Design and construction of the CRC generator 120 is well known to those skilled in the art and will not be further described herein.
The signals generated by the Parallel to Serial Shift Register 110 and the CRC generator 120 are conducted to the Zero Bit Insertion Unit 124 via the 2 to 1 multiplexor 116. During the data portion of a packet, the address, control and information fields will be referred to as the "data", the multiplexor 116 passes data from the shift register 110. After the last bit of the data portion of the packet has been shifted out of the shift register 110, the FCS is passed out of the CRC generator 120 if the CRC generator is enabled.
A 2:1 MUX 116 control signal causes 2:1 MUX 116 to select the data path from the Parallel to Serial Shift Register 110, except when the FCS is actually being transmitted.
To maintain data transparency the DLC transmitter 102 will examine the frame content between the Opening and Closing Flag (including the address, control, information, and FCS fields) and will cause the Zero Bit Insertion Unit 124 to insert a ZERO bit after all sequences of five contiguous ONEs. This is done to ensure that the Flag and Abort sequences are not simulated in the data stream. Additionally, the Zero Bit Insertion Unit 124 generates the Shift Clock, which is used by the Parallel to Serial Shift Register 110, the CRC Generator 120, and a MUX control signal generator (not shown). With reference to FIG. 7A, the Zero Bit Insertion Unit 124 consists of a three bit counter 176 and related logic.
Three-bit counter 176 receives at a count enable input the data stream on the signal line 126 generated by 2:1 MUX 116. The transmit clock (XMIT CLOCK) signal is conducted to counter 176 as well as to a clock stretcher circuit 178. The resulting counter signal is generated by counter 176 on a signal line 180 when conducts the signal to clock stretcher 178, to an input of an AND gate 182 and to a complement input of an OR gate 184. AND gate 182 also receives the data stream on signal line 126 as does OR gate 184 at a second complement input. OR gate 184 generates a signal applied at a load-to-zero input of counter 126. The AND gate 182 generates a signal conducted on line 132 to 2:1 MUX 130.
The counter 176 is automatically cleared to ZERO when it is reset. As the data stream is received on line 126, the counter 176 is incremented each time a ONE bit is detected and reset (to ZERO) when a ZERO bit is detected. In this way the counter 176 will only count up to five when five consecutive ONEs are encountered. When the counter 176 reaches five, three actions are taken: the data input to 2:1 MUX 130 is forced LOW for one cycle of the transmit clock by AND gate 182, the next Shift Clock cycle is lengthened by one cycle time by clock stretcher 178, and the counter 176 is reset. (Note that for purposes of description all action is shown related to the same clock edge, such as: the same clock edge that shifts the fifth ONE bit to the Zero Bit Inserter is shown clocking it into the counter--obviously, this creates race conditions. These can be avoided by using delayed clocks where appropriate as will be appreciated by those skilled in the art.) By forcing the data input to a LOW, a ZERO is inserted in the data stream since the transmit clock is still running. By stretching the Shift Clock, the shifting of the next bit of data (from either the Parallel to serial Shift Register 110 or the CRC Generator 120) is held off for one bit time--making room for the inserted ZERO. The counter 176 is held in Reset whenever the transmitter is sending Flags, Aborts, or is Mark Idling.
Clock stretcher 178 also receives an IN-FRAME signal from a control, not shown, and the RESET signal. The clock stretcher 178 generates the Shift Clock which is a conditioned version of the transmitter clock. The clock is conditioned by clock stretcher 178 in two ways: First, its duty cycle can be modified, as just described, to provide for ZERO bit insertion. Second, the shift clock is gated ON and OFF--selecting when data is to be shifted out of the Parallel to Serial Shift Register 110 and the CRC Generator 120. The Shift Clock is gated ON when the first byte of a new packet is loaded into the Parallel to Serial Shift Register 110 from the FIFO buffer 150. (This load is automatic and generates a control signal to the Zero Bit Insertion Unit 124. The clock remains ON until the last bit of the FCS is sent as indicated by the 2:1 MUX 116 control signal going high, or if CRC generation is not enabled (bit 5 of the DLC Command/Control Register), until the last bit of data has sent (the point at which the data/FCS MUX control would have gone low if CRC generation had been enabled. A control line (not shown) which indicates the ON or OFF state of the Shift Clock is provided to the Parallel to Serial Shift Register 110 for use by its load counter 110a.
The signal generated by AND gate 182 represents the output of the ZERO bit insertion unit 124 and is conducted to 2:1 MUX 130 that selects between the transmission of data of Flags/Aborts. The control signal for MUX 130 is generated by the Flag/Abort generator 134. The control signal causes 2:1 MUX 130 to select packet data transmission generated by the Zero Bit Insertion Unit 124 from after the last bit of the Opening Flag until the first bit of the Closing Flag. The multiplexer 130 selects the signals generated by Flag/Abort generator 134 whenever data transmission is not explicitly selected.
The Flag/Abort Insertion Unit 134 shown in FIG. 7B generates Flag and Abort characters inserted by 2:1 MUX 130 into the data stream. The unit consists of a shift register 186 which is loaded in parallel with either the Flag (01111110) or Abort (01111111) characters stored in registers 188 and 190, respectively, a divide by eight counter and the logic load shift register 192, and the control logic 194 generating the control signal to the 2 to 1 Multiplexer 130.
The shift register 186 is connected to registers 188 and 190 and can be loaded with either a Flag or an Abort character. The contents of register 186 are shifted out least-significant bit first by the falling edge of the transmit clock and serially conducted to one input of 2:1 Mux 130 via signal line 136.
The shift register 186 is loaded just prior to the transmission of a Flag or an Abort by unit 134. Flags are transmitted back to back whenever the transmitter 102 is not sending either a packet (exclusive of Opening and Closing Flags) or an Abort. Aborts are transmitted whenever the Send Abort bit is set (bit 0 in the DLC Command/Control Register (App. A)). This bit is set and cleared by software. One Abort character is also sent in response to a Transmit FIFO Underrun condition.
When an Abort is requested it is transmitted immediately. If the Send Abort bit is cleared in the middle of the transmission of an Abort character, the transmission of the Abort character will be completed before the transmission of Flag characters will commence. (Flags or Mark Idle always follow an Abort. Since the Mark Idle is inserted after the 2 to 1 Output Multiplexor 130, the Flag/Abort Insertion Unit 134 will always default to sending Flags. If Mark Idle is Selected (bit 3 of the Command/Control Register), the output of the DLC 52 will be forced to an all ONEs pattern, ignoring the Flags coming from the Flag/Abort Insertion Unit 134.)
When continuous Flags or Aborts are being transmitted, the shift register 186 is automatically reloaded after the transmission of the first Flag/Abort. This takes place every eight bit times. A divide-by-eight counter within block 192 is used to divide down the transmit clock for this purpose.
The Flag/Abort Insertion Unit 134 contains a three-bit counter which contains a user-supplied value indicating the number of residue bits in a packet. This value is transferred from a Residual Bit Control/Status Register (App.A) when the last INFO byte of a packet just prior to the FCS. The counter is decremented as each bit is shifted out of register 186. When the contents of the counter reaches zero all residual bits have been transmitted and the FCS, if enabled, and closing flag can be transmitted.
The Flag/Abort Insertion Unit 134 generates a control signal to the 2:1 Multiplexer 130, indicating whether packet data or Flags/Aborts are to be transmitted. The control signal selects the Flag/Abort path whenever the transmitter 102 is not sending packet data. Packet data is sent from the end of the Opening Flag until the beginning of the Closing Flag. A request to send an Abort (Send Abort bit or FIFO Underrun) places the transmitter 102 Out of Frame.
The Serial Bus Port (SBP) 104 receives the signal selected by 2:1 MUX 130. The SBP 104 performs several functions related to time slot assignment, clock selection, data inversion, enabling the transmitter, and Loop Back testing. FIG. 8 is a block diagram of the SBP 104.
The signal selected by Multiplexer 130 is routed through a Time Slot Multiplexer (TSM) where it is assigned one of thirty-one time slots, or transmitted as is (referred to as the non-multiplexed mode). The SBP 104 is designed to connect directly to the SBP 104 of the DSC 12 (FIG. 1). Up to thirty-one time slots combine to form a frame, where data is transmitted during one of the 8-bit groups shown in FIG. 9.
A transmit clock control 198 receives a Serial Frame Synch (SFS) signal and a Serial Clock (SCLK) signal applied to pins of the IDPC 10.
The Serial Frame Sync (SFS) signal (the SFS/XMITCLK pin serves as either the SFS input in multiplexed mode, or the transmit clock input in non-multiplexed mode) provides a reference indicating the location of the first eight bits of the frame. The transmitter time-slot multiplexer 196 can be programmed by microprocessor 18 (shown in FIG. 8 by the signal line "TIME SLOT SELECTION") to place data on any one of the time slot via bits 1 to 5 of the SBP Control Register, as described in App. A hereinafter. In the multiplexed mode a signal applied on SCLK pin provides the transmit clock source. This clock source is gated by transmit clock control 198 with the selected time slot to provide the transmit clock. If time slot 0 is selected, data is transmitted for as long as the SFS signal is active, instead of for eight bits at a time. If the SFS input is held active for 16 bit times instead of 8 each frame, the transmitter 102 will send out 16 bits per frame, as opposed to 8. By doing this the DSC 12 can place the data on both of the two B channels (on an every-other-byte basis) effectively doubling the data rate. In the non-multiplexed mode (bits 1 to 5 set to ONEs in the SBP Control Register), data is transmitted continuously. In this mode transmit clock is input on the SFS/XMITCLK pin. Data is always transmitted on the falling edge of the transmit clock.
After data has passed through the TSM 196 it is conducted to a programmable inverter XOR gate 200. If bit 0 of the SBP Control Register is set to 1, the data will be inverted by virtue of an INVERT DATA signal conducted to XOR gate 200 from Status/Control Registers 112.
Whenever the transmitter 102 is enabled (bit 1 of the DLC Command/Control Register) and is out of frame (and the Closing Flag or Abort has been sent) with Mark Idle selected (bit 3 of the DLC Command/Control Register), the transmitter's 102 output will be forced HIGH by an XOR gate 202 receiving the signal generated by the programmable data inverter 200 and a MARK IDLE signal generated by Status/Control Register block 112. The transmitter 102 is enabled and disabled via bit 1 in the DLC Command/Control Register (App. A). Whenever the transmitter is disabled, the SBOUT pin is three-stated by virtue of transistor 204 receiving the signal generated by programmable Mark Idle inserter 202, upon application of a transmit enable (XMIT ENABLE) signal. The signal conducted via transistor 204 is generated at a Serial Bus Output (SBOUT) terminal pin of the IDPC 10.
The DLC 52 can be placed in a Local Loop Back configuration for test purposes. This is done by setting bit 3 to a 1 in the SBP Control Register. Local Loop Back disconnects the SBIN and SBOUT pins (SBOUT is three-stated) and connects the transmitter 102 output and receiver input together. The selected transmitter clock describe earlier is used as the receive clock.
The DLC 52 can be placed in a Remote Loop Back configuration for test purposes. This is done by setting bit 4 to a 1 of the SBP Control Register. Remote Loop Back disables the transmitter, and echoes whatever is received at the SBIN pin out the SBOUT pin. Reference should be had to App. A for a complete description of these aspects of the IDPC 10.
Associated with the DLC 52 transmitter 102 are shown several user visible status and control registers. These registers, contained in functional block 112 are described in detail in Appendix A, are used to configure the DLC transmitter 102, instigate specific actions, report status, and generate interrupts. All of these registers can be accessed by the local microprocessor 18. None of them can be accessed by a hot processor.
Although not shown in FIG. 4, various control and status signal lines interconnect the DLC transmitter 102 elements shown there with the Status and Control Register block 112. As these signal lines are conventional, and their ability to control the elements to which they are connected is well understood by those skilled in the art. Accordingly, the design and construction of block 112, nor of the other similar control and status blocks employed by the IDPC 10, will be elaborated herein. Referring again to FIG. 3, the receiver sections 106 and 108 of the DLC 52 takes serial data from the Serial Bus Port (SBP) 104, processes it, and allows it to be moved to off-chip memory 22. Dedicated hardware modules are used to perform the bit level operations on each frame of data as it is received (Mark Idle detection, data inversion, Flag/Abort recognition, Zero Bit Deletion, CRC checking, and address recognition). The 16-Bit deep receive FIFO 106 is used as a buffer between this bit-rate-dependent processing and packet-at-a-time processing performed by the microprocessor 18. Data can be moved from the receive FIFO 106 to memory 22 either by DMA, or by microprocessor 18 control.
With reference to FIG. 10, a block diagram of the receiver sections 106 and 108 of the DLC 52, shows the 16-byte RECV FIFO 106 interconnecting the internal busses 58, 60 and 62 and three shift registers 208, 209 and 210. Status and control registers 212 within DLC receiver 108 are connected to busses 58, 60 and 62. Status and Control signals are conducted to and from the various elements of the receiver 108 and the status and control registers 212 on lines not shown in FIG. 10.
The Serial Bus Port 104 receives data signals from a Serial Bus Input (SBIN) terminal which are conducted to a shift register 212. A Flag Detect, Abort Detect Unit 214 is connected to shift register 212. The shift register 212 is connected via a signal line 216 to the shift register 210 for transference of data signals.
A recovered DATA INPUT CLOCK signal generated by SBP 104 is conducted to a Bit Delete, Byte Count, Short Frame Error Unit 218 via a signal line 220, which also receives the data signals on line 216. Shift register 212 also receives the recovered DATA INPUT CLOCK signal on line 220. A cyclic redundancy code (CRC) Checker 222 receives the data signals on line 216 as well as a clock generated by Bit Delete, Byte Count, Short Frame Error Unit 218 via a signal line 224. Shift register 210 also receives the clock signal on line 224. An address detection unit 226 is connected to registers 208 and 210.
The major elements of the receiver sections 106 and 108, shown in block form in FIG. 10, will be described in greater detail in conjunction with FIGS. 11-18. With reference to FIG. 11, the hardware blocks of the receiver 108 will be discussed in the order that data flows through the unit, from the receiver portion Serial Bus Port 104 to the RECV FIFO 106 (refer to FIG. 10). The receiver 102 must support data rates from DC to 2.048 MHz. For this reason care has been taken in the design of the receiver 108 to minimize the effects of real time events on the software that processes the received data packets. The DLC 52 of the instant invention has been designed to receive an entire packet and move it to off chip memory 22 without the intervention of the microprocessor 18, if direct memory access (DMA) is used. Packet status information is reported on a packet-by-packet basis at the time that the packet has been completely moved to memory 22. A description of this delayed status reporting mechanism is given hereinafter in connection with FIG. 27.
The receiver portion of Serial Bus Port (SBP) 104 receives serial data from the SBIN pin of the IDPC 10 and generates signals therefrom to the Flag/Abort Detection Unit 214 and the Zero Bit Deletion Unit 218. The receive-side of SBP performs three operations on the data: Mark Idle detection, programmable data inversion, and time slot demultiplexing. FIG. 11 is a block diagram of the receive-side portion of SBP 104. Data is clocked into the receive side SBP by the rising edge of a serial clock (SCLK) signal applied at a terminal pin of IDPC 10. This signal is conducted to a clock input terminal (CLK) of a Mark Idle detector 230 and to a clock input terminal of a time slot demultiplexer (TSD) 232. A transistor 234 interconnects the SBIN terminal and a signal line 236 connected to a count enable (CNT ENABLE) input terminal of Mark Idle Detector 230. Transistor 234 receives a RECEIVER ENABLE signal which causes the data signals applied at the SBIN terminal to be conducted on signal line 236. The RECEIVER ENABLE signal is generated by status and control register 212 as described in App. A.
Mark Idle detector 230 also receives at a complemented input an IN-FRAME signal, and at a complemented input the data signals conducted on line 236.
The Mark Idle detector 230 examines the data stream received via line 236 for the presence of 15 or more contiguous ONE bits, whenever the receiver 108 is out of frame. The detection of Mark Idle must take place after the receiver 108 is out of frame since a valid data pattern of 15 or more ZEROs, while In-frame on an inverted data link (inverted to all ONEs), will simulate the Mark Idle condition. The Mark Idle detection unit 230 consists of a counter that is enabled by the In-frame signal being inactive; counts each ONE bit as it arrives; is reset by each ZERO bit that arrives; generates a Mark Idle indication signal when it counts 15 ONEs and maintains that indication until a ZERO is received; is cleared by a hardware or software Reset; and is cleared and disabled when the receiver 108 goes In-frame upon reception of the In-frame signal.
The detection of a Mark Idle condition sets bit 0 in a Receive Link Status Register (App. A.). If enabled, an interrupt is generated in response to a negative-to-positive transition of this bit.
A Programmable Data Inverter comprising XOR gate 238 receives the data signals via signal line 236 and an INVERT DATA signal; the reception of which causes inversion of the received data on a bit-by-bit basis. INVERT DATA is also generated by status and Control Register 212 as described in App. A. Setting bit 0 in a SBP Control Register (App. A) causes this inversion.
Time slot Demultiplexer 232 receives the signal generated at the output of XOR gate 238 and a Serial Frame Synchronizer (SFS) signal. The Time Slot Demultiplexer (TSD) 232 can operate in one of two modes: multiplexed or non-multiplexed. Reference should now be had to FIG. 12, a timing diagram of the TSD 232. When in the multiplexed mode (selected by bits 1 through 5 of the SBP Control Register (App. A) the incoming data is valid during one of up to 31 eight-bit long time slots of a 24 bit long frame. The Status/Control Register block 212 generates a signal denoted "CHANNEL SELECT" received by TSD 232 based on bits 1 to 5 of the SBP Control Register as described in App. A. The Serial Frame Sync/Transmit Clock (SFS/XMITCLK) pin of the IDPC 10 receives the frame sync pulse (SFS) which is active for the first eight bit times of the frame and this defines the frame boundaries. The active time slot is selected by bits 1 to 5 of the SBP Control Register. Time slot 0 is treated as a special case in which data can be received more than eight bits at a time. When time slot 0 is selected data is received for as long as SFS is active. This allows, for example, 16 bits of data to be received each frame. If the DSC 12 were using both B channels to receive data belonging to the same packet (thus doubling the data rate), it would send the data to the IDPC 10 over both channels 0 and 1 of its SBP 104. With the SFS pulse lengthened to 16 bit times, the IDPC 10 would receive all 16 bits (on its channel 0) as part of the same packet.
In the non-multiplexed mode, data is received by the TSD 232 as a continuous stream, clocked by SCLK. Non-multiplexed operation is selected by setting bit 1 to 5 of the SBP Control Register (Refer to App. A). In this mode, the SFS/XMITCLK input is not used by the receiver 108 (it is used as the transmit clock input by the transmitter, thus giving separate receive and transmit clocks).
The selected data signals generated by TSD 232 are generated at a DATA output terminal of TSD 232 and the clock used, either SFS or SCLK, is generated at a RECEIVE CLOCK output terminal.
With reference to FIG. 13, the Flag/Abort Detection unit 214 includes an eight-bit shift register 240 connected to the Data Output Terminal of TSD 232. The serial receive data is shifted on the rising edge of SCLK received by register 240. The contents of the shift register 240 are tested by comparators 242 and 244, respectively, for the presence of either a Flag or an Abort character. Testing takes place every time a bit is shifted into the shift register 240. In the case of Abort detection, only the first seven bits are tested. Comparators 242 and 244 generate a signal on lines 246 and 248, respectively, indicating detection of the Flag or Abort character, respectively. Flag/Abort Detection Unit 214 also includes comparators 242 and 244 connected to shift register 240.
The Flag/Abort Detection Unit 214 generates an IN-FRAME signal received by the receive and transmit sides of SBP 104 of the DLC 52, and by the Short Frame Byte Counter 260. The IN-Frame signal is generated when a Flag Character is present in the shift register 240, eight bit times elapse, and neither a Flag nor an Abort character is then present in the shift register 240.
The contents of shift register 240 are conducted on line 216 to the Zero-Bit Deletion Unit 218. A divide-by-eight counter 250 is used to generate a byte boundary signal. The counter 250 receives the SCLK signal which it divides by eight, to produce the BYTE BOUNDARY signal. The counter 250 is reset by the receipt of a Flag detection signal conducted on line 246.
On Reset, the shift register 240 is set to all ZEROs in order to avoid false Flag or Abort detection.
In order to prevent valid data patterns from being detected as either Flags or Aborts, a technique called Bit Stuffing is used. The transmitter 102 examines the data stream between the Opening and Closing Flags (exclusive). If five consecutive ONE bits are detected, a ZERO is inserted after the fifth ONE. The Zero Bit Delection Unit in the receiver 108 removes this added ZERO. FIG. 14 shows a block diagram of the Zero Bit Deletion Unit.
With reference to FIG. 14, the Zero Bit Deletion Unit 252 of Zero Bit Deletion Byte Count and Short Frame Error Unit 218 is shown. The data received from the shift register 240 is conducted via signal line 216 to the Zero Bit Delection Unit 252. A three-bit counter 254 receives the data on line 216 as well as the RECEIVE CLOCK generated by SBP 104. Signal Line 216 is connected to a count enable (CNT ENAB) input terminal of Counter 254 as well as to a complemented clear (CLR) input terminal thereof. A COUNT NOT EQUAL TO 5 (CNT.noteq.5 signal is generated at an output of counter 254 which is conducted to an AND gate 256 as well as to a complemented clear (CLR) input of the counter. AND gate 256 also receives the RECEIVE CLOCK signal and receives at a complement input the RESET signal.
Counter 254 generates the CNT=5 signal at the presence of five consecutive ONEs in the data received on line 216. If this event occurs, the next bit is deleted from the data stream (normally ZERO). The deletion is performed by stretching the Receive Clock one clock cycle in a Receive Shift Clock signal generated by AND gate 256. The Receive Shift Clock is received by divide-by-eight counter 258 which also receives the Flag signal on line 246 and generates a Receive Character Clock (synchronized to Flag character receipt). The Receive Shift Clock and the Receive Character Clock signals are conducted to the Serial to Parallel Shift Register 210, a Receive Byte counter portion of unit 218 and the CRC Checker 222 via signal lines 224.
With reference to FIG. 15, the Short Frame Byte Counter 260 (SFBC) portion of Unit 218 includes a four-bit down counter 262 receiving at a clock input the RECEIVE SHIFT CLOCK signal that counts the number of characters that have reached the Serial to Parallel Shift Register 210. Four-bit down counter 262 also includes a register 264 storing a Minimum Packet Size value received on internal busses 58, 60 and 62. The contents of register 264 is conducted to down counter 262 where it is applied to a load terminal thereof. The counter 262 generates a COUNT NOT EQUAL TO ZERO (CNT=0) signal conducted to an AND gate 266. AND gate 266 also receives a RECEIVE BYTE COUNT GREATER THAN ZERO (RECV BYTE CNT=0) signal generated by receive 16-byte FIFO 106 and an IN-FRAME signal. If a frame ends in a Flag, AND the number of bytes received is less than the value programmed in the Minimum Packet Size Register, AND data has been placed in the FIFO (Receive Byte Counter=0), a Short Frame Error signal is generated by AND gate 266.
The CRC Checker 222 is virtually identical to the CRC Generator 120 in the transmitter and accordingly will not be further described.
FIG. 16 shows the interconnection of the Serial To Parallel Shift Registers 208, 209 and 210, the RECV FIFO 106, and the Address Detection Unit 226. The data stream, as modified by the Zero Bit Deletion Unit 252, is conducted to a 24-bit shift register comprising the 8-bit registers 208, 209 and 210 which converts the serial data stream into 8-bit bytes. The 16-bit contents of the shift registers 209 and 210 are presented in parallel to the Address Detection Unit 226 for comparison. For one byte addresses, only the first eight bits of the shift register (register 210) are compared. The contents of the shift registers 208, 209 and 210 are conducted in parallel to the Receive FIFO 106 a byte at a time. A LOAD CONTROL portion 268 of Serial to Parallel Shift Register 208, 209 and 210 generates the LOAD control signal that writes the data into the FIFO buffer 106.
Serial data is received on line 216 clocked into the shift registers 208, 209 and 210 on the rising edge of the Receive Shift Clock. The Receive shift clock is active only when data is to be shifted into the shift register. The shift registers 208, 209 and 210 have three output paths to the RECV FIFO 106. The first output path 270 moves the least significant byte (the one received first) to the RECV FIFO 106. All but the last bytes in a packet move over this path into the RECV FIFO 106. A second output path 272 and a third output path 273 are used to move the last bytes of the packet into the FIFO 106 (including the last byte of the FCS if the FCS is present in the packet).
Load control 268 receives the RECV CHAR CLOCK signal generated by SBP 104 and generates load signals on lines 274 and 276 conducted to shift registers 208, 290 and 210, and RECV FIFO buffer 106, respectively. Load Control 268 also generates a residual bit count signal which is received by a residual Bit Control/Status Register (App. A). The movement of data from the shift registers 208, 209 and 210 to the RECV FIFO buffer 106 is enabled by the rising edge of the Receive Character Clock signal generated by divide-by-eight counter 258 of the Zero Bit Deletion Unit 252. Assuming that the packet's address matched, or address detection is disabled, (Reference App. A) the load takes place on the next synchronized edge of the clock received from microprocessor 18. If the top byte of the RECV FIFO buffer 106 is not empty at the time the load is to take place the load is delayed, and retried on each successive microprocessor 18 clock cycle. If the load does not take place prior to the receipt of the next RECEIVE SHIFT CLOCK, an Overrun error occurs.
When a Packet terminates with a Flag, an Abort, or a Long Frame Error, the last byte of the packet is moved to the RECV FIFO 106 directly. At the time that the closing Flag, for example, is detected, there are still two bytes of data in the shift registers 209 and 210 and residual bits (1 to 8), if any, are located in shift register 208, left-justified. At the time the closing flag is detected, the FCS is located in the first 16 bits of the shift registers 209 and 210. The residual bits (1 to 8) are located in the last eight bits of the shift register 208 (left justified). When the closing flag is detected, the following actions take place:
The residual bit count is saved in the Residual Bit Control/Status Register;
The data in the last eight bits of the shift register 208 is then shifted until the residual bit counter reaches eight;
If the FCS is not to be placed into the RECV FIFO 106, the contents of the last eight bits of the shift register 208 are loaded into the FIFO via path 273 and tagged as the last byte in the packet; and
If the FCS is to be placed in the RECV FIFO 106, the last eight bits of the shift register 208 are loaded into the FIFO 106 via path 273, the two bytes of the FCS are moved into the FIFO 106 via paths 270 and 272, and the last byte of the FCS is tagged.
Any packet that terminates with a Flag or an Abort before any data has been loaded into the FIFO 106, the contents of the Byte Counter are ZERO, as will be described hereinafter, and in this case no data is allowed to be placed into the RECV FIFO 106. The contents of the shift registers 208, 209 and 210 is simply ignored--it will be cleared out by the first 16 bits of the next packet.
The Address Detection Unit 226 is used to identify packets that are addressed to the receiver 108. Depending on programming via Status/Control Registers 212, the first one or two bytes of each received packet is compared against up to five Address Registers (four user programmable and one broadcast). If the incoming packet's address field matches one of the Address Registers, if enabled, the packet is received. If no match occurs the packet is descarded and the receiver 108 reenters looking for a Flag state. The states which the receiver 108 can assume are described hereinafter in connection with FIG. 20.
The Address Detection Unit 226 is illustrated in FIG. 17 and includes five comparison units 278, 280, 282, 284 and 286. The first four comparison units 278-284 include a programmable 16-bit address register and a two-byte comparator. The last comparison unit 286 (broadcast) consists of register containing all ONEs and a two-byte comparator. A control element 288 receives the RECV CHAR CLK signal and is connected to an Address Control Register within element 212. Associated with each comparison unit is an enable bit that turns that particular recognition unit on or off. These bits reside in the Address Control Register (App. A). If all five enable bits are cleared (disabled) the receiver 108 will accept all packets. Bit 5 of the Address Control register selects whether the address is one or two bytes long. If one-byte addressing is selected, either the least significant eight bits of the sixteen bit Address Registers or the most-significant eight-bits, as selected by bit 7 of the Address Control Register, are used in the comparison. Also, bit 6 of the Address Control Register causes the second bit (bit 1) of the first byte of all addresses to be ignored. This is required since some BOPs use this bit position to indicate whether the packet is a command or a response (C/R). When this ignore C/R bit control bit is set, bit 1 of the first byte of all addresses is considered a don't care. Refer to App. A for a complete description of the Address Control Register.
Address comparison takes place when the Serial to Parallel Shift Registers 209 and 210 have received 16 bits following the Opening Flag. The identity of the particular comparator that makes the match with the incoming address is reported in bits 0-2 of the Interrupt Source Register described in App. A. This status is reported when the last byte of the packet is read from the RECV FIFO 106.
With reference to FIG. 18, the Receive FIFO 106 interconnects the Serial to Parallel Shift Registers 208, 209 and 210 and the Internal Busses 58, 60 and 62 and consists of a RECV FIFO buffer 290, a Receive Byte Counter 292, and a 4-stage Receive Byte Counter 294 and Data Request control logic 296.
The Receive Byte Counter 292 is a read/write register and is connected to the internal busses 58, 60 and 62 and receives a LOAD signal generated by the shift register load control 268.
The 4-stage Receive Byte Counter 294 is a read-only register and is connected to the internal busses 58, 60 and 62 and receives an END-OF-FRAME TAG signal from a data register portion 298 of FIFO buffer 290.
The END-OF-FRAME TAG signal is used by the 4-stage delayed status reporting mechanism employed by Receive Byte Counter 294 as will be explained hereinbelow in connection with FIG. 27.
The receive FIFO buffer 290 is a 32-byte deep buffer that is loaded at the "top" from the Serial to Parallel Shift Registers 208 and 210 and unloaded at the bottom via the Data Register 298 by the microprocessor 18 or DMA. (Refer to description of data movement given in connection with FIG. 16). Data is shifted down the buffer at the clock rate supplied by the microprocessor 18.
The presence of data in the Data Register 298 is indicated by the setting of the Data Available bit (bit 1) in FIFO Status Register (App. A) portion of Status and control registers 212. This bit is cleared when the Data Register 298 becomes empty and the location in FIFO buffer 290 directly above the Data Register 298 is empty.
When the receiver 108 terminates the receipt of a packet (normally or abnormally), and data from that packet has been placed in the receive FIFO buffer 290, the last byte of the packet is tagged when it is placed into the buffer. Each FIFO buffer 290 location contains a ninth bit to accommodate this tag. The presence of a tagged bit in the buffer 290 forces Data Request, described hreinafter, active.
Associated with the receive FIFO buffer 290 is the Data Request Control logic 296 which generates a Threshold Reached signal. The Data Request Control logic 296 receives a signal from FIFO buffer 290 indicating the number of bytes stored in the buffer 290. This signal is active whenever the number of bytes of data in the buffer 290 is equal to or greater than the threshold level programmably stored in a FIFO Threshold Register (App. A). When Threshold Reached is active, bit 0 in a Receive FIFO Status Register is set to 1. A maskable interrupt is generated when the Threshold Reached bit transitions from ZERO to ONE. The Threshold Reached signal is also used in the generation of Data Request to the DMA.
If the "top" location in the receive FIFO buffer 290 is full when the Serial To Parallel Shift Register load control 292 generates a load signal for a new byte of data, an Overrun condition occurs. This error is described in detail hereinafter.
Data Request Control logic 296 of the FIFO 190 generates a Data Request signal that controls the operation of the DMA (when used). Data Request signal being active informs the DMA that it should empty the FIFO buffer 290. Data Request signal goes active when the Threshold Reached signal becomes active, OR, a byte tagged as the end of a packet is present in the FIFO buffer 290. Data Request remains active until the buffer 290 becomes empty, OR, the tagged byte has been removed.
A 16-bit Receive Byte Counter 292 is provided in the receive FIFO 106 to maintain a count of the number of bytes that have been placed in the FIFO buffer 290 from the packet that is currently being received. When the last byte of the packet (tagged as such) is removed from the FIFO buffer 290 the contents of the Receive Byte counter 292 is conducted to a Receive Byte Count Register 294. This is a four stage register that delays the reporting of the byte count until the tagged byte is read from the FIFO 290--this delayed reporting opertion is described in detail hereinafter. The Receive Byte Counter 292 is cleared when its contents are loaded into the Receive Byte Count Register 294.
The Receive Byte Count Register 294 reports the length of the receive packet to software. This read only register is connected to the Internal Busses 58, 60 and 62. A description of the delayed-reporting four stage register is given hereinafter in connection with FIG. 27.
Associated with the DLC 52 receiver 108 are several user visible registers. These registers, which are described in detail hereinafter are used to configure the receiver, instigate specific actions, report status, and generate interrupts. All of these registers can be accessed by the local processors; none of them can be accessed by an off-chip host processor. Appendix A contains a description of the various DLC 52 registers.
Briefly, normal operation of the transmit-side IDPC 10 will be described by reference to FIG. 19, a transmit-side state diagram. Following hardware Reset of the IDPC 10, or when the IDPC 10 is reset by the microprocessor 18 (bit 6 of the DLC Command/Control Register within block 112), the transmitter 102 of the DLC 52 is disabled, and is in state OA300--sending Mark Idle-denoted element 300 in FIG. 19.
The microprocessor 18 initializes the DLC transmitter 102 by setting bits within transmitter status/control registers 112, described in App. A, by selecting data inversion or non-inversion (bit 0 of the Serial Bus Port (SBP) Control Register, selecting the SBP channel configuration (bits 2-1 in the SBP Control Register), selecting whether CRC generation is to be used, and selecting either Flag or Mark Idle (bit 3 of the DLC Command/Control Register, the default is Mark Idle).
The Transmit Byte Count Register 152 (App. A) is used to specify the length of the packet to be transmitted, excluding FCS bytes, and is only programmed when the packet length to be transmitted is different from the previous packet transmitted. Bytes are counted in the transmit byte counter 154 in the transmit FIFO 100 as they are placed into the transmit FIFO buffer 150. When the count equals the value programmed into the Transmit Byte Count register 152, that byte is tagged as the last non-FCS byte in the packet. Data inversion/non-inversion and SBP channel configuration do not affect the operational sequence of the transmitter 102. The Flag Idle/Mark Idle selection does affect the operational sequence and is described below.
After the DLC transmitter 102 is Reset (bit 6 of the DLC Command/Control Register, or hardware Reset), the transmitter 102 goes to state 0a 300. The transmitter will remain in state 0 until data has been placed in the transmit FIFO 100, and the first byte of that data reaches the top of the FIFO. At that time the transmitter 102 will go the state 1 (element 302).
With the transition to state 1 (302) the transmitter 102 is said to be "In-frame". In state 1 the transmitter 102 sends the Opening Flag. When this Flag has been sent state 2 (304) is entered.
While in state 2, data is unloaded from the transmit FIFO buffer 150 into the eight bit Parallel to Serial Shift Register 110. Serial data is clocked out of the shift register, through the 2 to 1 multiplexer 116, and into the Zero Bit Insertion Unit 124. The data is then fed into the Serial Bus Port (SBP) 104 where it is optionally inverted, and transmitted to the data communications network. The transmitter 102 leaves state 2 when the last byte of the packet up to the first FCS byte has been shifted out of the Parallel to Serial Shift Register 110.
If CRC generation has been selected (bit 5 of the DLC Command/Control Register) the transmitter 102 will enter state 3 (306). If CRC generation is disabled, state 4 (308) is entered directly from state 2. In state 3 the inverted contents of the CRC generator 120 is fed to the Zero Bit Insertion Unit 124 following the original packet (now completed) data stream. The inversion of the CRC generator 120 output is required by the CRC algorithm. After the 16 bits of the FCS (inverted contents of the CRC generator) have been transmitted the Valid Packet Sent bit is set (bit 4 in the Interrupt Source Register) and State 4 (308) is entered. The Valid Packet Sent indication can generate a maskable interrupt.
While in state 4 one Flag character (the Closing Flag) is transmitted. The transmitter 102 will transition to either state 0a (300) 0b (310) or 1 (302) when the transmission of the Flag completes. If data is present in the transmit FIFO 100 (a new packet), state 1 is entered. If no data is present in the FIFO 100, state 0 is entered. The selection of the Flag Idle or Mark Idle inter-frame fill (bit 3 of the DLC Command/Control Register) selects between state 0a and 0b.
There are five exceptions to the normal flow of events described above: Abort, Local Loop Back, Remote Loop Back, transmitter disabled while In-frame, and FIFO Underrun. Of these only FIFO Underrun is an error condition.
The user can terminate the transmission of a packet by requesting that an Abort be sent (bit 0 of the DLC Command/Control Register). When a Send Abort request is received the transmitter 102 enters state 5 (312) where the transmitter 102 will begin transmitting Abort characters (01111111 with 1 being the LSB). This action takes place on the next bit boundary after the Send Abort bit is set by software; the transmit FIFO 100 will be cleared. Abort characters will continue to be sent until this bit is cleared. The transmitter 102 will go out of frame when transmission of the Abort begins. When the Send Abort bit is cleared the transmitter will enter state 0b if Flag Idle is selected or data is present at the top of the FIFO (a new packet); state 0a is entered otherwise. In all cases at least one Abort character will be transmitted, even if the Send Abort bit is set and cleared by consecutive CPU instructions. (The Abort is used to tell the receiver on the other end of the link that the packet currently being received is to be terminated and discarded.) While sending an Abort has no meaning when the transmitter is out of frame (not sending a packet), the request will be honored. It will have no meaning at the receive end if the receiver is out of frame.
For test purposes the DLC 52 can be placed in a Local Loop Back mode of operation (bit 3 of the SBP Control Register (App. A). In this mode the DLC transmitter 102 is disabled at the same point that the Transmit Enable bit (bit 1 of the Command/Control Register is implemented. The DLC receiver 108 is also disabled to prevent incoming data from interfering with the Loop Back. The transmitter 102 is then connected to the receiver 108 and the transmit clock is used as the timing reference for both the transmitter 102 and the receiver 108. Packets can then be transmitted normally with the exception that nothing leaves the part. The receiver receives 108 the packet just as if it were originating from outside the IDPC 10. See App. A for loop-back operation.
Remote Loop Back, selected by setting bit 4 of the SBP Control Register, causes any activity on the SBIN input to the receiver 108 to be echoed on the SBOUT output pin. The DLC transmitter 102 is disconnected from the SBOUT pin via transistor 204. When the SBP is operating in multiplexed channel mode each received bit (conditioned by SFS/XMITCLK) is transmitted on the next falling edge of the receive clock ie., data received at the SBIN pin on the rising edge of SCLK is clocked out of the SBOUT pin by the subsequent falling edge of SCLK. When the SBP 104 is operating in the non-multiplexed mode, data bits received via SBIN (clocked in by the positive going edge of the receiver clock [SCLK]) is clocked out on a bit by bit basis using the negative edge of the same clock (SCLK). The DLC receiver 108 can still receive data while in this state.
If an attempt is made to use the DLC transmitter 102 102 while in Remote Loop Back mode, the transmitter will function normally, but no data will leave the IDPC 10.
DLC Transmitter 102 is disabled while In-Frame. The transmitter will continue to process the frame normally, and will disable the SBOUT pin as soon as the Closing Flag has been sent. Once the Closing Flag is transmitted, the transmitter 102 returns to state 0 and disconnects the SBOUT pin via transistor 204 (places it in an open drain condition with no ability to be driven low).
A FIFO Underrun occurs when the transmitter attempts to unload a byte of data from an empty transmit FIFO 100 while in frame. This condition is reported via bit 4 of the FIFO Status Register (App. A) and a maskable interrupt is generated. This causes the FIFO Status Register bit to be sent in the Interrupt Source Register (App. A) (if the Underrun interrupt has been enabled in the FIFO Status Interrupt Enable Register). When the FIFO Underrun is detected the DLC transmitter 102 enters state 6 (314) where one Abort character (01111111) is transmitted and the transmitter 102 reenters state 0.
Briefly, normal DLC receiver 108 operation will be described by reference to FIG. 20, a receive-side state diagram. Following hardware Reset of the IDPC 10 or when the bus 14 is reset by software (bit 6 of the DLC Command/Control Register), the DLC receiver 108 is disabled and is in a state 0 (316 in FIG. 20).
When the receiver 108 is disabled (by clearing bit 2 of the DLC Command/Control Register), the connection between the SBIN pin and the receiver is severed via transistor 234. This is the only effect that disabling the receiver 108 has on the remainder of the DLC 52. All other receiver functions work in the same manner as they do when the receiver 108 is on.
The user, via software running on the microprocessor 18, initializes the DLC receiver 108 by: selecting data inversion/non-inversion (bit 0 of the SBP Control Register (App. A)), specifying SBP channel configuration (bits 1 and 2, of the SBP Control Register), enabling CRC check if desired (bit 4 in the DLC Command/Control Register (App. A)), selecting the desired address mode (Address Control Register (App. A)), loading the address(es) to be recognized (Address Register(s)), specifying the minimum packet size Minimum Packet Size Register 264 (App. A)), specifying the maximum packet size (Maximum Packet Size Register (App. A)), and finally enabling the receiver 108 (bit 2 in the DLC Command/Control Register.
The DLC receiver 108 starts operation in state 0 (316). In state 0 the receiver 108 examines the incoming data stream (clocked in from the SBIN pin on the rising edge on SCLK [SCLK pin]) on a bit by bit basis for the presence of a Flag character. No data is passed beyond the Flag/Abort detection unit 214 in state 0. The detection of a Flag causes a transition to a state 1 (318).
In state 1 the data stream is inspected on a character by character basis for the presence of a non-Flag, non-Abort character (character boundaries are established by the receipt of a Flag). If the character following the Flag is another Flag, the receiver remains in state 1. If the character is an Abort, the receiver reenters state 0. If the character is not a Flag or an abort, the receiver 108 is said to be In-frame, and a state 2 (320) is entered.
In state 2 data is passed beyond the Flag/Abort detector 214 to the Zero Bit Deletion Unit 218. Here, the next bit following any five contiguous ONEs is deleted (this bit should always be a ZERO, and was inserted by the transmitter to prevent data patterns from being detected as Flag or Abort Characters--which have six and seven contiguous ONE bits respectively). The first one or two characters following the Opening Flag of the packet are normally the address field (while the address field can be more than two bytes long, the receiver 108 can examine only the first two bytes of any address--any remaining bytes are treated as data). If address recognition is enabled (bits 0-4 of the Address Control Register), these characters are tested by the address detection unit 226 for a match with one of the five enabled preprogrammed addresses (four programmable addresses and the Broadcast Address). If there is not a match, the DLC receiver 108 returns to state 0 (looking for Flags). The packet currently being transmitted is ignored and no status is reported on it. If, however, there was an address match (or address detection was disabled, in which case all frames are accepted), the frame is received and is placed into the receive FIFO 106, one byte at a time (including the Address, Control, Information, and FCS fields). Each received character is loaded into the receive FIFO 106 108 when it reaches the last eight bits of the 16 bit long Serial to Parallel Shift Register 208, 210 (with the exception of the last character, discussed below).
State 2 is exited normally whenever the Flag/Abort detector 214 receives a Flag character. If a Flag is detected the receiver 108 enters state 1. (Back to back packets can share Opening and Closing Flags.) At the time the Flag is detected, the two previous characters still in the 16 bit long Serial-To-Parallel Shift Register 208, 210 are immediately loaded into the receive FIFO 106 and the second of these two bytes is tagged as the last character in the packet. The tag makes the form of a ninth bit appended to each word in the FIFO 106. If CRC checking has been enabled (the output of the CRC comparator 222 is valid at this time), and its status (error or not) is recorded. These last two characters loaded into the receive FIFO 106 are the Frame Check Sequence (FCS) if CRC check is enabled.
When the packet has been received with either a Closing Flag, an Abort, or a Long Frame Error, its length and status are latched. This information is presented to the user when the last byte of the packet (tagged as such) is read from the receive FIFO 106 (by DMA or programmed I/O). An interrupt (maskable) indicating the receipt of a pocket, and its status, are generated at this time. The delay in status reporting is required since the user's software operates at a packet level and has not received the complete packet until the last byte has been moved from the receive FIFO 106 to memory 22. In normal operation the receive FIFO 106 is automatically unloaded by the DMA and the user is not interested in the status of a packet until it has been completely transferred to memory 22.
During the course of normal operation six error or exception conditions can occur. These are: the receipt of an Abort Character while In-frame, a CRC Error, a Short Frame Error, a Long Frame Error, a Non-Integer Number of Bytes Error and a FIFO Overrun Error. In addition to these six cases, the DLC receiver 108 can be placed in two test modes: Local Loop Back and Remote Loop Back.
When an Abort is received while the receiver 108 is In-frame (state 2), the packet is terminated. The Abort takes precedence over all receive errors. As a result of this termination several actions are taken: the contents of the 16 bit shift register 208, 209 210 is moved to the receive FIFO 106. The last byte is tagged as such as it is placed into the FIFO; the DLC receiver 108 returns to state 0; The status, including the Abort Received bit in the Receive Link Status Register (App. A) and byte count are latched; and when the last byte of the aborted packet is read from the receive FIFO 106, a maskable interrupt is generated.
When the Closing Flag of a packet is detected, the CRC Checker 222 has finished its work. If CRC checking is enabled (bit 4 in the DLC Command/Control Register), the output of the CRC checker 222 is tested at this time. If an error has occurred, this error condition is latched for delayed reporting.
When a packet is terminated (with a Flag) that has fewer characters (exclusive of Flags) than is programmed into the Minimum Receive Packet Size Register, and more than 16 bits, a Short Frame Error is reported. If the packet had 16 or fewer bits it is discarded without notification to the user. This is possible since no data has been placed into the receive FIFO 106 at this time. If the Short Frame contained more than 16 bits, it is terminated the same way that a normal packet is, with the exception that the Short Frame Error is latched for delayed reporting. The receiver 108 returns to state 1.
The DLC receiver 108 contains a Maximum Receive Packet Size Register (App. A) within block 212 which is programmed to specify the maximum acceptable packet length. If the number of bytes received equals this count and a Flag or an Abort is not detected at this time, a Long Frame Error exists and the packet is terminated. This termination is the same as for a normal frame with the exception that the Long Frame Error status condition is latched for delayed reporting.
If a flag is detected on a non-byte boundary (when from 1 to 7 bits of a character have been received), a Non-Integer Number of Bytes Error exists. The packet is terminated as normal with the exception that the short character is loaded into the receive FIFO 106 as is (it is tagged as the last byte), and the Non-Integer Number of Bytes Error status is latched for delayed reporting Note that in an alternative embodiment of the IDPC 10, the DLC 52 can receive and transmit packets containing a non-integral number of bytes.
When a byte has been shifted into the last 8 bit positions of the 16 bit shift register 208, 210 it is moved into the receive FIFO 106. There is one bit time for this operation to take place. If the top location in the receive FIFO 106 is full when this load is attempted, the load is blocked. If the top location in the FIFO 106 does not become empty before the next bit is to be shifted into the shift register, a FIFO Overrun condition exists. When this happens the packet is terminated, the last byte in the FIFO is tagged as the last byte in the packet, status is latched--including the Overrun condition indicator--for delayed reporting, and the receive returns to state 0 (if a Flag is detected at the same time as the Overrun then state 1 is entered).
For test purposes the output of the DLC transmitter 102 can be Looped Back to the receiver 108. This mode is selected by setting bit 3 in the SBP Control Register (App. A). When in the Local Loop Back mode, the receiver is isolated from its input (SBIN pin) via transistor 234.
For test purposes the input of the DLC receiver 108 can be fed directly to the output pin of the transmitter 108 (SBOUT). This mode is entered when bit 4 of the SBP Control Register is set. The operation of the receiver 108 is unaffected by this action.
FIG. 21 is a functional block diagram of the UART 54 portion of the IDPC 10 of the present invention. The UART 54 of the instant invention is compatible with the industry standard 8250 UART as described at pages 357-371 of "Communications Products Handbook" published by Western Digital Corporation, copyright 1984, which description is hereby incorporated herein, and, in addition, provides operation in a synchronous mode as well as an asynchronous mode. The UART 54 also includes a Special Character Recognition Unit and transmit and receive first-in, first-out (FIFO) registers.
As shown in FIG. 21, UART 54 includes a 10-bit receive serial-to-parallel shift register 400 connected via a signal line to a Receive Data input terminal of the IDPC 10. Receive shift Register 400 is connected to a Receive FIFO 404 via a bus 406. Data signals are received by register 400 and transferred to FIFO 404 under control of signals received from a UART control 408 which includes a set of Status and Control Registers. Receive Shift Register 400 and Receive FIFO 404 are connected to UART Control 408. Receive FIFO 404 contains a receive FIFO data register 404a located at the "top" of receive FIFO 404, i.e., that portion of FIFO 404 connected to busses 58, 60 and 62. A Parity, Special Character, Frame, Break Checker 412 is connected to Receive Shift Register 400, Receive FIFO 404 and to UART control 408. Parity, Special Character, Frame, Break Checker 412 includes a random access memory 413, as will be described in greater detail hereinafter in connection with FIG. 22.
A receive multiplexer 410 connected to UART control 408 receives Receive Clock signals on a signal line 409 connected to an input terminal of the IDPC 10. The receive clock MUX 410 has an output terminal connected to Receive Shift Register 400. A Baud Clock signal generated by a Baud Rate Generation Unit 414 is conducted on a signal line 416 to a second input terminal of receive Clock MUX 410, as well as to a first input of a transmit clock MUX 418, also receiving the Receive Clock via signal line 409 and connected to UART control 408. The output terminal of transmit clock MUX 418 is connected to a transmit (XMIT) parallel-to-serial shift register 420.
The XMIT shift register 420 receives signals via a bus 422 from a transmit (XMIT) FIFO 424 which, in turn, is connected to the busses 58, 60 and 62. The XMIT shift register 420 is connected to UART control 408, as is the XMIT FIFO 424. The XMIT parallel-to-serial shift register generates signals conducted on a signal line 426 to a XMIT Data terminal of the IDPC 10.
Transmit FIFO 424 contains a transmit FIFO data register 424a located at the bottom of Transmit FIFO 424, i.e., that portion of FIFO 424 connected to busses 58, 60 and 62.
A Parity, Frame, Break Generation Unit 428 is connected to UART control 408 and to XMIT shift register 420 and XMIT FIFO 424.
A UART Interrupt controller 430 is connected to busses 50, 60 and 62 and generates signals to UART control 408 via a signal line 432. UART control 408 receives clear to send (CTS/), data set ready (DSR/), ring indicator (RI/), and received line signal detect (RLSD/) signals conducted from an input terminal of the IDPC 10 and generates return to send (RTS) and data terminal ready (DTR) signals conducted to an output terminal of the IDPC 10.
The clocks used to transmit and receive data by UART 54 come from one of two sources: the receive clock (RXCLK) input in, or the baud rate generator 414. Clock selection is made via bits 0 and 1 in a UART Control Register within Status and Control register block 408. Appendix B contains a complete description of the registers within UART block 408. As with the DLC Status/Control Registers, various status and control signals are conducted between these registers and the UART elements shown in FIG. 21, not shown.
The baud rate generator 414 is a programmable divider that receives a signal via line 414 applied to the UARTCLK pin. Generator 414 provides a Baud clock, to the UART receiver and transmitter sections. The input clock received on signal line 414 is divided down by a programmable 16 bit (1-65536) Divider. The programmable divider is configured by loading the Divisor Latch LSB and Divisor Latch MSB Registers (App. B). These registers are accessed by setting the Divisor Latch Access Bit (DLAB), bit 7 in the Line Control Register (App. B) of control 408, and then writing the UART addresses 0 and 1 (these are the DATA Registers and Interrupt Enable Register addresses when the DLAB bit is cleared).
In the asynchronous mode the baud rate generator 414 is similarly programmed to a value 16 times the receive clock rate.
The sources of the transmitter and receiver clocks are independently selectable via receive clock MUX 410 and transmit clock MUX 418, respectively. For example: When bit 0 is set in the UART Control Register, the receiver clock MUX 410 selects the output of the baud rate generator 414 for its clock. When bit 0 is cleared, the RXCLK input is used. The same options apply for the transmitter clock MUX 418 except that in this case bit 1 in the UART Control Register (App. B) specifies the clock source.
The UART 54 has two primary modes of operation: asynchronous and synchronous.
In the asynchronous mode the receive and transmit shift registers 400 and 420 are clocked at a rate that is 16 times the baud rate. Asynchronous operation is selectable via microprocessor 18 by clearing bit 2 of the UART Control Register (App. B) of Control 408 to ZERO. As described above, the source of the clock can be either the internal baud rate generator 414 or an external input (receive clock input, RXCLK). Receive clock selection is determined by bit 0 of the UART Control Register, transmit clock selection by bit 1 of the UART Control Register.
In synchronous operation the receive shift register 400 is clocked at the same rate as the data. This means that the data and clock must be in synchronization with each other. Data is latched into the receive shift register 400 on the rising edge of the clock. Synchronous mode is selected by setting bit 2 of the UART Control Register.
The clock used by the transmit shift register 420 is also the data rate. Data is shifted out of the shift register 420 on the falling edge of the clock. The transmit clock can be provided by either the baud rate generator 414 or the external receive clock input (RXCLK).
Data is transmitted as a steady stream of bits with no framing (start and stop bits) involved. When the transmit shift register 420 is loaded, its contents are transmitted directly. The next data byte is concatenated onto the previous one. When the shift register 420 and FIFO 424 are empty the line is placed in a Marking (ONEs) condition.
Data is received on line 402 as a steady stream of bits with no framing involved, and therefore no character boundaries. As eight bits are received into the received shift register 400, they are loaded into the Receive FIFO 404. When the line 402 is idle (Marking), the receive shift register 400 is receiving (and moving to the FIFO) bytes containing all ONEs. This mode is useful in low speed synchronous applications since the end to end link--IDPC UART, to ISDN, to IDPC UART--appears as a piece of wire to the two end users. Data is sampled and transferred as long as receive clock pulses are received.
The receive shift register 400 is used to convert incoming serial data into parallel characters. The serial data is clocked into the shift register 400 by the data sample strobe signal on line 416 in asynchronous mode and the rising edge of the receive clock on line 412 in synchronous mode as selected by clock MUX 410.
Asynchronous operation--The data sample strobe signal is generated by Baud Rate Generator 414 in the following manner: Whenever the UART receiver is not receiving a character, the rising edge of the 16X clock is used to sample the receive data (RXD) input signal on line 402. If RXD has transitioned from high to low since the last rising edge of the 16X clock, a potential start bit has been detected. If the RXD signal line 402 remains low for at least three clock cycles, the start bit is assumed to be valid; if not, it is ignored. Assuming the start bit was determined to be valid, the eighth rising clock edge after the high to low transition of the RXD signal (beginning of the start bit) is used to synchronize a divide by 16 counter within Baud Rate Generator 414 that divides the 16X receive clock down to form the data sample strobe (Baud Clock) signal. The RXD signal on line 402 is then sampled by the Baud Clock once for each bit in the character to be received.
The receive shift register 400 is ten bits long permitting up to eight data bits, one parity bit, and the start bit. When the previous character is moved from the shift register 400 to the FIFO 404, or at Reset, the shift register 400 is loaded with all ONEs. Data is shifted into the shaft register start bit first (the start bit is a ZERO). When the start bit reaches the end of the shift register (bit position ten transitions from a high to a low) the character has been completely received. Note that for characters of less than eight bits (or an eight bit character without parity), the data is loaded into the shift register 400 at a bit position that is closer to the low order bit position such that the start bit will wind up in the last bit position at the end of the character. This technique eliminates the need for a counter to keep track of the number of bits received.
If the RXD signal is sampled low on the next bit time after the last bit of a character is received, a framing error exists, and is reported via bit 3 of the Line Status Register. The character with the framing error is not loaded into the FIFO 404.
When the UART 54 receives characters containing less than eight data bits, the additional high order bits in the 8 bit byte that is to be loaded into the receive FIFO ar set to ZERO.
Synchronous operation--In synchronous mode the RXD input signal is sampled on every rising edge of the 1X receive clock received on signal line 409. Data is shifted into the receive shift register 400 on every clock cycle. In this mode there are no start or stop bits. One byte of data is received and loaded into the receive FIFO 404 every eight bit times.
Received data is loaded into a four byte deep receive FIFO 404. Receive FIFO 404 is preferably of the "bubble up" type. An interrupt condition flag is set in the Interrupt Identification Register (bits 1-3) when the number of characters in the FIFO 104 has reached the level designated in the receive FIFO 404 threshold field of the UART Control Register (bits 3 and 4). Bit 3 in the UART Status Register is set when the receive FIFO 404 threshold is reached, and cleared when the FIFO 404 level falls back below the threshold. A timeout is generated internally if the number of characters received is less than the FIFO threshold level (0), and no characters have been received for 1600 baud clock cycles in the asynchronous mode, and 100 clock cycles in the synchronous mode (approximately ten character times). The timeout sets bit 0 in the UART Status Register and generates a maskable interrupt.
Data is read out of the FIFO 404, from a Receive FIFO Data Register 404a connected to busses 58, 60 and 62 by the microprocessor 18. The presence of valid data in the Receive FIFO Data Register 404a is indicated by (Receive Data Available) bit 0 in the Line Status Register.
If the receive FIFO 404 is full when a newly received character is to be loaded into the FIFO, an Overrun Error is reported via bit 1 in the Line Status Register.
With reference to FIG. 22, a parity checker 412a and RAM 413 portion of parity, special character, frame, Break Checker 412 is shown connected to the receive FIFO 404 which is ten bits wide, eight data bits, one special character flag, and one parity error flag. Parity, framing, and special character conditions are checked by element 412 when data is loaded into the FIFO 404. In particular, the presence of a character that has a parity error is reported by parity checker portion 412a, or is a special character is reported by comparison with RAM 413, in the Line Status Register. The parity error flag and the special character flag are set accordingly. Interrupts (if enabled) are generated when either condition is detected. Only the data bits can be read by the user. While Special Character and Parity Error interrupts are generated when the character is loaded into the receive FIFO 404, the Parity Error present and Special Character Available status bits (in the UART Status Register) are not set until the character is at the FIFO output 404a. This allows the user to identify which character caused the interrupt.
When the UART 54 is programmed to receive characters with fewer then eight bits, the unused bit positions are filled with ZEROs as the character is placed into the receive FIFO 404.
Special Character Recognition is performed within element 412 connected to receive shift register 400 and receive FIFO 404. When a valid character has been received by shift register 400, the lower seven bits of its bit pattern are used as a pointer into the 128 bit deep RAM 413. Bits in the 128 bit RAM 413 are set and cleared by the microprocessor 18. If the RAM bit addressed by the data is set (1), the character is flagged as "special" by the setting of bit 7 in the Line Status Register. This test is performed when the character is loaded into the receive FIFO 404. An interrupt is generated only if the special character enable bit is set (bit 5 in the Interrupt Enable Register). The special character received bit is used to identify the presence of an interrupting condition. A second bit, bit 2 in the UART Status Register, is used to identify which character in the FIFO 404 is special. This bit is not set until the character is at the output of the FIFO 404.
The special character recognition unit 412 uses the received characters as addresses into a 128 bit RAM 4B 413. The 128 bit RAM 413 is organized as 128.times.1, as seen by the special character detector, and as a 16.times.8 array as seen by the user. RAM 413 is loaded by the user by writing to one or more of the 16 registers. The first register, located at relative address 9, contains the first eight bits of the 128 bit map. Bit 0 in the map corresponds to bit 0 in the first register. Bits 15-8 are located in the second register (address 10) and so forth. The default value at Reset is all ZEROs.
Parity is checked by parity checker element 412a on all received characters as they are loaded into the receive FIFO 404. If a violation has occurred, and parity is enabled (bit 3 of the Line Control Register (App. B)), the parity error bit is set (bit 2 of the Line Status Register (App. B)). If the receiver line status interrupt is enabled (bit 2 of the Interrupt Enable Register (App. B)), an interrupt will be generated. A second status bit, bit 1 in the UART Status Register (App. B), is set when the character containing the parity error reaches the output of the receive FIFO 404. This allows the user to identify which character in the FIFO 404 contains the error. The selection of even or odd parity is made via bit 4 of the Line Control Register. The UART 54 can be placed in a test mode that forces the parity bit to be generated and then detected in the state opposite the programmed state (even or odd). This stick parity mode is invoked by setting bit 5 in the Line Control Register.
Frame errors are detected by element 412. Framing is valid only in the asynchronous mode of operation. Framing is not checked in the synchronous mode.
Bit 3 of the Line Status Register is set if the received character does not have a valid stop bit, and is not a break condition. An interrupt is generated if the line status interrupt enable bit is set (bit 2 of the Interrupt Enable Register).
Break Detection is performed within element 412. Break detection is valid only in asychronous mode. Break detection does not take place in synchronous mode.
Bit 4 in the Line Status Register is set if the receive data input is held spacing (0) for more than a full character time (start bit+data bits+parity bit+stop bits). The Receive Line Status interrupt must be enabled for an interrupt to be generated.
Data that has been transferred into the transmit FIFO 424 by the microprocessor 18 via busses 58, 60 and 62 is loaded into the parallel-to-serial transmit shift register 420 and shifted out synchronized by the transmit clocked selected by transmit clock MUX 418. Parity can be generated and appended to the data. The character length and number of stop bits are programmable via microprocessor 18. Break indications can be generated by the UART transmitter.
The shift register clock applied to transmit shift register 420 can come from either the baud rate generator 414 or the receive clock received from the input pin as selected by transmit clock MUX 418. Clock source selection is made via the transmit clock selection (bit q) in the UART Control Register. The input source for the shift register clock is 16 times the data rate in asynchronous mode, and 1 times the data rate in synchronous mode. Synchronous operation is selected via bit 2 of the UART Control Register). In Asynchronous Mode (only) the transmit logic automatically divides the clock by 16. Data is shifted out of shift register 420 on the falling edge of the clock.
Bit 6 of the Line Status Register is set when the transmit FIFO 424 is empty and the last bit has been shifted out of the shift register 420. An interrupt can be generated by this condition.
Data to be transmitted by UART 54 is loaded into the transmit FIFO 424 by the microprocessor 18. As the transmit shift register 420 becomes empty it is reloaded from the FIFO 424. When the number of bytes in the FIFO 424 is equal to or less than a programmable threshold, the Transmit FIFO Threshold Reached Bit (5) is set in the Line Status Register (App. B). An interrupt is generated (if enabled) when the FIFO level FALLS TO the programmed threshold level (the transition causes the interrupt, not the level in the FIFO 404 being at or below the threshold). The threshold is programmed via bits 5 and 6 of the UART Control Register. Parity, if selected, is generated by element 428 connected to XMIT FIFO 424 and XMIT Shift Register 420 as the data is moved from the FIFO 404 to the shift register 420.
Frame generation by element 428 takes place only in the asynchronous mode of operation. The number of stop bits and character length are programmed into the UART transmitter. These parameters also hold for the receiver. The number of stop bits is programmed in the Line Control Register bit 2. The character length is programmed by bits 0 and 1 of the Line Control Register.
Break Generation is also performed by element 428. Under control of the microprocessor 18, the UART 54 will transmit an all ZEROs "Break" pattern until the break bit is reset by the microprocessor 18. The Break request bit is bit 6 in the line Control Register. The UART 54 will wait until any character currently being transmitted is complete before transmitting a break. (A minimum of ten contiguous ZERO bits will always be sent when a break is requested.) The UART transmitter will return HIGH for at least one bit time following the transmission of a break before a new character will be sent. This allows the start bit of the new character to be detected. Break generation causes the transmit FIFO 424 to be cleared.
The UART 54 controls until Y 408 provides handshake signals for use in controlling communications between the IDPC 10 and an external terminal. These signals are: RTS/, CTS/, DSR/, and DTR/. RTS/ and DTR/ are outputs to the terminal. They are controlled by the CPU bia bits 1 and 0 in the Modem Control Register (App. B), respectively. CTS/ and DSR/ are inputs from the terminal. Their status can be read at Modem Status Register bits 4 and 5, respectively. The CTS/ and DSR/ inputs generate a modem status interrupt if they have changed since the Modem Status Register was last read. This interrupt is enabled via Interrupt Enable Register bit 3. The Delta CTS and Delta DSR bits in the Modem Status Register (0,1) reflect the fact that the status of CTS/ or DSR/ has changed since the Modem Status Register was last read. Reading the register clears these bits.
The UART 54 has four handshake lines in addition to the lines used by the IDPC. These are Ring Indicate, (RI/), Receive Line Signal Detect (RLSD/), Output 1, and Output 2. RI/ and RLSD/ are inputs to the UART 54. Their status is reported by bits 6 and 7 of the Modem Status Register, respectively. An interrupt is generated by the detection of the trailing edge of RI/ (RI/ going inactive--high). This is reported via bit 2 in the Modem Status Register. An interrupt is generated if RLSD/ changes since the Modem Status Register was last read. This Delta RLSD/ indication is reported via bit 3 in the Modem Status Register. The Output 1 and 2 signals are general purose outputs. They are controlled by setting and clearing bits 2 and 3 in the Modem Control Register, respectively.
With reference again to FIG. 2, a dual-port timing controller (DPTC) 56 is illustrated connected to the MPI 50 via a control line 57 and to the IDPC internal busses 58, 60 and 62. Also shown in FIG. 2 connected to DPTC 56 are signal lines conducting signals to and from external terminal pins of the IDPC 10. These include bus arbitration control terminals: a local processor bus request (LREQ/) input terminal, a local data transmit/Receive (LDT-R/) input terminal, a local ready (LRDY) output terminal, a host processor bus request (HREQ) input terminal, a host data transmit/receive (HDT-R) input terminal, a host ready (HRDY) output terminal, a host interrupt in (HINTIN) input terminal, a host interrupt acknowledge (HINTACK) input terminal, a host interrupt out (HINTOUT) output terminal, a local interrupt out (LINTOUT) output terminal. Also connect to IDPC 10 are a set of four host port (HPORT) control output lines, a set of three RAM control output lines and four local port (LPORT) control output lines. The HPORT lines include a Host Data Latch Enable (HDLE) output line, a host data bus enable (HDBE/) output line, a host address bus enable (HABE/) output line, and a host data laach output enable (HDLOE/) output line. The RAM control lines include a RAM Chip Select (RAMCS/) output line, a RAM write enable (RAMWE/) output line and a RAM Output enable (RAMOE/) output line. The LPORT output lines include a local address bus enable (LABE/) output line, a local data abus enable (LDBE/) output line, a local data latch enable (LDLE) output line and a local data latch output enable (LDLOE/) output line.
The signals on the various lines connected to the DPTC56 are now described more completely.
The input pin is used as the direction control for the DPTC 56 portion of the IDPC when the local processor 18 is accessing a shared RAM to be describe hereinafter in connection with FIG. 23. When this pin goes high it indicates that a write cycle to the shared RAM is in progress. As a result of LDT-R/ going high, RAMWE/ and LDBE/ are driven active (low). When LDT-R goes low it indicates that a read cycle from the RAM is in progress. At this time RAMOE/, LDLE/ and LDLOE/ are driven active low. LDT-R is returned to the inactive state on the next falling edge of CLK.
HDT-R/ functions identically to LDT-R except that it is the direction control supplied when a remote host is accessing the shared RAM.
The LREQ/ is an active low input to the IDPC 10 from the local processor 18 requesting access to the shared RAM. LREQ/ is sampled on the negative edge of every IDPC clock cycle. LREQ/ is normally active for two IDPC clock cycles. When sampled active, LREQ/ drives RAMCS/ and LABE/ active (low). LREQ/ is to be synchronous to the clock.
The HREQ signal functions identically to LREQ/ except that it comes from a remote host processor requesting access to the shared RAM and it is active high. HREQ is an asynchronous input with respect to the IDPC clock.
LRDY is an active high output from the IDPC 10 used by the local processor 18 to complete shared RAM memory cycle. LRDY is normally high. It is driven low when request for the shared RAM is received from the local processor 18(LREQ/) and the host processor is currently accessing the shared RAM.
The HRDY signal performs the same functions as the LRDY except that it is used by the host processor.
When activated LINTOUT signal intended to generate an interrupt to the local processor 18. LINTOUT goes active (high) as a result of bit 1 in a Semaphore Register being set to a 1. LINOUT is returned to the inactive state when bit 1 of the Semaphore Register is cleared to 0.
The HINTOUT pin functions similar to the LINTOUT pin but it is intended to interrupt the host processor. HINTOUT is activated by the local processor 18 writing a done into bit 0 of the Semaphore Register. HINTOUT is intended to be connected to an interrupt input on the host processor. HINTOUT is deactivated by the host pulsing the HINTACK pin which clears bit 0 of the Semaphore Register and deactivates HINTOUT.
The HINTIN is an active high input used by the host processor to generate an interrupt to the local processor 18 (LINTOUT). When HINTIN goes active it causes bit 1 of the Semaphore Register to be set to one which in turn generates LINTOUT out. This mechanism is necessary because the host cannot read/write the Semaphore Register.
The HINTACK active high input to the IDPC 10 clears bit 0 of the Semaphore Register to a zero. HINTACK is output by the host processor in response to the receipt of a HINTOUT interrupt from the IDPC.
LABE/ is driven active low by the IDPC 10 as a result of receiving an LREQ/ from the local processor 18 and is used to enable the address lines from the local processor 18. LABE/ remains active until the end of the memory cycle.
HABE/ functions identically to LABE/ except that it enables address lines from the host address latches to the memory bus and is activated by HREQ.
LDBE/ is an active low output used to enable the data lines from the local processor 18 to the shared RAM data bus. LDBE/ is driven active as a result of LDT-R/ being driven high (write cycle). It remains high until the end of the memory cycle.
HDBE/ functions identically to LDBE/ except that it enables data from the host bus onto the shared RAM bus and it is activated by HDT-R/ going high.
The LDLE active high output is used to latch data from the shared RAM to the local processor 18. LDLE is driven low (the latch is made transparent) as a result of LDT-R/ going low (read cycle). It returns active (high) at the end of the memory cycle.
HDLE functions identically to LDLE except that it latches data from the shared RAM 22A to the host processor data bus and is activated by HDT-R/ going low (read cycle).
LDLOE/ is an active low output from the IDPC 10 used by the local processor 18 to enable the output of the data bus latches back to the local processor 18. LDLOE/ is driven active (low) when LDT-R/ is driven low (read cycle). It is cleared (high) when LREQ/ goes inactive.
HDLOE/ functions identically to IDLOE/ except that it is used to enable the output of data onto the host data bus and is activated (low) by HDT-R/ going low (read cycle). It is cleared (high) when HREQ goes inactive.
RAMCS/ is an active low output from the IDPC 10 used by the shared RAM 22A as its chip select enable. It is driven active (low) when either LREQ/ or HREQ are sampled active. RAMCS/ remains active until the end of the memory cycle.
RANWE/ is an active low output from the IDPC 10 used by the shared RAM as a write strobe. It is activated when either LDT-R/ or HDT-R/ goes high (write cycle). It is deactivated at the end of the memory cycle.
RAMOE/ is an active low output signal used by the shared RAM 22A to enable its output drivers. It is driven active when either LDT-R/ or HDT-R/ is driven low (read cycle). It is cleared (high) at the end of the memory cycle.
With reference now to FIG. 23, the IDPC 10 can be used in host-based systems in which the "local" microprocessor 18 and an external "host" communicate with one another via a shared memory 22a (dual port RAM). This memory is an external shared RAM (SRAM), that can be accessed by either the microprocessor 18 or the host. The Dual Port Timing Controller (DPTC) 56 of IDPC 10 provides the control functions necessary to allow an ordinary SRAM 220 to function as a dual port device. These functions include: memory cycle timing generation, control of buffers and latches required to isolate the host's system bus 500 from the microprocessor 18 local bus and generation of the Ready control signals back to the host and the local processor.
In addition to arbitrating accesses to the shared RAM 22a, the DPTC 10 provides a semaphore mechanism (bidirectional Interprocessor Interrupts) that is used to coordinate the passing of high level messages to and from the local microprocessor 18 and the host. SRAM 22a is connected to the date and address busses 26 and 28 and receives the RAMCS/ (at CS/ terminal), the RAMOLE/ (at an OE/ terminal) and the RAMWE/ (at a WE/terminal) and WE/ generated by the DPTC 56 of the IDPC 10.
Various bus isolation devices are shown in FIG. 22. A latch 502 is placed on the data bus 26 between the SRAM 22a and the IDPC 10. Latch 502 receives the LDLE at an OE/ input and LDLE/ at an E input from the DPTC 56 of the IDPC 10. A latch 504 is placed on the data bus 26 between the IDPC 10 and the SRAM 22a receives the LDBE/ at an OE/ input from the DPTC 56. A latch 506 is placed on the address bus 28 between the IDPC 10 and the SRAM 22a receives the LABE/ at an OE/ input. A latch 508 is placed on the address bus 28 following the latch 506 between the host system bus 500 and the SRAM 22a receives the HABE/ signal at an OE/ terminal generated by DPTC 56. A latch 510 is placed on the data bus 26 following the latches 502 and 504 between the host system bus 500 and receives the HDBE/ signal at an OE/ terminal generated by the DPTC 56. A latch 512 is placed on the data bus 26 following the latches 502 and 504 between the SRAM 22a and the host system bus 500 and receives the HDLOE/ signal at an OE/ terminal and a HDLE signal at an E terminal generated by the DPTC 56.
Finally, the IDPC 10 communicates the HINTOUT, HINTIN, HINTACK, HRDY, HDT-R/ and HREQ signals to and from the host system bus 500 and the LINTOUT, LREQ/, LRDY, LDT-R1 conducted to the MCS0, SRDY and SI/ terminals of local processor 18.
With reference now to FIG. 24, a functional block diagram of the DPTC 56 of IDPC 10 shows reception and generation of the various control signals described hereinbefore in connection with FIG. 2. The operation of DPTC 56 will be described in connection with the seven major functional blocks shown in FIG. 24.
A synchronization (SYNC) block 520 receives the master clock (CLK) signal from the local processor 18, as well as the HREQ signal from the host on bus 500. The synchronization block 520 generates a host request signal synchronized with the local clock which is conducted to a conflicting request cycle arbitration block 522 which also receives the LREQ signal from local processor 18 and the CLK signal. Cycle arbitration block 522 generates a local cycle (LCYCLE) signal and a host cycle (HCYCLE) signal therefrom for use by the other functional blocks within DPTC 56. Cycle arbitration block 522 also generates a GO signal received by a RAM cycle timer block 524. RAM cycle timer block 524 also receives the CLK signal and the LDT-R/ and HDT-R/ signals, and generates therefrom the RAMOE/, the RAMCS/ and the RAMWE/ signals, as well as a STOP signal.
A local port cycle controller 526 receives the STOP signal generated by RAM cycle timer 524, the CLK signal, the LCYCLE signal and the LDT-R signal and generates therefrom the LDLE, LDLOE/, LDBE/ and LABE/ signals.
A host port cycle controller 528 receives the STOP signal, the CLK signal, the HCYCLE signal and the HDT-R/ signal and generates therefrom the HDLE, HDLOE/, HDBE/ and HABE/ signals.
A local port ready (LRDY) controller 530 receives the LREQ signal, the CLK signal, the HCYCLE signal and the LCYCLE signal and generates therefrom the LRDY signal.
A host port ready (HRDY) controller 532 receives the HREQ signal, the CLK signal, the HCYCLE signal and the LCYCLE signal and generates therefrom the HRDY signal.
Design and construction of the various blocks shown in FIG. 24 will be understood by those skilled in the art when taken with their description above as well as further description of their functioning given now in connection with the DPTC timing diagram of FIG. 25.
The DPTC 56 generates the cycle timing for all accesses to the shared RAM 22a. The length of each cycle is fixed, and is independent of the cycle times of either the local processor 18 or the host. Memory cycles are generated in response to a request form either the local processor 18 or the host. In the case of conflicting requests the DPTC 56 arbitrates the conflict, granting the first cycle to one requester while holding off the other (via the appropriate Ready line LRDY or HRDY). The DPTC 56 will always arbitrate in favor of the local processor 18 (referred to as the L-port). With reference now to the timing diagram of FIG. 25, if the L-port has a request pending (via the LREQ/ input) at the time when the cycle arbitration block 522 is ready to start the next memory cycle, at the time labelled by reference numeral 540 in FIG. 25, the L-port will be granted the cycle regardless of a request from the host (H-port). If a request from the host (HREQ input pin) is present, or becomes present during the cycle (L-cycle) time 542, the next cycle will be granted to the host (H-cycle) time 544. This takes place implicitly since the DPTC 56 will start the next cycle before the local processor 18 can request another cycle time 546. If an L-cycle request is received in the middle of an H-cycle the local processor 18 is held off (via the LRDY line) until the H-cycle has completed (time 548 through time 550).
L-cycle requests are synchronous with the IDPC clock. This is not a problem since the IDPC clock is the same as the local processor clock and the memory cycle timing is generated from the IDPC clock. H-cycle requests are assumed to be asynchronous to the IDPC clock, and are synchronized internally to the DPTC within the SYNCH block 520.
As shown in FIG. 25, the SRAM 22a memory cycle is two IDPC clock (CLK) times in length, with at least one CLD clock time dead space in between any two SRAM cycles.
While the SRAM 22a is idle the cycle arbitration block 522 of DPTC 56 samples the LREQ/ and synchronized HREQ signals on the falling edge of every IDPC clock cycle. If a request is present a cycle is started and a GO signal is generated to RAM cycle timer 524. The starting of a cycle causes the following actions to take place: RAMCS/ is driven active (low) by RAM cycle timer 524 (time 522) and either LABE/ or HABE is driven active (low) (times 554 or 556, respectively) depending on whether LREQ/ or HREQ/ was sampled.
RAMCS/ provides the chip select control output to the SRAM 22a. Both RAMCS/ and either LABE/ or HABE/ signals remain active until the end of the memory cycle times 558 or 560 respectively.
On the next falling edge of the IDPC clock (CLK) the active port's direction control input line (LDT-R/ or HDT-R) is sampled (times 562 or 564, respectively) by RAM cycle timer 524. This signal determines whether the cycle is a read or write cycle. If the direction control is sampled high (write) the following actions are taken: RAMWE/ is driven active (low) by RAM cycle timer 524 (time 566) and either LDBE/ or HDBE/ is driven active (low) (times 568 or 570, respectively) depending on whether LDT-R/ or HDT-R/ was sampled.
RAMWE/ is the SRAM 22a write strobe. It is returned to its inactive (high) state at the end of the cycle (time 572). LDBE/ and HDBE/ are the data buffer enable controls that place the data to be written into the SRAM 22a on the memory bus. They are also returned to their inactive (high) state at the end of the cycle (time 574 or 576, respectively).
If the direction control line LDT-R/ or HDT-R/ is sampled low (read), the following happens: RAMOE/ is driven active (low) by RAM cycle timer 524 (time 578); LDLE or HDLE is driven active (low) (times 580, time for HDLE omitted for clarity); and LDLOE/ or HDLOE/ is driven active (LOW) (time 582, time for HDLOE/ omitted for clarity).
RAMOE/ enables the SRAM 22a output drivers. LDLE and HDLE place the appropriate data bus latch 502 or 512, respectively, in its transparent state. LDLOE/ and HDLOE/ enable the data abus latch 502 or 512, respectively, outputs back to the local or host system bus. RAMOE/, LDLE, and HDLE are cleared at the end of the cycle (times 584, 586, respectively, time for HDLE omitted for clarity). LDLOE/ (time 588) and HDLOE/ (time omitted for clarity) are cleared when the cycle request (LREQ/ or HREQ) is removed (time 590).
The memory cycle ends on the next falling edge of the IDPC (CLK) clock (time 592).
The LREQ/ and HREQ inputs are sampled by cycle arbitration block 522 on each successive falling edge of the IDPC clock (CLK) to determine if a new cycle is to be started.
The LCYCLE and HCYCLE control blocks 526 and 528 generate the various LDLE, LDLOE/, LDBE/, LABE and HDLE, HDLOE/, HDBE/, HABE timing signals described in connection with FIG. 24.
In the event that the L-port requests a cycle while an H-cycle is in progress, or the H-port requests a cycle while either an L-cycle is in progress or an L-port request is present, a conflict occurs. The cycle arbitration block 522 of DPTC 56 will always arbitrate in favor of the L-port.
If LREQ/ becomes active while an H-cycle is in progress LRDY is driven inactive (low) by LRDY control 530. This takes place immediately. LRDY is returned active at the start of the next memory cycle (which will be an L-cycle).
The case in which HREQ becomes active while an L-cycle is in progress is handled exactly the same as above, except that HRDY is used as the control signal instead of LRDY.
The case where HREQ is active prior to the state of a cycle and LREQ/ also becomes active, causes HRDY to be driven inactive (low) as soon as LREQ/ becomes active. (If LREQ/ is already active--before the L-cycle starts--HRDY is driven inactive as soon as HREQ becomes active). HRDY is returned active when the H-cycle is started.
With reference now to FIG. 26, all communication between the local processor 18 and the host processor 595 takes place through "mailboxes" located in shared RAM 22a. A mechanism is required to inform the recipient that there is a message in his mailbox. Interrupts are used for this task.
Message passing takes two forms: local processor 18 sending to the host 595, and host sending to the local processor. When the local processor wishes to send a message to the host 595, it first places the message in the host's 595 mailbox and then generates an interrupt request to the host 595. The host 595 reads the message and clears the interrupt request. Conversely, when the host wishes to send a message to the local processor 18 it places the message in the local processor's mailbox and generates an interrupt request to the local processor 18. The local processor 18 reads the message and clears the interrupt request. The DPTC 56 provides a two-bit semaphore register 596 to facilitate the generation and clearing of these interrupt requests. The low-order bit position of semaphore register 596 (bit 0) contains an interrupt-to-host processor (ITLP) flag and the high-order bit position (bit 1) contains an interrupt-to-local processor (ITHP) flag.
The ITLP bit portion of semaphore register 596 is connected to the local processor 18 (via an external pin of IDPC 10) by a signal line 597 carrying a LOCAL INT OUT signal. The host processor 595 is connected to the ITLP bit position (via an external pin of IDPC (0) by a signal line 598 carrying a HOST INT IN signal. The local processor 18 can write a LOCAL IN CLR signal to bit 1 of register 596 and a HOST IN REQUEST signal to bit 0 of register 596 via the MPI 50.
The host 595 is connected to the ITHP bit position of semaphore register 596 (via an external pin of IDPC 10) by a single line 599a carrying a HOST IN ACK signal and (via an external pin of IDPC 10) by a signal line 599b carrying a HOST IN OUT signal.
The Semaphore Register 596 can be read and written by the local processor (but not by the host). Local processor-to-host interrupt--The local processor 18 generates an interrupt to the host 595 by writing a ONE to bit 0 in the Semaphore Register 596. The setting of this bit activates the host interrupt output (HINTOUT pin). The host 595 clears the bit, and therefore the HINTOUT pin, by pulsing the host interrupt acknowledge input (HINTACK pin).
Host-to-local-processor interrupt--The host 596 generates an interrupt to the local processor 18 by pulsing the host interrupt input (HINTIN pin). This sets bit 1 in the Semaphore Register 596 and activates the local interrupt output (LINTOUT pin). The local processor clears the interrupt request (generated by the LINTOUT line) by clearing bit 1 in the Semaphore Register.
The IDPC 10 of the present invention contains a number of registers into which user-definable data can be written and/or from which data can be read. The DLC 52 transmitter 102 has a set of status and control registers (11, FIG. 4), the DLC receiver 108 has a set of status and control registers (212, FIG. 10), the UART 54 has a set of status and control registers (408, FIG. 21) and a set of special character bit map registers within element 412 and the DPTC 56 has a single semaphore register. These registers are associated with various aspects of each of these three major functional blocks of the IDPC 10, as will now be described.
The user accesses the various status and control registers and the semaphore register 596 via microprocessor 18 by supplying an address to the MPI 50 according to the following memory map:
Status and control registers listed in Table I below are contained within the DLC 52 in blocks 112 and 212 and are used to establish the required modes and configurations of the DLC transmitter 102 and receiver 108 as well as monitoring and reporting the necessary status of the DLC 52 to the user. The status and control registers used for the DLC FIFOs 100 and 106 and Serial Bus Port (SBP) 104 are also listed in Table I. These rgisters occupy the first 29 locations in a 32 byte DLC address space. This space starts at location 00 in the Internal Memory Map.
Prior to discussing the details of the individual registers listed below in Table I, the following section describes two DLC registers and a bit field in a third register which differ from the other user-accessible DLC registers.
The Receive Frame Status Register, Receive Byte Count Register, and the Receive Link Address Bit field (bits 0-2) of the Interrupt Source Register support the reception of multiple contiguous frames (back-to-back frames). These two registers and the bit field of the third register must maintain a "history" of the status (good or bad frame) and byte count of up to two previously received frames while a third frame is actually being received by the DLC 52. These registers and the bit field are four stage registers to support multiple levels of status from frames received by DLC 52.
Each of the Receive Frame Status Register, Receive Byte Count Register and the Receive Link Address Bit Field are comprised of the following four stages: (1) Current, (2) Holding, (3) Master, and (4) Slave. A typical four-stage "delayed-status" structure used for the Receive Frame Status Register is shown in FIG. 27. The FIG. 27 illustrates a typical interconnection as will be described hereinafter.
With reference to FIG. 27, the flag detector 214 of DLC receiver 108 is connected to an AND gate 600 as is the eight-bit minumum (receive) packet size register 264 (together representing "stage 1.infin.). (Although only one AND gate 600 is shown in FIG. 27, eight such gates, operating in parallel and each connected to the flag detector, are employed). The signals generated by AND gates 600 are conducted to an eight-bit latch 602, receiving at a reset (R) input the IN-FRAME signal. The outputs of latch 602 are conducted to a set of (eight) AND gates 604, each also receiving an OUT-OF-FRAME signal and an EMPTY signal generated by an eight-bit ("stage 2") register 606. Register 606 receives the eight signals conducted in parallel from AND gates 604.
Register 606 is, in turn, connected at its outputs to a set of (eight) AND gates 608, each also receiving an EMPTY signal generated by an eight-bit ("stage 3") register 610. Register 610 is, in turn, connected at its outputs to a set of (eight) AND gates 612, each also receiving an EMPTY signal generated by an eight-bit ("stage 4") register 614. Register 614, is, in turn, connected at its outputs to a set of (eight) AND gates 616 each also receiving a signal from bit 5 of a Receive Frame Status Interrupt Enable Register (typical of other bit positions within the register). The outputs of AND gates 616 are conducted in parallel to an OR gate 618. The single output generated by OR gate 618 is conducted to bit position five of an Interrupt Source Register 620, which is, in turn, connected at its output to an AND gate 622. AND gate 622 also receives a signal from bit 5 of an Interrupt Source Interrupt Enable Register. The signal generated by AND gate 622 generates a DLC interrupt signal.
Stage 1 (602) contains the current status of the frame presently being received by the DLC 52. This stage is updated with the current DLC receiver status as changes occur in real-time. The contents of Stage 1 is transferred to Stage 2 (606) via gates 604 when Stage 2 is empty and an event occurs that caused a byte to be tagged as the End-of Frame (EOF) byte as it enters the DLC Receive FIFO 106 as described hereinabove in connection with FIG. 18. If Stage 2 is not empty (e.g., contents not yet transferred to Stage 3), then Stage 1 will retain its status. When Stage 1 is transferred to Stage 2, Stage 1 is free to begin monitoring the next frame that arrives. Stage 2 then holds the data until Stage 3 is empty. Data is transferred from Stage 2 to Stage 3 as soon as Stage 3 becomes empty. This, in turn, allows transfer of data from stage 1 to Stage 2 at the EOF condition.
The contents of Stage 3 register 610 is transferred to Stage 4 register 614 (which is the register accessible by the user) when Stage 4 is empty and the EOF-tagged byte is read (by DMA or the microprocessor 18) from the Receive FIFO Data Register 298. If Stage 4 is not empty, then Stage 3 will retain its status. Stage 4 is cleared ("emptied") when read by microprocessor 18 or when DLC 52 Reset occurs.
Received frame status can "back up". If microprocessor 18 has not read Stage 4 when an event occurs that would cause Stage 3 to be transferred to Stage 4, Stage 3 is not transferred to Stage 4. There is no problem if Stage 4 is emptied before an event occurs which would cause Stage 1 to be transferred to Stage 2. In this case, Stage 3 is transferred to Stage 4 as soon as Stage 4 is emptied. However, with both Stages 2, 3, and 4 non-empty when an event occurs that would result in Stage 1 being transferred to Stage 2, existing Stages 1, 2, 3, and 4 are not disturbed. The DLC Receiver 108 begins ignoring all received link bytes, freezing Stage 1. Any frames which are transmitted to the DLC receiver are therefore lost until Stage 4 is read by microprocessor 18. As soon as Stage 4 is emptied by a microprocessor read, Stage 3 is transferred to Stage 4, Stage 2 is transferred to Stage 3 and Stage 4, Stage 2 is transferred to Stage 3 and Stage 1 is transferred to Stage 2. At this point, the DLC Receiver 108 logic enters Receiver State 0 (Hunt for Flag) and frame reception can begin again.
The valid and invalid packet received bits (3,5) of the Interrupt Source Register are also reported in a delayed fashion. These bits can be built from the other delayed status conditions and do not themselves require four-stage mechanism.
If Receive Frame Status Register has not been read since the Interrupt Source Register was last read, and the least significant bit of the Receive Byte Count Register is read, the Receive Status Register will be cleared. In this manner, the four-stage delayed status mechanism remains synchronized if a valid data packet is received and the Receive Status Register is not read.
The DLC 52 contains a number of registers within the transmitter status and control registers block 112 (FIG. 4) and the receiver status and control registers block 212 (FIG. 10). These registers are listed in Table I.
Appendix A contains a description of the DLC status and control registers listed in Table I.
The DLC registers fall into five categories, command/control, status, FIFO data, interrupt identification, and interrupt enable registers.
DLC command/control registers--The command/control registers are used to configure the DLC, and to request specific actions. These include:
DLC Command/Control Register;
Link Address Control Registers (4);
SBP Control Register;
Minimum Receive Packet Size Register;
Maximum Receive Packet Size Register;
FIFO Threshold Register; and
Transmit Byte Count Register.
The DLC Command/Control Register controls the operation of the entire DLC. The other registers each control the actions of a specific portion of the DLC. The bit assignments are not critical in these registers.
DLC status registers--The DLC status registers report the state of the DLC to the user. These include:
FIFO Status Register;
Receive Byte Count Register;
Receive Frame Status Register;
Receive Link Status Register; and
Portions of the Interrupt Source Register.
The status registers are organized to group status information according to type. This is important since this is the way that the software interrupt handling routines will tend to be organized. For example, status information that pertains to the real time condition of the communications link is reported separately from information specific to a particular received frame of data. In general, the software is interested in the status of packets, not portions of packets--this is the key, the DLC reports status to the user only after the packet has been moved from the IDPC into external RAM. Traditionally, the user was involved in either the status of data on a character by character or several character at a time basis, not on a packet at a time basis. This status structure is unique to the IDPC.
The bits inside the various status registers are organized with the most probable condition in the LSB position and the least probable condition in the MSB position. This reduces the software overhead in identifying a given condition. Further, the most likely status conditions (and the identification of the address associated with the packet in question) are reported in the Interrupt Source Register. This is the first register that a user will read after receiving an interrupt. Under all normal conditions, the user need access no other register to identify the status of the DLC.
FIFO data registers--These are the registers that the user reads or writes to move data to and from the DLC (FIFOs).
Interrupt identification register--The Interrupt Source Register contains three bit fields, the packet address identification field, the valid packet field, and the interrupt source field. The first two fields were discussed above. The interrupt source field has one bit for each of the status registers. When this bit is set, the associated register contains the interrupting condition. In this manner, the user can efficiently locate the cause of the interrupt.
By way of example: To identify that a valid packet has been received, the IDPC requires only a read to the Interrupt Source Register, and a shift right and test instruction--a total of two instructions. If a less optimum organization were used, as many as 17 instructions could have been required.
Interrupt enable registers--These registers are bit-for-bit matches of the status registers. This provides a user friendly organization for interrupt enabling. Extra registers are required by this scheme, but the result is clearer for the user.
Table II lists the 12 user-accessible status and control registers in the UART 54 plus a 128 bit bit-map, addressed as 16, 8 bit registers corresponding to the random access memory 414 of the parity, Special Character, Frame, Break Checker 412. The UART registers are mapped into a 31 byte space. The two baud rate divisor registers overlap the FIFO Data Registers and the Interrupt Enable Register Addresses. Access is gained by setting the Divisor Latch Access Bit (DLAB) in the Line Control Register. The base address of the 31 byte block is indicated in the memory map presented earlier.
Appendix B contains a description of the UART status and control registers listed in Table II.
UART registers--The UART registes are identical to those defined in the 8250, with the exception of the bits required to control and report status on the features added to the 8250 (special character recognition, FIFOs, synchronous operation, etc.). The trick here is to be exactly compatible with the 8250, while providing the new capabilities cleanly. The UART Status, and UART Control registers are new to the basic 8250. Additional bits have been added to unused positions in existing 8250 registers (identified in the UART register section of the FPS). The positions of these added bits is important to direct the interrupt source identification process in a logical manner.
The DPTC 56 contains one user-accessible register. This register is used by the local processor 18 to control the generation and clearing of semaphore interrupts between the local processor 18 and the host processor 595. This DPTC register is described hereinabove in connection with FIG. 26. The DPTC register (Semaphore Register 596) is mapped into address 63 decimal.
APPENDIX A
DLC 52 Status/Control Registers (112,212)
COMMAND/CONTROL REGISTER is an eight-bit register. All bits in this register are set and cleared by software except when initialized to default values as a result of DLC Reset as described hereinbelow or IDPC Reset Pin as described hereinbelow. This register can be written to and read from by the local processor 18.
DLC ADDRESS CONTROL REGISTER is an eight-bit register. All bits in this register are set and cleared by software except when initialized to default values as a result of DLC Reset described in connection with DLC Command/Control Register or IDPC Reset Pin. This register can be written and red by the microprocessor 18. When all Link Address Enable bits (bits 0-3) and the Broadcast Enable bit (bit 4) are cleared to ZERO, the DLC will perform no address detection and pass all received frame bytes (assuming more than two frame bytes are received) to the DLC Receive FIFO 106 (FIG. 10). In this case, bits 5, 6 and 7 of this register are ignored.
If one or more of bits 0-4 are set to one, then a successful link address compare described in connection with Address Detection Unit 226 (FIG. 16) must occur before any frame bytes can be transferred to the DLC Receive FIFO 106.
SERIAL BUS Port (SBP) CONTROL REGISTER is an eight-bit register. All bits in this register are set and cleared by software except when initialized to default values as a result of DLC Reset or IDPC Reset Pin. This register can be written and read by the local microprocessor 18.
MINIMUM RECEIVE PACKET SIZE REGISTER is an eight-bit register (264) FIG. 15. Default=Hex 5. Bits 0-3 of this register are set and cleared by software except when initialized to the default value of 5 as a result of DLC Reset or IDPC Reset pin. Bits 4-7 are not used. This register can be written and read by the local microprocessor 18.
This register indicates the minimum length packet (exclusive of Opening and Closing Flags) that can be received by the DLC without generating a "Short Frame" error in the Receive Frame Status Register.
At the time that the Short Frame Interrupt is generated, the contents of the Receive Byte Count Register reflects the number of bytes in the Short Frame. ##STR7##
MAXIMUM RECEIVE PACKET SIZE REGISTER is a 16-bit register. Default=Hex 0000.
The 16 bits of this register are set and cleared by software except when initialized to the default value as a result of DLC Reset or IDPC Reset pin. This register can be written and read by the local microprocessor 18.
This register indicates the maximum length packet (exclusive of Opening and Closing Flags) that can be received by the DLC without generating a "Long Frame" error in the Receive Frame Status Register. As each packet byte is received, the contents of the Maximum Receive Packet Size Register are compared with the Receive Byte Counter 292 (FIG. 18). If the maximum packet size is exceeded in the Receive Byte Counter, a "Long Frame" error is generated in the Receive Frame Status Register. At this point, the received byte that caused the Receive Byte Counter 292 to exceed the maximum length is tagged as the End-of-Frame (EOF) byte and the DLC receiver enters receiver state 0 (Hunt for Flag). ##STR8##
DLC INTERRUPT ENABLE REGISTERS
Interrupt Source Interrupt Enable Register (Default=Hex 0000)
Receive Frame Interrupt Enable Register (Default=Hex 0000)
Receive Link Interrupt Enable Register (Default=Hex 0000)
FIFO Status Interrupt Enable Register (Default=Hex 0000)
All bits in these registers are set and cleared by software except when initialized to default values as a result of DLC Reset or IDPC Reset Pin. These registers can be written and read by the local microprocessor 18.
The last three enable registers are bit-for-bit images of the corresponding Receive Frame Status Register, Receive Link Status Register, and FIFO Status Register, respectively, described hereinbelow. The Interrupt Source Interrupt Enable Register is an image of the corresponding Interrupt Source Register described hereinbelow except for bits 0-2, which have no interrupts associated with them.
The last three enable registers form the lower level of a two-level interrupt enable mechanism used for the corresponding three status registers. The three bits in the Interrupt Source Interrupt Enable Register that correspond to these three status registers form the higher level of the two-level enable mechanism. For example, in order for the Short Frame error interrupt to be enabled, the Short Frame bit must be set to one in the Receive Frame Interrupt Enable register (lower-level enable) AND the Receive Frame Status bit must be set to one in the Interrupt Source Interrupt Enable Register (higher-level enable).
When an event occurs that causes a bit to be set in one of the three status registers (reference the descriptions of the three status registers) and both levels of status interrupt enable are set to ONE, the DLC interrupt is generated and the bit for that register is set to ONE in the DLC Interrupt Source Register. If the status register bit is set to ONE and either interrupt enable level is not enabled, no interrupt is generated and the Interrupt Source Register bit for that status register is not set to ONE. *The Transmit Threshold Reached interrupt described in connection with FIG. 5 (bit 2 in the FIFO Status and Enable Registers) described hereinbelow, differs in the following way. The threshold reached bit reflects the actual real time condition of the FIFO (above, equal to or below the threshold). The interrupt, however, is generated only when the level in the FIFO fails to the threshold level. This prevents the generation of an interrupt when the FIFO is empty because the transmitter is not in use.
A software read of any of the three status registers clears the status register to ZERO and clears the interrupt condition caused by bits being set to ONE in that status register. A DLC Reset or activation of the IDPC Reset Pin also has this effect.
In contrast to the interrupt enable mechanism used for the three status registers, the Valid Packet Received and Valid Packet Sent bits in the Interrupt Source Register can generate an interrupt through a single level interrupt enable mechanism. When an event occurs that causes either of these bits to be set in the Interrupt Source Register, if the corresponding Interrupt Source Interrupt Enable Register bit has been set to one, the DLC interrupt is generated. When either of these two Interrupt Source Register bits is set to one and the corresponding interrupt enable register bit is not set to one, no interrupt is generated. ##STR9##
TRANSMIT BYTE COUNT REGISTER (152) is 16-bit register. Default=0
Bits 0-15 of this register are set and cleared by software except when initialized to the default value as a result of DLC Reset, IDPC Reset Pin or when an Abort is issued by Flag/Abort Insertion Unit 134 and conducted via signal line 164 (FIG. 5). This register can be written or read by the local processor 18.
Software writes this register with the count of bytes to be transmitted in each frame, NOT including Opening Flag, Closing Flag, and FCS (CRC) bytes. Software only writes this register when the count of bytes to be transmitted is different from the count currently in this register.
The contents of this register are transferred to the Transmit Bytes Counter 154 (FIG. 5) whenever software writes this register (if the transmitter is out-of-frame) or when an End-of-Frame (EOF) tagged byte is loaded from the transmit FIFO 100 into the Parallel to Serial Shift Register 110. If software is writing this register when the EOF-tagged byte is loaded, the transfer to the Transmit Byte Counter is delayed until the software write is complete. ##STR10##
FIFO THRESHOLD REGISTER is an eight-bit register. The 8 bits of this register are set and cleared by software except when initialized to the default value as a result of DLC Reset or IDPC Reset. This register can be written or read by the processor 18.
INTERRUPT SOURCE REGISTER (620) is an eight-bit register. The Interrupt Source Register contains the status information most important to the user during normal operation. The intent of this register is to narrow down what caused a DLC interrupt in as few steps as possible. This register is a read only register.
This register is initialized to the default value shown below for each individual bit and bit field as a result of DLC Reset or IDPC Reset Pin.
Note: Bit 3 and Bit 5 are a special case of the four stage status reporting mechanism described in connection with FIG. 27. These two bits do not need to be implemented in Stages 1, 2, and 3; instead, they can be generated in Stage 4 from other Stage 4 bits as follows:
Bit 5 (Receive Frame Status) can be updated by DLC hardware as the logical OR of the six bits of the Stage 4 Receive Frame Status Register described hereinbelow. Bit 3 (Valid Packet Received) can be updated as the logical NOT of bit 5 at the same time bit 5 is updated.
RECEIVE BYTE COUNT REGISTER (294) is a 16-bit register. Default+0
This 16 bit register indicates the number of bytes received in a packet (i.e., between but not including Opening and Closing Flags) whether the packet was received in error or not. The receive byte counter 292 is incremented when a byte of data is placed into the receive FIFO 290. The Receive Byte Counter register is one of the unique Four Stage Status Registers and Bit Field entities described in connection with FIG. 27. This register is a Stage 4 register and is therefore loaded with a valid byte count only when both of the following events have occurred:
(1) Stage 4 is cleared by a software read of this Receive Byte Count Register and
(2) The End-of-Frame (EOF) tagged byte is read from the receive FIFO 290 (by DMA or software).
This register is reset to its default value of 0 when DLC Reset is executed or the IDPC Reset pin is activated. This register is a read only register from the local processor 18. ##STR15##
RECEIVE FRAME STATUS REGISTER is an eight-bit register. The bits of this register are set to ONE as described below. Bits 6 and 7 are not used. This register is a read only register for local processor 18.
The setting of any bit in the Receive Frame Status register will set bit 5 of the Interrupt Source Register if the corresponding enable bit is set in the Receive Frame Interrupt Enable Register and the Receive Frame Status bit is set in the Interrupt Source Interrupt Enable Register as described hereinbelow in connection with the Interrupt Source Register 620.
The bits of the Receive Frame Status register are all cleared to ZERO (default bit settings) when DLC Reset is executed, the IDPC Reset Pin is activated or the register is read and the hardware condition that set the bit no longer exists.
The register indicates which error or exception condition has occurred during the reception of a frame. This register is one of the unique "Four Stage Status Registers and Bit Field" entities described in connection with FIG. 27. This register is a Stage 4 register and is therefore loaded (except during DLC Reset or IDPC Reset) only when both of the following events have occurred:
1. Stage 4 is cleared by software read of this Receive Frame Status Register and
2. The End-of-Frame (EOF) tagged byte is read from the receive FIFO 290 (by DMA or software).
The Receive Frame Interrupt Enable Register is a bit-for-bit image of the Receive Frame Status register.
RECEIVE LINK STATUS REGISTER. Each of the bits in this register are individually set to ONE or cleared to ZERO by the DLC to indicate the real-time state of the the various status conditions they represent. Bits 3-7 are not used. Setting any bit in this register will set bit 7 of the Interrupt Source Register if the coresponding enable bit is set in the Receive Link Enable Register and the Receive Link Status bit is set in the Interrupt Source Interrupt Enable Register. Upon completion of the DLC Reset or IDPC Reset, the bits in the Receive Link Status register will be set/cleared to their default condition as a result of the Resetting of the portion of the DLC that they monitor.
The Receive Link Interrupt Enable Register described hereinabove is a bit-for-bit image of this register.
FIFO STATUS REGISTER. Each of the bits in the FIFO Status register are set to ONE or cleared to ZERO by the DLC to indicate the real-time state of the various status conditions they represent. Bits 5-7 are not used.
Upon completion of DLC Reset or IDPC Reset pin, the bits in this register will be set cleared to their default condition as a result of the Resetting of the portion of the DLC that they monitor.
The FIFO Status Interrupt Enable Register described hereinabove is a bit-for-bit image of the FIFO Status register. Setting any bit in the FIFO Status register will set bit 6 of the Interrupt Source Register if the corresponding enable bit is set in the FIFO Status Interrupt Register and the FIFO Status bit is set in the Interrupt Source Interrupt Enable Register.
DLC FIFO DATA REGISTERS
DLC Receive FIFO Data Register 298.
DLC Transmit FIFO Data Register 160.
Each of these registers is eight bits long.
The Receive FIFO Data Register 298 is read by DMA or software to remove one byte from the Receive FIFO 290.
The Transmit FIFO Data Register 160 is written by DMA or software to load one byte to the Transmit FIFO 150.
APPENDIX B
UART 54 Status/Control Registers (408)
RECEIVE FIFO DATA REGISTER 404a. The receive FIFO Data Register 404a (FIG. 21) (read only) is the output side of the receive FIFO. Data received by the UART 54 is read from the Receive FIFO 404, by the processor 18. The register is eight bits wide. Bit 0 corresponds to the least significant data bit, which is the first bit to be transmitted or received. The default value at Reset is all ZEROs.
TRANSMIT FIFO DATA REGISTER 424a. The Transmit FIFO Data Register 424a (FIG. 21) is a write only input to the transmit FIFO 424. Data placed in this eight bit wide register is transmitted out of the transmit FIFO 424 least significant bit first (bit 0). The default value at Reset is all ZEROs.
BAUD RATE DIVISOR LEAST-SIGNIFICANT BYTE AND MOST-SIGNIFICANT BYTE REGISTERS. These two eight-bit registers contain the low order and high order eight bits of the number by which the UART clock input (UARTCLK) is to be divided by Baud Rate Generator 414. Bit 0 of each register is the least significant bit of each byte. The default value at Reset is all ZEROs. When the two registers are combined the divisor is as follows:
Divide by 1 passes the UARTCLK through unaffected. This allows the receiver and transmitter to operate off of separate external clocks.
Any write to either the MSB or LSB Divisor Registers causes the baud rate generator 414 to be loaded with the 16-bit value stored in the Baud Rate Divisor Registers.
INTERRUPT ENABLE REGISTER. The Interrupt Enable Register is an eight-bit read/write register used to enable specific interrupt sources. Setting a specific bit to ONE enables its corresponding interrupt. The default value at Reset is all ZEROs. Resetting a bit to ZERO disables the interrupt and resets the interrupt pin if the corresponding condition is present.
INTERRUPT IDENTIFICATION REGISTER. This is a four-bit read-only register used to identify which UART status register contains an interrupting condition. Unused bit positions (7-4) contain ZEROs when this register is read.
LINE CONTROL REGISTER. The eight-bit Line Control Register is used to allow microprocessor 18 to program the serial interface parameters, as well as to request that a break condition be transmitted. The default value at Reset is all ZEROs.
MODEM CONTROL REGISTER. The five bit Modem Control Register allows the CPU to manipulate the link handshake signals. Additionally, the UART can be placed in a Loop Back mode for testing. Unused bits (7-5) should be ZEROs when the register is read. The default value at Reset is all ZEROs.
LINE STATUS REGISTER. The eight bit Line Status Register contains flag bits, that when set, indicate the presence of a condition that when ANDed with the appropriate interrupt enable bits of the Interrupt Identification Register can generate a line status interrupt. Bits 1, 2, 3, 4, and 7 are cleared by reading the Line Status register. Bit 5 is cleared when the condition goes away, but the interrupt is cleared by reading the Interrupt Identification Register (when the identification register is reporting this interrupt). Bits 0, and 6 are cleared when the causing condition is no longer present. The default values at Reset are shown below.
MODEM STATUS REGISTER. The eight-bit Modem Status Register is used to indicate the condition of the link handshake input signals, as well as the presence of a change in their status. Bits 3-0 default to 0 on Reset, bits 7-4 reflect the input status.
UART CONTROL REGISTER. The eight bit UART Control Register is used to control non-8250 like functions. Additionally, the UART software Reset bit is located here.
UART STATUS REGISTER. The five-bit UART Status Register reports status conditions that do not occur in an 8250 UART. Additionally, the "character with parity error available" bit is located in this register. The default value at Reset is all ZEROs, except bit 4 which is a ONE. Bit zero is cleared when the register is read. Bits 1-4 are cleared when the corresponding condition is no longer present.
Claims
What is claimed is:
1. A bit-oriented protocol (BOP) data controller (10) fabricated as a single integrated circuit having an internal bus (58,60,62), bidirectional serial port means (104) for high-speed serial receipt and transmission of data signals, full-duplex means (42,44) for low-speed serial receipt and transmission of data signals, and a microprocessor interface means (50) connected to said internal bus for the connection of a microprocessor (18), said BOP data controller comprising: a data link controller (DLC) (52) connected to said internal bus, to said microprocessor interface means and to said serial port means, comprising transmitter means (100,102) for parallel reception of data on said internal bus, for parallel-to-serial conversion thereof, and for serial generation thereof at said serial port means, and receive means (106,108) for serial reception of data on said serial port means for serial-to-parallel conversion thereof and for parallel generation thereof on said internal bus; a universal asynchronous receiver-transmitter (UART) (54) connected to said microprocessor interface means, to said internal bus, and to said full-duplex means, comprising transmitter means (418,420,422,424,428) for parallel reception of data on said internal bus, for parallel-to-serial conversion thereof, and for serial generation thereof at said full-duplex means, and receiver means (400,404,410,412) for serial reception of data on said full-duplex means, for serial-to-parallel conversion thereof and for parallel generation thereof on said internal bus; and dual-port timing controller (DPTC) means (56) connected to said internal bus, to said microprocessor (18), to a host processor (595) and a shared RAM (22a) and bus arbitration means (502,504,506,508,510,512) for connecting said microprocessor and said host processor to said BOP data controller, for generating timing and control signals to said microprocessor, said host processor, said bus arbitration means and said shared RAM, whereby said shared RAM and said BOP data controller is accessible to both said microprocessor and said host processor.
2. A BOP data controller according to claim 1 wherein said microprocessor interface means has a memory map and wherein said DLC, said UART and said DPTC means have predetermined addresses within said memory map and each of said DLC, said UART and said DPTC further include a plurality of status and control registers (112,212) (408) (596).
3. A BOP data controller according to claim 1 wherein said UART is selectably operable in a synchronous mode, comprising: a source of asynchronous clock signals; receive clock multiplexer means (410) receiving a synchronous receive clock signal and said asynchronous clock signals and generating therefrom, in response to a receive synchronous/asynchronous mode selection receive clock signals, serial-to-parallel receive shift register (400) for receiving serial data signals and said selectable clock signal generated by said receive clock MUX and generating parallel data signals; first-in, first-out (FIFO) receive register means for (404) receiving in parallel said data signal generated by said receive shift register for storing a plurality of said parallel data signals and for generating in parallel signals at an output connected to said internal bus signals representing stored data received earliest in time; transmit clock multiplexer means (418) for receiving said synchronous receive clock signals and said asynchronous clock signals and generating, in response to a transmit synchronous/asynchronous mode selection, a transmit clock signal; first-in, first-out (FIFO) transmit register means for (424) receiving in parallel data signals on said internal bus, for storing a plurality of said received data signals received over time and for generating in parallel output signals representing said stored data received earliest in time; parallel-to-serial transmit shift register (420) for receiving said selectable clock signal generated by said transmit clock MUX and said signals generated by said FIFO transmit register and generating serial data signals.
4. A BOP data controller according to claim 3, further icluding addressable means (413) for storing a plurality of "special" characters; and special character recognition means (412) connected to said receive shift register and said receive FIFO register means for determining if parallel data generated by said receive shift register corresponds to one of said "special" characters stored in said addressable means and for generating a signal indicating said determination.
5. A BOP data controller according to claim 4 wherein said receive FIFO register means includes means (404) responsive to said special character determination signal for tagging each of said plurality of data stored therein as a special character and for generating a signal indicative of the presence of said tagged data upon receipt at said FIFO, and a signal indicative of the presence of said tagged data at said FIFO output.
6. A BOP data controller according to claim 4 further including interface means connected to said internal bus for the connection of a microprocessor, and a plurality of register means (408) operably connected to said microprocessor interface means, each register means of said plurality comprising a plurality of bit storage locations, each of said locations for storing a predetermined status/control condition of said UART, wherein said plurality of status/control registers includes line Status Register means for receiving said signal indicative of the presence of said tagged data upon receipt at said FIFO and for setting a predetermined storage location therein according to said received signal, and wherein said plurality of status/control registers includes UART Status Register means receiving said signal indicative of the presence of said tagged data at said FIFO output for setting a predetermined storage location therein according to said received signal.
7. A BOP data controller according to claim 6 further including interrupt generating means (430) connected to said UART Status Register means for generating an interrupt signal indicative of said presence of said tagged data of said FIFO output.
8. A BOP data controller according to claim 7 wherein said interrupt generating means includes an Interrupt Identification Register means for receiving said signal indicative of said tagged data at said FIFO output for setting a plurality of predetermined ("Interrupt Source") storage locations therein according to said received signal, said Interrupt Identification Register means also having a predetermined ("Interrupt Pending") location indicating reception of said signal.
9. A BOP data controller according to claim 8 wherein said receive FIFO generates a signal indicative of the number of said data signals stored therein, and wherein said plurality of Control/Status Register means further includes UART Control Register means for receiving Receive FIFO Threshold signals from said microprocessor interface means for storing in predetermined storage locations therein said Receive FIFO Threshold signals, and wherein said Interrupt Identification Register means is responsive to said Receive FIFO Threshold signals stored in said UART Control Register and to said signal generated by said receive FIFO for indicating the number of data signals stored therein and sets said plurality of Interrupt Source location therein indicating said Receive FIFO is storing less than said Threshold.
10. A BOP data controller according to claim 9 wherein said transmit FIFO generates a signal indicative of the number of said data signals stored therein, and wherein said UART Control Register means further receives Transmit FIFO Threshold signals from said microprocessor interface means further for storing in predetermined storage locations therein said Transmit FIFO Threshold signals, and wherein said Interrupt Identification Register means is responsive to said Transmit FIFO Threshold signals stored in said UART Control Register and said signal generated by said Transmit FIFO for indicating the number of data signals stored therein and sets said plurality of Interrupt Source location therein indicating said Transmit FIFO is storing less than said Threshold.
11. A BOP data controller according to claim 10 further including means (412) connected to said receive shift register and said receive FIFO register means for testing the parity of parallel data generated by said receive shift register and for generating a parity error signal.
12. A BOP data controller according to claim 1 wherein said DLC means is responsive to a source of clock signals and a mode selection signal for serial receipt and transmission of data signals, and serial port means selectably operably in a time-division multiplexed (TDM) mode or in a non-multiplexed mode.
13. A data link controller according to claim 12 further having a transmitter including means (100, 102) for parallel reception of data on at least one channel for parallel-to-serial conversion thereof, and for serial generation thereof at said serial port means, wherein said serial port means includes a transmit-side portion selectably operable in said TDM of said non-multiplexed mode, wherein said transmit-side portion serial port means is further responsive to a time-slot selection signal and comprises: means (198) for receiving said clock signals, a serial frame synchronization (SFS) signal and a first transmit clock signal for generating a second transmit clock signal therefrom; and multiplexer means (196) for receiving said time-slot selection signal and said serial data from said at least one channel and for generating said serial data signals in said TDM or said non-multiplexed mode, said clock signals providing transmission synchronization in said TDM mode and said transmit clock signals providing transmission synchronization in said non-multiplexed mode.
14. A data link controller according to claim 13 wherein said multiplexer means is further responsive to said SFS signal and generates said signal from one said channel while said SFS signal is active, said clock signals providing transmission synchronization.
15. A data link controller according to claim 14 wherein said transmission receives data on thirty-one channels and wherein said time-slot selection signals include thirty-one time-slots.
16. A data link controller according to claim 15 further having a receiving including means for serial reception of data on at least one channel, wherein said serial port means includes a receive-side portion selectably operable in said TDM or said non-multiplexed mode, wherein said receive-side portion serial port means is further responsive to a channel-select signal and includes: multiplexer means (232) for receiving said clock signals, a serial rame synchronization (SFS) signal and said serial data from said at least one channel and for generating said serial data signals in said TDM or said non-multiplexed mode, a series of said signals being ones of a predetermined channel while said SFS signal is active in said TDM mode and said clock signals providing receiving synchronization in said non-multiplexed mode.
17. A data link controller according to claim 16 wherein said multiplexer means generates said signal from a predetermined one said channel while said SFS signal is active.
18. A BOP data controller according to claim 1 wherein said DLC transmitter means further includes a transmit byte register and counter means (152,154) for receiving a transmit packet size, for decrementing said transmit packet size and for generating a signal when said decremented count is zero; FIFO transmit means (150) connected to said internal bus and to said serial port means for receiving in parallel data on said internal bus, storing a plurality of said data and generating therefrom for generation of said serial port means said most-recently stored data, wherein said FIFO transmit means comprises a plurality of registers each having a plurality of bit positions, including a bit position for storing a signal indicative of the signal generated by said transmit byte register and counter means, thereby tagging a "least byte of a transmit packet".
19. A BOP data controller according to claim 1 further including means (112,212) connected to said internal bus, said microprocessor interface means and said serial port means for receiving and generating a plurality of status signals and control signals, said status and control means including: a plurality of registers (112,212) operably connected to said microprocessor interface means, each register of said plurality comprising a plurality of bit storage locations arrayed in a least-significant to a most-significant order, each said location representing a predetermined status condition of said DLC and arrayed in said least-significant to most-significant order in proportion to said status condition being most- to least-likely to occur, respectively.
20. A BOP data controller according to claim 19 wherein said DLC transmitter means further includes a FIFO transmit register means (100) connected to said internal bus and to said serial port means for receiving in parallel data on said internal bus, for storing a plurality of said data generated therefrom, and for generation at said serial port means said stored data, and wherein said DLC receiver means further includes a FIFO receive register means (106) connected to said internal bus and to said serial port means for receiving in parallel data received on said serial port means and for storing a plurality of said data and generating therefrom on said internal bus said stored data; and wherein said plurality of status and control registers includes a FIFO status register comprising five of said bit storage locations, said least-significant thereof being a received threshold reached status, a second least-significant location being a received FIFO data available status, a third least-significant location being a transmit threshold reached status, a next-to-most-significant location being a transmit FIFO buffer available status, and said most-significant location being a transmit underrun status.
21. A BOP data controller according to claim 20 wherein said FIFO transmit register means is responsive to a transmit threshold signal and wherein said FIFO transmit register means further generates a data request signal, said FIFO transmit register means includes: FIFO transmit buffer means (150) for storing said plurality of parallel data received by said FIFO transmit register means, for generating at a plurality of outputs signals representing said data received, and for generating a signal indicative of the number of said plurality of data stored therein; and means (156, 158) responsive to said transmit threshold signal and said signal indicative of the number of said plurality of data stored in said FIFO transmit buffer means for generating said data request signal.
22. A BOP data controller according to claim 21 wherein said FIFO transmit register means is further responsive to a transmit byte count signal and said data request generating means includes transmit byte counter means (154) responsive to said transmit byte count signal, said signal indicative of the number of said plurality of data stored in said FIFO transmit buffer means, for generating a transmit byte count equal to zero (TBC=0) signal, and wherein said data request generating means is further responsive to said TBC=0 signal, whereby said data request signal is generated when said threshold becomes equal to a predetermined value and said TBC=0 signal is not active.
23. A BOP data controller according to claim 22 wherein said FIFO transmit byte counter means further, responsive to said stored data tag, for maintaining a count of the number of said data received by said FIFO transmit register means and for generating a signal indicative of said data-received count when said tagged data is generated at said output of said FIFO transmit buffer means.
24. A BOP data controller according to claim 23 wherein said FIFO transmit register means further generates a last-byte-of-packet signal, wherein said FIFO transmit buffer means further includes means for tagging each of said plurality of data stored therein as a last-byte-of-packet, and for generating a signal indicative of the absence of said tagged data stored therein; wherein said transmit byte counter means generates a signal indicative of a last-byte-of-packet count, said last-byte-of-packet count signal received by said FIFO transmit buffer means, and wherein said data request generating means is further responsive to said absence of tagged data stored signal within said transmit buffer means, said data request signal is generated when saiid threshold signal equals said predetermined value, said TBC=0 is not active and said absence of tagged data signal is active.
25. A data link controller according to claim 24 wherein said FIFO receive register means is responsive to a receive threshold signal and wherein said FIFO receive register means further generates a data request signal, said FIFO receive register means includes FIFO receive buffer means (290) for storing said plurality of parallel data received by said FIFO receive register means, for generating at a plurality of output signals representing said data received, and for generating a signal indicative of the number of said plurality of data stored therein; and means (296) responsive to said receive threshold signal and said signal indicative of the number of said plurality of data stored in said FIFO receive buffer means for generating said data request signal.
26. A BOP data controller according to claim 25 wherein said FIFO receive register means is further responsive to a last-byte-of-packet signal, wherein said FIFO receive buffer means further includes means for tagging each of said plurality of data stored therein as a last-byte-of-packet, and for generating a signal indicative of said tagged data stored therein, wherein said data request generating means is further responsive to said absence of tagged data stored signal generated by said FIFO receive buffer means, said data request signal is generated when said receive threshold signal becomes equal to a predetermined value or said tagged data signal is active.
27. A BOP data controller according to claim 26 wherein said FIFO receive register means further includes receive byte counter means (292,294) responsive to said stored data tag and to said last-byte-of-packet signal for maintaining a count of the number of said data received by said FIFO receive register means and for generating a signal indicative of said data receive count when said tagged data is generated at said output of said FIFO receive buffer means.
28. A data link controller according to claim 27 further including a cyclic redundancy check (CRC) code checker (222) and a flag/abort detector (214) wherein said plurality of status and control registers includes a receive frame status register connected to said CRC code checker, said receive byte counter means and said FIFO receive register means, and said flag/abort detector comprising six of said bit storage locations said least-significant thereof being an abort received status, a second-least-significant location being a non-integer number of bytes received status, a third-least-significant location being a cyclic redundancy check error status, a fourth-least-significant being a short frame error status, a next-to-most-significant location being a long frame error status, and said most-significant location being an overrun error status.
29. A BOP data controller according to claim 28 further including a receive mark idle detector (230), and wherein said plurality of status and control registers includes a receive link status register connected to said receive mark idle detector and said flag/abort detector, comprising three of said bit storage locations said least-significant thereof being a mark idle received status, a second-least-significant location being a flag idle received status, and said most-significant location being an in-frame status.
30. A BOP data controller according to claim 29 wherein said receive byte counter means includes: means for receiving said data-received count signal and said in-frame signal and for generating said signals indicative of said data received count when said tagged data is generated at said FIFO received buffer means output ("delayed data-received count" signal), comprising; current stage means (602) responsive to said in-frame signal receiving said data-received count signals and said flag detection signal and generating therefrom signals indicative of said data-received count signals; holding stage means (606) receiving said data-received count signals generated by said current stage means and receiving a holding-empty signal, an end-of-frame signal and generating therefrom said data-received count signals upon reception of said holding-empty and end-of-frame signals, and generating said holding-empty signal; master stage means (610) for receiving said data-received count signals generated by said holding stage means and receiving a master-empty signal and an end-of-frame signal and generating therefrom said data-received count signals upon reception of said master-empty and end-of-frame signals, and generating said master-empty signal; slave stage means (614) for receiving said data-received count signals generated by said master stage means and for receiving a slave-empty signal and generating therefrom said "delayed data-received count" signals upon reception of said slave-empty and data received count signals.
31. A BOP data controller according to claim 30 wherein said DLC status and control means further include an interrupt source register storing in a predetermined bit position a receive frame status signal and a plurality of delayed status reporting means receiving a minimum packet size signals and a flag detection signal for generating a status of received data packets on a packet-at-a-time basis, comprising current stage means for receiving an in-frame signal, and said minimum packet size signals and said flag detecting signal and generating therefrom signals indicative of the status of data received by said DLC upon reception of said in-frame signal; holding stage means for receiving said status signals generated by said current stage means and receiving a holding empty signal and an end-of-frame signal and generating therefrom said status of data received by said DLC upon reception of said holding-empty equal and generating said holding-empty signal; master stage means for receiving said status signals generated by said holding stage means and receiving a master empty signal and an end-of-frame signal and generating therefrom said status of data received by said DLC upon reception of said master empty and end-of-frame signals and generating said master empty signal; and slave stage means for receiving said status signals generated by said master stage means and receiving a slave empty signal and generating therefrom an OR function of said status of data received by said DLC upon reception of said slave signal and generating said slave empty signal.
32. A BOP data controller according to claim 1 wherein said DLC includes an Interrupt Source register connected to said microprocessor interface having a plurality of bit positions, predetermined continguous ones of said bit positions forming at least a least-significant receive link address field portion thereof, a valid packet field portion thereof, and a most-significant interrupt source field portion thereof.
33. A BOP data controller according to claim 32 having link address detection means (226) comprising at least a first, second, third and fourth link address register and a broadcast link address register for recognition of a packet address, and wherein said interrupt source register receive link address field portion is a three-bit field associating said four link address registers and said broadcast link address registers with the status of a received packet according to the following table: Contents of Received Link Address Field Bit 2 1 0 Meaning ______________________________________ 0 0 0 Contents of Said First Link Address Register Recongized 0 0 1 Contents of Said Second Link Address Register Recongized 0 1 1 Contents of Said Third Link Address Register Recongized 0 0 1 Contents of Said Fourth Link Address Register Recongized 1 0 0 Contents of Said Broadcast Link Address Reg. Recognized 1 0 1 Not used 1 1 0 Default - No packet received 1 1 1 Packet Received ______________________________________
34. A BOP data controller according to claim 33 wherein said Interrupt Source Register Valid packet field portion is a two-bit field comprising a fourth bit position of said Interrupt Source Register representing reception of a valid packet by said DLC and a fifth bit position of said register representing transmission of a valid packet by said DLC.
35. A DLC according to claim 34, wherein said transmitter means further including first-in, first-out (FIFO) transmit register means (100) for receiving said data on said internal bus, for storing a plurality of said data and for generating said data for said parallel-to-serial conversion, and said receiver means further including first-in-first-out (FIFO) receive register means (106) for receiving said serial-to-parallel converted data for storing a plurality of said data and for generating said data on said internal bus; wherein said Interrupt Source Register interrupt source field portion is a three-bit field comprising a fifth bit position of said Register representing occurrence of any of a plurality of predetermined error conditions in a frame received by said DLC, a sixth bit position of said Register representing occurrence of any of a plurality of predetermined conditions in said transmit FIFO and said receive FIFO, and a seventh bit position of said Register representing occurrence of any of a plurality of predetermined conditions in a receive-side of said serial port.
36. A BOP data controller according to claim 1 wherein said DPTC means is connected to a source of clock signals receiving control signals from a local processor including a local data transmit/receive (LDT-R) signal and control signals from a host processor including a host data transmit/receive (HDT-R) signal and generating signals to a shared memory (22a) and to a bus arbitration means, comprising: means (520) connected to said source of clock signals for synchronizing said host request signal to said clock signals and generating a synchronous host request signal; means (522) connected to said source of clock signals responsive to said local request signal, said synchronous host request signal for generating a host memory cycle timing (HCYCLE) signal and a local memory cycle timing (LCYCLE) signal, and a memory access enable (GO) signal, therefrom, implementing predetermined cycle arbitration products; means (524) connected to said source of clock signals receiving said LDT-R and HDT-R signals for generating a plurality of control signals conducted to said shared RAM and generating a memory access disable (STOP) signal; and means (526, 528, 530, 532) connected to said source of clock signals receiving said LCYCLE and HCYCLE signals, said STOP signal and said HDT-R signal for generating a plurality of control signals to said bus arbitration means.
37. A bit-oriented protocol data controller fabricated as a single integrated circuit for controlling data communications with a station, the controller comprising a processor interface for facilitating communication between a local processor and the controller, a data link controller means for effecting serial communications with said station, a receiver-transmitter means for effecting duplex communications with said station, a dual port timing controller means for managing access to a memory register by a plurality of processors, and an internal bus means for internal transfer of data within the controller; said internal bus means being operatively connected to said processor interface means, said data link controller means, said universal asynchronous receiver-transmitter means, and said dual port timing controller means.
38. A bit-oriented protocol data controller as recited in claim 37 wherein the controller further comprises memory means associated with at least one of said data link controller, said receiver-transmitter means and said dual port timing controller means; said communication between said local processor and the controller comprising a plurality of communication signals, each of said communication signals having an associated encoded address; said processor interface means being configured to effect decoding of said address and directing each of said plurality of communication signals via said internal bus means to appropriate respective of said memory means according to said address.
39. A bit-oriented protocol data controller as recited in claim 37 wherein said receiver-transmitter means is capable of operation in a synchronous or an asynchronous mode.
40. A bit-oriented protocol data controller as recited in claim 37 wherein at least one of said data link controller register and said receiver-transmitter means employs first-in first-out register means to effect said internal transfer of data by movement of packets of data.
41. A bit-oriented protocol data controller fabricated as a single integrated circuit for controlling data communications with a station, the controller comprising: an interface means for fabricating communication between a local processor and the controller; a simplex communications means for effecting serial communications with said station; a duplex communications means for effecting duplex communications with said station; a memory access controller means for managing access to a memory register by a plurality of processors; and an internal bus means for internal transfer of data within the controller; said internal bus means being operatively connected to said interface means, said simplex communications means, said duplex communications means, and said memory access controller means.
42. A bit-oriented protocol data controller as recited in claim 41 wherein the controller further comprises memory means associated with at least one of said simplex communications means, said duplex communications means, and said memory access controller means; said communication between said local processor and the controller comprising a plurality of communication signals, each of said communication signals having an associated encoded address; and said interface means being configured to effect decoding of said address and directing each of said plurality of communication signals via said internal bus means to appropriate respective of said memory means according to said address.
43. A bit-oriented protocol data controller as recited in claim 41 wherein said duplex communication means is capable of operation in a synchronous or an asynchronous mode.
44. A bit-oriented protocol data controller as recited in claim 41 wherein at least one of said simplex communication means and said duplex communication means employs first-in, first-out register means to effect said internal transfer of data by movement of packets of data.
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