Arithmetic Operation Circuit

The present invention relates to semiconductor integrated circuit, and moreover to technology which is effective when adopted to a composite logic circuit consisting of CMOS device and bipolar transistor. It is also directed to technology which is effective when adopted, for example to an arithmetic operation circuit forming the arithmetic operation logic unit of microcomputer.

As a logic gate circuit which requires larger load driving force than that of CMOS (complementary MOS) circuit and less power consumption than that of bipolar logic circuit, a composite logic gate circuit (hereinafter called a Bi-CMOS logic circuit) as indicated in FIG. 4 has been proposed (e.g., see Nikkei Electronics, from page 188 to page 189, issued on Aug. 12, 1985, Nikkei Mcgrowhill), in which the output part is formed by a totem pole type buffer consisting of bipolar transistors Q.sub.5, Q.sub.6 and the input logic part LG which controls such an output part is formed by P-MOSQ.sub.1, Q.sub.2 and N-MOSQ.sub.3, Q.sub.4.

Said Bi-CMOS logic circuit is capable of sufficiently utilizing the advantages in high speed operation and low power consumption in case it is adopted to an input/output buffer, a bus driver and a clock driver, etc. having a large load.

The inventors of the present invention have discussed whether it is possible or not to realize high speed arithmetic operation by adopting the Bi-CMOS logic circuit to the arithmetic operation logic unit of CMOS microcomputer.

The arithmetic operation logic unit employing the CMOS circuit can be formed by combining an arithmetic operation circuit, for example, as indicated in FIG. 5, consisting of the input latch part LT and logic/output part LG/OC.

The truth value table of arithmetic operation circuit indicated in FIG. 5 is indicated as Table 1 and Table 2.

Said CMOS arithmetic operation circuit is formed by cascade-connected six stages of a CMOS circuit and has a large number of stages of logic circuits. For example, the invertors IV1, IV2, IV3 and IV4, AND gate AND 1 and NOR gate NOR1 are cascade-connected in order to form an output signal A based on the input signal X. However, a load capacity driven by the output signal A is generally very small. Therefore, the operation speed of said arithmetic operation circuit is defined by a number of stages of logic circuits and the speed of CMOS gate. Accordingly, the inventors of the present invention have made it obvious by investigation that high speed operation of arithmetic operation circuit cannot be realized even when the Bi-CMOS logic circuit is only adopted to such arithmetic operation circuit for driving a small load.

It is therefore an object of the present invention to provide a semiconductor integrated circuit technology to realize high speed operation of low power consumption type arithmetic operation circuit without losing the advantage of low power consumption.

These and further objects and novel characteristics of the present invention will become apparent from the following description taken in conjunction with the preferred embodiment thereof with reference to the accompanying drawings.

The invention disclosed in the present specification is outlined as described below.

Namely, an arithmetic operation circuit is formed by an input latch part which is formed by a CMOS inverter circuit and forms and maintains the complementary signal of the input signal, a logic processing part consisting of N-MOS switch array which is controlled for ON and OFF with the signal latched by such input latch part and carries out logic operations, and an amplifier part which is formed by a grounded emitter type bipolar transistor and amplifies logic output having small amplitude obtained by said logic processing part.

According to said means, since change of amplitude of signal obtained by the logic processing part is amplified by high transmission conductance characteristic corresponding to g.sub.m of MOSFET of the bipolar transistor, amplitude of logic output in the logic processing part consisting of N-MOS switch array can be lowered and the processing can be done only with the one stage of logic circuit. Thereby, said object of realizing high speed operation of logic circuit of low power consumption type can be attained by execution of logic operations without any delay.

FIG. 1 is a circuit diagram indicating an embodiment of the arithmetic operation circuit of the present invention,

FIG. 2 is a circuit diagram indicating another embodiment of the arithmetic operation circuit of the present invention,

FIG. 3 is a circuit diagram indicating a modification of an amplifier part of the arithmetic operation circuit of the present invention,

FIG. 4 is a circuit diagram indicating an example of the Bi-CMOS basic logic circuit,

FIG. 5 is a circuit diagram indicating an example of an arithmetic operation circuit for an arithmetic operation logic unit discussed prior to the present invention,

FIG. 6 is a circuit diagram indicating an embodiment of the logic processing part and amplifier part of the arithmetic operation circuit of the present invention, and

FIG. 7 is a block diagram indicating an example of the microprocessor using the arithmetic operation circuit of the present invention.

FIG. 1 is an embodiment of the arithmetic operation circuit of the present invention.

Each circuit element in the same figure formed, for example, on a semiconductor substrate such as a single crystal silicon by the well known Bi-CMOS circuit technology. Moreover, the arithmetic operation circuit of FIG. 1 is used, for example, as a circuit which forms ALU (Arithmetic operation Logic Unit) such as 1-chip microcomputer or microprocessor.

The truth value tables of the circuit indicated as FIG. 1 are given as the Table 3 and Table 4.

The values of output signals A, B indicated in said Table 1 match the values of output signals A, B in said Table 3. Moreover, the values of output signals A, B in said Table 2 match the values of output signals A, B in said Table 4. Therefore, the arithmetic operation circuit of FIG. 1 has the same arithmetic operation function as the arithmetic operation circuit of FIG. 5.

The input signal X and signal Y are input to the input latch circuit LT1 consisting of the CMOS inverters IV.sub.11 .about.IV.sub.13 and the input latch circuit LT2 consisting of the CMOS inverters IV.sub.21 .about.IV.sub.23 and thereby the signals X, X, Y, Y of the true level and false level are formed and maintained. Of the inverters IV.sub.11 .about.IV.sub.23, IV.sub.11 and IV.sub.12, IV.sub.21, IV.sub.22 are clocked inverters.

In the stage next to said input latch circuit, the logic process part LG consisting of the switch array where the N-channel type MOSFETs are arranged like a matrix is provided. Although not restricted particularly, this embodiment provides 10 switch columns, each of which is formed by a pair of serially connected N-MOS and the true and false input signals X or X and Y or Y formed by said input latch circuits LT1, LT2 are respectively applied selectively to the gate terminals of N-MOS of each switch column.

The source side of the switch column of transistors Q.sub.11, Q.sub.12, switch column of Q.sub.21, Q.sub.22, switch column of Q.sub.31, Q.sub.32, switch column of Q.sub.41, Q.sub.42 and switch column of Q.sub.51, Q.sub.52 among these switch columns is connected to the ground potential of circuit through the common transistor Q.sub.01. Simultaneously, the sense circuit SA1 in the next stage is connected to the drain side of the switch column of transistors Q.sub.11, Q.sub.12, switch column of Q.sub.21, Q.sub.22 and switch column of Q.sub.31, Q.sub.32. Here, the signal X is applied to the gate of transistors Q.sub.11, while the signal Y to the gate of Q.sub.12. For this purpose, said switch column Q.sub.11, Q.sub.12 executes the NOR logic operation in which an output (level of node n.sub.1) is set to low level only when both signals X, Y are high level under the condition that the transistor Q.sub.01 is in the ON state.

Said sense circuit SA1 (SA2) is formed by the grounded emitter type Schottky bipolar transistor Q.sub.111 (Q.sub.121) where the base terminal is connected to the output node n.sub.1 (n.sub.2) of logic processing part LG, P-channel MOSFET Q.sub.112 (Q.sub.122) connected between the base terminal of transistor Q.sub.111 (Q.sub.121) and the power supply voltage terminal V.sub.cc and P-MOSFET Q.sub.113 connected between the collector terminal of transistor Q.sub.111 and V.sub.cc. Both MOSFETs Q.sub.112 (Q.sub.122) and Q.sub.113 (Q.sub.123) are caused to operate as the resistors when the ground potential is applied to the gate terminal thereof. However, such resistance value of MOSFETs Q.sub.112 (Q.sub.122) is selected to about 10 kohms, while that of Q.sub.113 (Q.sub.123) to about 200.about.300 ohms.

Said sense circuits SA1, SA2 sense and output an output of the logic processing part by utilizing a high transmission conductance of bipolar transistor and therefore if an output of the logic processing part LG has the amplitude as low as 0.about.0.8 V, the signal of almost CMOS level having high amplitude may be output to the next stage.

In addition, the logic part of logic processing part LG is formed by a single stage and its output amplitude can be lowered to 0.8 V having low amplitude and thereby a delay time of arithmetic operation circuit can be reduced remarkably. That is, in the arithmetic operation circuit as indicated in FIG. 5 formed by the six stages of CMOS gates, when a delay time per gate is set to 2 ns, the delay time of 12 ns in the circuit as a whole can be reduced only to 5 ns in the total circuit, namely 4 ns at the input latch part consisting of two stages of gates, 0.5 ns at the logic processing part consisting of N-MOS array and 0.5 ns at the bipolar type amplifier part in said arithmetic operation circuit of the embodiment explained earlier. Therefore, the operation speed can be increased almost upto 2 times in comparison with the arithmetic operation circuit of the prior art.

Moreover, since the logic function is realized by the rule logic consisting of the switch array of N-MOS, the AND logic such as said embodiment and other logic than the exclusive OR logic can also be realized easily. Thereby, logic design of arithmetic operation circuit becomes easier.

FIG. 2 indicates a circuit diagram of another embodiment of the present invention. The circuit diagram of FIG. 2 forms an arithmetic operation circuit like the circuit diagram of FIG. 1.

Difference between the arithmetic operation circuits of FIG. 1 and FIG. 2 lies in the structure of logic processing part. The logic processing part LG' of FIG. 2 is formed by the six switch columns (Q.sub.11,Q.sub.12), (Q.sub.21,Q.sub.22), . . . , (Q.sub.61,Q.sub.62). The truth value tables of the arithmetic operation circuit of FIG. 2 are indicated in Table 5 and Table 6.

As it is apparent from the truth value table of Table 5, the values of output signals A, B for the input signals, X, Y indicated the truth values of half-adder circuit. Moreover, it is obvious from then truth value table of Table 6, the values of output signals A, B for the input signals X, Y indicate the truth values of half-subtractor circuit. Therefore, the arithmetic operation circuit of FIG. 2 is capable of executing the adding function and subtraction function by switching them with the control signals C, C.

In the case of forming a total adder circuit using the half-adder circuit of said embodiment, the carry forming circuit (carry circuit) and a half-adder circuit similar to that explained above are connected to the next stage of the sense circuits SA1, SA2.

In the embodiment shown in FIG. 1 or FIG. 2, when the voltage of node n.sub.1 (n.sub.1 ') or n.sub.2 (n.sub.2 ') is in the high level while the arithmetic operation circuit is not operable, a constant current continuously flows into the bipolar transistor Q.sub.111 or Q.sub.121 resulting in possibility of large power consumption. Therefore, the bipolar transistor Q.sub.111 (Q.sub.121) may be protected from the saturating condition by connecting MOSFET Q.sub.114 between the base and collector of the bipolar transistor indicated in FIG. 3 and then turning ON such transistor. Thereby, it is prevented that a collector currents flow constantly and power consumption may also be reduced.

FIG. 6 is the circuit of essential portion indicating another embodiment of the present invention. The logic processing part LG" comprises the fist switch column consisting of cascade-connected MOSFETs Q.sub.11, Q.sub.12, the second switch column consisting of cascade-connected MOSFETs Q.sub.21, Q.sub.22, the third switch column consisting of cascade-connected MOSFETs Q.sub.31, Q.sub.32, the fourth switch column consisting of cascade-connected MOSFETs Q.sub.41, Q.sub.42, the fifth switch column consisting of cascade-connected MOSFETs Q.sub.51, Q.sub.52 and the sixth switch column consisting of cascade-connected MOSFETs Q.sub.61, Q.sub.62. The switch MOSFET Q.sub.01 to which the power supply voltage V.sub.cc is applied to the drain thereof is provided to supply the power supply current to said fist, second and third switch columns. The source of this switch MOSFT Q.sub.01 is connected in common to the drains of said transistors Q.sub.11, Q.sub.21, and Q.sub.31. Moreover the switch MOSFET Q.sub.02 to which the power supply voltage V.sub.cc is supplied to the drain thereof is provided to supply the power supply current to said fourth, fifth and sixth switch columns. The source of this switch MOSFET Q.sub.02 is connected in common to the drains of said MOSFETs Q.sub.41, Q.sub.51 and Q.sub.61. Said MOSFETs Q.sub.01 .about.Q.sub.02 are turned ON selectively by the control signals C and C. Thereby, switching of the arithmetic function may be conducted. The sources of MOSFETs Q.sub.12, Q.sub.42 are connected in common to the node n.sub.1 ", and the sources of MOSFETs Q.sub.22, Q.sub.32, Q.sub.52 and Q.sub.62 are connected in common to the node n.sub.2 ". The signal on said node n.sub.1 "is amplified by the sense circuit SA1' and thereby the output signal B is formed. The signal on said node n.sub.2" is amplified by the sense circuit SA2' and thereby the output signal A is formed. Relationship between the input signals X, X, Y, Y of the circuit indicated in FIG. 6 and the output signals A, B matches that of the circuit of FIG. 2. The sense amplifier SA1' comprises the grounded emitter type bipolar transistor Q.sub.10 which receives the signal on the node n.sub.1 " at the base, the P-channel MOSFET Q.sub.12 provided as the collector load resistance of such bipolar transistor Q.sub.10 and the N-channel MOSFET Q.sub.11 connected between the collector and base of bipolar transistor Q.sub.10. The output signal obtained from the common connecting point of the drain of said MOSFET Q.sub.12 and the collector of bipolar transistor Q.sub.10 is fed back to the gate of said MOSFET Q.sub.11 through the inverter IV6. When a driving current is supplied to the node n.sub.1 " from the logic processing part LG", the bipolar transistor Q.sub.10 turns ON and the output signal B becomes low level. Thereby, the MOSFET Q.sub.11 which receives the high level signal B turns ON. Since the MOSFET Q.sub.11 becomes ON, the bipolar transistor Q.sub.10 is not saturated. Accordingly, high speed characteristic when the bipolar transistor Q.sub.10 turns OFF is not deteriorated.

In case the drive current is not supplied to the node n.sub.1 ", the bipolar transistor Q.sub.10 turns OFF and the output signal B becomes high level. Thereby, the MOSFET Q.sub.11 which receives the low level output signal B turns OFF. When the ON resistance of MOSFET Q.sub.10 is set to a comparatively higher value, the output signal B becomes high level in accordance with the OFF state of said bipolar transistor Q.sub.10. The structure of the sense amplifier SA2' is similar to that of said sense amplifier SA1'.

According to the circuit shown in FIG. 6, low power consumption of the sense amplifier circuits S1', SA2' can be realized while the logic processing part LG" is non-operable condition. That is, under the waiting condition where the control signals C, C are in the low level, since the drive current is not supplied to the nodes n.sub.1 " and n.sub.2 ", the respective bipolar transistors Q.sub.10, Q.sub.7 forming the sense amplifiers SA1', SA2' are set to the OFF state. Therefore, the electrical power is not consumed uselessly in the sense amplifier circuits SA1', SA2'.

In the sense amplifier circuit SA1' (SA2'), a resistor means for extracting charges of base may also be provided between the base and ground potential GND of the bipolar transistor Q.sub.10 (Q.sub.7). The resistance mans is effective to improve the switching speed to the OFF state from ON state of the bipolar transistor Q.sub.10 (Q.sub.7).

FIG. 7 is an example of the hardware structure of a microprocessor including the arithmetic operation logic unit ALU to which the arithmetic operation circuit of the present invention is adopted.

The microprocessor of this embodiment provides the control part of microprogram control system. Namely, the micro-ROM 2(Read Only Memory) storing the microprogram is provided within an LSI chip forming the microprocessor. The micro-ROM 2 is accessed by the microaddress generating circuit 2 and sequentially outputs the microinstructions forming the microprogram. To the microaddress generating circuit 5, the signal obtained by decoding the code of microinstruction fetched to the instruction register 3 with the instruction decoder 4 is supplied. The microaddress generating circuit 5 forms the corresponding microaddress on the basis of such signal and then supplies to the micro-ROM 2. Thereby, the first instruction of a series of microinstruction groups to instruct the such microinstructions can be read. By this microinstruction code, the control signal for the execution unit 6 consisting of the various kinds of temporary registers, data buffer, arithmetic operation logic unit ALU and address calculation unit AU may be formed.

The second and successive microinstructions among a series of microinstruction groups corresponding to the macroinstruction are read by supplying the code of next address field of microinstruction read just precedingly to the micro-ROM 2. That is, the microinstruction latch 9 is provided to maintain the next address in the preceding microinstruction and the second and successive microinstructions are read based on the output of said latch 9 and the address sent from the microaddress generating circuit 4. A series of microinstructions thus read are decoded by the microinstruction decoder 10, the execution unit 6 is controlled by the output control signal thereof and the macroinstructions are thus executed.

In this embodiment, although not restricted particularly, a buffer storing system is employed, a cash memory 7 is provided within the microprocessor LSI and the program data having high access frequency among the data in the external memory 8 are registered in the cash memory 7. Thereby, program fetch is carried out at a high speed.

The address calculation unit AU calculates addresses of operand on the basis of information of the extended part for designating operand address and the specified register within the execution unit 6. Said extended part is supplied to the address calculation unit AU through the register 11 only for the extended part without decoding by the instruction decoder 4. Moreover, the address calculation unit AU is controlled by the address calculation control information INF obtained by decoding the instruction including the operand designation part.

As explained previously, the arithmetic operation circuit of the present invention comprises an input latch part which is formed by the CMOS inverter circuit and forms and holds the complementary signal of the input signal, a logic processing part which is formed by the switch array which is turned ON and OFF by the signal latched by said input latch part and executes the logic operation and an amplifier part which is formed by the grounded emitter type bipolar transistor and amplifies the logic output of low amplitude obtained by said logic processing part. Therefore, since change of amplitude of signal obtained by the logic processing part is amplified by the high transmission conductance of bipolar transistor, the amplitude of logic output of the logic processing part consisting of the N-MOS array can be made small and the logic signal can be processed by only one stage. Accordingly, the logic operation can be executed almost without delay and thereby the effect that high speed operation can be realized without deterioration of low power consumption characteristic of logic circuit can be attained.

While the invention proposed by the inventors of the present application has been described with respect to a specific embodiment thereof, it is to be understood that the present invention is not limited thereto in any way but covers any and all changes and modifications which will become possible within the scope of the appended claims. For example, in above embodiment, it is explained that the transistors Q.sub.112, Q.sub.122 forming the sense circuits SA1, SA2 are formed by the Schottky bipolar transistor but it is not limited only to the Schottky type and also may be formed by the ordinary bipolar transistor.

In above explanation, the invention by the inventors of the present application is adopted to the arithmetic operation circuit which forms the arithmetic operation logic unit such as a microcomputer which is the application field as the background thereof. This invention is not limited thereto, however, and it may also be used generally to the arithmetic operation device and ordinary logic circuit in the logic integrated circuit using CMOS circuit.