Single Track Absolute Encoder

This invention relates in general to absolute encoders, and more particularly, to an absolute encoder having a code track and providing an output signal indicative of the precise position of a rotary or linear scale.

Absolute encoders are known for providing an output indication of the position of a sensing head relative to a measuring scale. For sensing rotary displacement, the scale is in the form of a disc rotating a plurality of concentric tracks which provide respective bits of a multi-bit digital code. For linear rotation sensing, the scale is an elongated scale member containing linearly arranged parallel code tracks. The rotary code tracks are sensed by an array of sensors each concentric with a respective track to provide an output signal representing a bit of the multi-bit output code. The code tracks are often formed of optically responsive segments, which segments are light transmissive or light reflective, but the tracks can alternatively be of other forms such as magnetic, capacitive or inductive. Higher resolution is achieved by increasing the number of code tracks to provide a higher number of bits in the output code.

Broadly speaking, the present invention provides an absolute encoder having a code track and a clock track. The code track is encoded with a serial code which is unique for each increment that the disc rotates. That is, for a code of N-bits, each N adjacent bits represent a unique N-bit word. Such a code is sometimes defined as a shift register code. The invention can be embodied in a rotary or linear encoder to sense relative angular or linear movement, respectively.

The invention will be more fully understood from the following detailed description, taken in conjunction with the accompanying drawings, in which:

FIG. 1 shows one particular embodiment of an encoder disc having a track pattern in accordance with the present invention; and

FIG. 2 is a block diagram of a circuit operative with the encoder having the disc of FIG. 1 to provide an output signal.

With reference now to the drawings, there is shown the preferred embodiment of an absolute encoder of the present invention. While the present invention may be either a rotary encoder or a linear encoder, the present description will describe a rotary encoder having a disc 10.

With reference to FIG. 1, rotary disc 10 is mounted on shaft 11. Rotary disc 10 is circled by an outer ring 12 and an inner ring 14. The relative locations of the tracks 12 and 14 on the disc 10 is not of primary importance, but are preferably along its outer perimeter. In the preferred embodiment, the segments of the two tracks consist of light transmissive and opaque segments, but can be of any other signaling method known in the art.

Track 14 looks like that of an incremental encoder, and it is used to generate the two least significant bits of the total absolute output word. Herein, this equal-increment track will be called the "clock" track.

The other track, track 12, is called the "code" track and will have half as many binary bit portions as the clock track 14. The code track 12 is serially coded in such a way as to provide all of the more significant bits to form the complete absolute output word. Code track 12 is shown in FIG. 1 as comprising light segments 16 and dark segments 18.

The shift register code used in the code track 12 is a serial code which provides a unique value for each incremental position of the encoder. For ease of description, a 3-bit serial code is described, but as is readily apparent, a serial code of any number of bits can be used. The number of bits chosen depends upon the resolution to which angular position is desired.

To determine the bit sequence on the code track, a serial code must first be defined. An example of a 5-bit binary encoder is given here. Such an encoder would divide one rotation into 2.sup.5 or 32 discrete intervals, each 11.25.degree.. As stated above, the two least significant bits are derived from the clock track, and this will be detailed later. The three more significant bits of the shift register code, as shown below, are:

Note that each word in the series of eight comes from the previous word shifted one slot to the left with a new bit entered from the right, progressing from top to bottom. In the reverse direction, moving from bottom to top, the new bit enters from the left and the others are shifted to the right. Thus, the code track carries the sequence of 0's and 1's in the order of the Most Significant Bit (MSB) column, i.e., from top to bottom: first three 0's, followed by three 1's, a 0, and a 1. This is also the sequence of bits in all three bits columns in the code sequence. When this pattern is placed on the code track 12, any three adjacent segments produces a unique sequence. Shift register codes are in themselves known, and are described, for example, in such sources as S. Golumb, Shift Register Sequences (Aegean Park Press 1982); S. Lin, Error Control Coding. (Prentice-Hall, Inc. 1983); or F. McWilliams, The Theory of Error-Correcting Codes, (North Holland Publishing Co. 1977). The algorithms for generating such codes all leave out the "all zeroes" word, which then must be arbitrarily inserted in the proper place in the code sequence.

The code track pattern 12 is sensed to determine the state of every successive angular bit position, and each such state is entered as a "1" or a "0" in the end slot of a shift register. As each bit state is entered, the previously sensed code track bits are all shifted into the next adjacent position in the shift register. After the shift register is filled by transversing input motion by N-2 bits, the parallel output word from the shift register plus the two least significant bits from the clock track 14 form a unique N-bit word indicating absolute input position. From then on, the N output bits continually indicate absolute input position for either direction of motion. For one direction of motion, the new absolute bit is sensed via a reticle slit 20 and entered into the right-hand end of the shift register and all previous successive bits are shifted one slot left. For the opposite direction of motion, the newly sensed bit from a second reticle slit 22 is entered into the left-hand end of the register and all previously sensed bits are shifted to the next right slot in the shift register. Thus, the pattern of bits in the shift register correspond to the same pattern on the code track between the two code pattern slits, placed N-2 bits apart on a reticle sensing plate. Thus, the N-2 more significant bits must be layed out on the code track in a succession such that each output word is the same as the previous word, only shifted one slot with a new entry at one end or the other. Also, after power is initially applied to the encoder, the input motion must traverse either way by the small amount needed to fill the shift reqister. For example, a rotary encoder that divides one rotation into 2048 increments must move by less than 2.2.degree. to fill the register and generate the correct 11-bit output code. This is much simpler than having to rotate the up to one complete revolution necessary to find the zero-reference index in a purely incremental encoder.

As shown in FIG. 1, the clock track 14 is phase aligned with the code track 12 so as to cause the sensing circuitry to read each code track segment at its center, ensuring accurate readings of the code segments. The clock track 14 is required because, as can be seen FIG. 1, adjacent segments of the code track 12 may be of the same value (i.e. clear or opaque), thus creating ambiguity as to where one segment ends and the next begins. The A slit 24 and B slit 26, typically found on a common or separate reticle plate, are used to define the position at which the clock track is sensed. A clock signal determines when the code track is read, and the phasing of the two clock track signals determine direction of rotation.

FIG. 2 shows a preferred circuit diagram for converting the data on the rotary disc 10 to a determination of angular shaft position. With reference to FIGS. 1 and 2, the operation of the decoder circuitry will now be explained. The light emitting diode (LED) 30 for the clock track is always on, irradiating both the A slit 24 and the B slit 26, and producing resultant signals at the outputs of A and B comparators (Schmitt Triggers) 27 and 29, respectively. In order to ensure that every bit in the code track is sensed, the LED 32 for the sensor S.sub.1, 20, and the LED 34 for sensor S.sub.2, 22, are each pulsed on at the instants of the transition of the A track ANDED at AND gates 36 and 38, respectively, with the B track being in the zero state, which signal is received from inverter 31. The two tracks 12 and 14 are phased to each other so that the A transitions always occur when the single-line slits at S.sub.1 and S.sub.2 are in the middle of a code track element. For clockwise (CW) rotation, the S.sub.1 LED 32 is pulsed on by the B.times.A.uparw. (B and A.uparw.) transitions (where A.uparw. means OFF to ON), and for counter-clockwise (CW) rotation, the S.sub.2 LED 38 is pulsed on by the B.times.A.dwnarw. transitions (where A.dwnarw. means ON to OFF). The S.sub.2 slit is positioned, in the drawing, three code-track bits (or N-2 bits) behind the S.sub.1 slit. FIG. 1 shows the disc in the position where S.sub.1 's LED 32 is pulsed ON and radiates the middle of an opaque code track element. This is the beginning of the 000 code, because the two previous S.sub.1 pulse instants have already generated the first two opaque 0's rotating clockwise. The signal from comparators 42 and 44 are indicative of the state of the code track at slots S.sub.1 and S.sub.2, respectively. For clockwise rotation, the signal from S.sub.1 is input into the register via line C.sub.1. For counter-clockwise rotation, the signal from S.sub.2 is input into the shift register via line C.sub.2. Further 45.degree. clockwise rotation positions a clear bit under S.sub.1 at the instant of the next B.times.A.uparw. pulse, thus generating a "1" to enter the register in the right hand slot and shifting the other two "0's" left, thus causing the end of the 000 code and the beginning of the 001 code. During this same 45.degree. rotation, the A and B bits have gone through the normal sequence of four transitions, thus dividing the 45.degree. interval into four 11.25.degree. increments. The A and B square waves follow the conventional incremental cycle and are converted to an absolute natural binary sequence by the simple logic shown in FIG. 2, including inverter 33 and X-OR gate 35. The direction of shift, which is dependent on the direction of disc rotation, is sensed by AND-gates 36 and 38, which produce a clock signal which triggers the shift register depending on whether the disc is rotating clockwise or counter-clockwise.

The last step is to convert the code in the shift register 40 to the desired output code, in this case, natural binary. A PROM 46 is used for this purpose, with the N-2 bit absolute word transmitted along parallel lines 48 into PROM 46, which provides the means for decoding the shift register's word. The shift register parallel output is used as addresses. The output from the PROM 46 may be of any mapping form, including natural binary, binary-coded-decimal, logarithmic, or trigonometric. The mapping does not need to be linear, so, for example, a weighted value which might represent a cam could be encoded.

Table 1 shows the successive readouts for this 5-bit example:

It may be convenient to count transitions after turning on power in order to provide a "READY" output signal to indicate that the shift register is correctly filled and can be read. However, this detail is not shown in the electronics diagram of FIG. 2. Another convenient output line could present a "don't read" pulse during transitions.

As is apparent from the present description, although the described embodiment is of a rotary disc encoder using a single serial code track, various other modifications and alternative implementations will occur to those versed in the art without departing from the true spirit and scope of the invention. Accordingly, it is not intended to limit the invention to what has been particularly shown and described except as indicated in the appended claims.