Semiconductor Device

1. Field of the Invention

The present invention relates to a semiconductor device, more particularly to a permeable base transistor (PBT).

2. Description of the Related Art

A PBT comprising an emitter layer, comb-shaped or lattice-shaped base electrodes, a base layer, a collector layer, an emitter electrode, and a collector electrode is well known.

In a PBT, the value of the voltage applied to the comb-shaped base electrode can be used to change the coverage of the depletion layer extending from the base electrode in the horizontal direction. This effect can be used to control the electrons which pass between the comb-shaped base electrodes from the emitter layer to the collector layer.

The thickness of the base electrode is about 0.02 .mu.m. This corresponds to a field effect transistor (FET) which has a short channel length of 0.02 .mu.m. Therefore, the base electrons transit time in the PBT is very short, enabling high speed operation.

However, the switching speed of such a PBT is about 15 ps at most. Thus, a higher switching speed PBT is required. To obtain a higher switching speed PBT requires a more complicated structure and special processes.

An object of the present invention is to eliminate the above-mentioned problems.

Another object of the present invention is to provide a fast switching semiconductor device.

A further object of the present invention is to provide a PBT having a heterojunction.

According to the present invention there is provided a semiconductor device including a conductive type emitter layer; a conductive type base layer provided on the emitter layer, the emitter layer having a wider energy bandgap than the base; a conductive type collector layer; comb-shaped or lattice-shaped base electrodes formed adjacent to a heterojunction surface formed by the emitter layer and the base layer, the electrodes being provided through a Schottky junction or an insulating layer to the surrounding emitter and base layers.

FIG. 1 is a cross-sectional view of a conventional PBT;

FIG. 2 is a cross-sectional view of an embodiment according to the present invention;

FIGS. 3 and 5 are partial cross-sectional views of the FIG. 2 embodiment illustrating depletion layers with V.sub.BE >0 and V.sub.CE >0 and V.sub.BE =0 and V.sub.CE >0, respectively;

FIGS. 4 and 6 are energy band diagrams for the structures shown in FIGS. 3 and 5, respectively;

FIG. 7 is an energy band diagram with V.sub.BE =0 and V.sub.CE =0, i.e., normally off;

FIG. 8 is a circuit diagram according to the present invention;

FIGS. 9A to 9D are cross-sectional views illustrating the process of producing a structure according to the present invention;

FIG. 10 is a cross-sectional view of an IC device according to the present invention;

FIG. 11A is a plan view of the comb-shaped base electrode 2 for the FIG. 10 device; and

FIG. 11B is a plan view of a lattice-shaped electrode 2 for the FIG. 10 device.

Before describing the preferred embodiments of the present invention, an explanation of the prior art will be given for reference.

FIG. 1 is a cross-sectional view of a conventional PBT.

As shown in FIG. 1, on a n.sup.+ type GaAs emitter layer 1, a comb-shaped or lattice-shaped base electrode 2 comprising a high melting point metal such as tungsten (W) or a metal silicide such as tungsten silicide (WSi) is formed. Over the entire surface of the base electrode 2 and the emitter layer 1, an n.sup.- type GaAs base layer 3 is formed. On the base layer 3, an n.sup.+ type GaAs collector layer 4 is formed. Reference numerals 5 and 6 denote an emitter electrode and collector electrode, respectively.

In the above-mentioned conventional structure of a PBT, as explained above, the transit time of electrons from the emitter layer 1 to the collector layer 4 through the base electrode 2 is limited, so the switching speed limit is about 15 ps.

FIG. 2 is a cross-sectional view of an embodiment according to the present inveniton.

As shown in FIG. 2, an n type AlGaAs emitter layer 7 is additionally formed on the n.sup.+ type GaAs emitter layer 1 of FIG. 1. The other elements of the structure, for example, the base electrode 2, are the same as in FIG. 1.

The n type AlGaAs emitter layer 7 has a wider energy bandgap than the n.sup.+ type GaAs base layer 3 and n.sup.+ type GaAs collector layer 4. Further, the comb-shaped or lattice-shaped base electrodes 2 are formed on a heterojunction surface comprising the n type AlGaAs emitter layer 7 and the n.sup.- type GaAs base layer 3. As shown in FIGS. 3 and 5 base electrodes 2 are provided through a Schottky junction or insulation layer 10 to the surrounding emitter and base layers 7, 3. This means the base electrodes 2 should not ohmicly contact the base layer 3 or emitter layer 7.

The operation of the PBT according to the present invention will be explained.

FIGS. 3 and 5 are partial cross-sectional views of the FIG. 2 embodiment, illustrating depletion layers when V.sub.BE >0 and V.sub.CE >0, and when V.sub.BE =0 and V.sub.CE >0, respectively.

FIGS. 4 and 6 are energy band diagrams for the structures shown in FIGS. 3 and 5, respectively.

In FIGS. 3 to 6, the areas 8 around the comb-shaped or lattice-shaped base electrodes 2 denote depletion layers, and oe.sub.1 and e.sub.2 denote electrons and hot electrons, respectively.

In FIG. 3, when V.sub.CE (a voltage between the collector layer 4 and the emitter contact 1a)>0, and V.sub.BE (a voltage between the base electrodes 2 and the emitter layer)>0, the PBT is in an ON state. That is, not all the base layer 3 between the base electrodes 2 and the collector 4 is converted to a depletion layer, so that the potential barrier .phi..sub.p is low as shown in FIG. 4. Consequently, electrons e.sub.1 in an emitter contact layer 1a are injected into the base layer 3 through the emitter layer 7. Since there is an energy barrier .phi..sub.B due to the wider band gap emitter layer 7, when electrons are injected into the base layer 3, the injected electrons e.sub.1 obtain high kinetic energy so that the electrons e.sub.1 become hot electrons e.sub.2 with a high initial speed. Therefore, such hot electrons e.sub.2 can pass through the base layer 3 at a high speed so as to reach the collector layer 4, and generate a collector current. In the case of FIG. 3, the voltage between the base and emitter (V.sub.BE) is, for example, 0.3 V, and the voltage between the collector and emitter (V.sub.CE) is, for example, 0.6 V.

On the other hand, when in FIG. 5, V.sub.CE >0 and V.sub.BE =0, the PBT is in an ON state. That is, all of the base layer 3 between the base electrodes 2 and the collector 4 is converted to a depletion layer because of the built in potential between the base electrode 2 and the base layer 3, so that the potential barrier .phi..sub.P is high, as shown in FIG. 6. Consequently, the electrons e.sub.1 in the emitter contact layer 1a are not injected into the base layer 3, and no collector current is generated. In the case of FIG. 5, V.sub.CE is given as 0.2 V. In FIG. 6, the broken line illustrates the conduction band in FIG. 4. Therefore, the PBT turns ON or OFF depending upon whether V.sub.BE >0 or V.sub.BE =0.

As shown in FIGS. 4 and 6, the barrier height of the emitter layer 7 gradually increases from the emitter contact layer 1a to the base layer 3, so as to enable the electrons e.sub.1 in emitter contact layer 1 to be injected into the base layer 3 through the wide band gap layer 7.

The electrons e.sub.1 injected from the emitter layer 7 into the base layer 3 in FIG. 3, lose potential energy crossing the energy barrier. The electrons e.sub.1, however, gain kinetic energy in place of the lost potential energy so that the electrons e.sub.1 change to hot electrons e.sub.2. Thus, the speed of the electrons e.sub.2 in the base layer 3 is increased, for example, to 1.times.10.sup.8 cm/sec.

FIG. 7 is an energy band diagram with V.sub.CE =0 and V.sub.BE =0, i.e., in the normally off state.

FIG. 8 is a schematic diagram of a PBT inventor circuit according to the present invention.

FIGS. 9A to 9D are cross-sectional views illustrating the process of producing a structure according to the present invention.

As shown in FIG. 9A, on an n.sup.+ type GaAs emitter contact layer 1a, an n type Al.sub.x Ga.sub.1-x As emitter layer 7 having a thickness of about 1000 A is formed by molecular beam epitaxy (MBE). The X value of the emitter 7 is changed from 0 to 0.3. When the 1000 .ANG. emitter layer 7 is formed, the X value becomes, 0.3, so that the energy barrier .phi..sub.B is formed between the emitter layer 7 and the base layer 3. Furthermore, the graded value of X in the emitter layer generates the graded energy barrier in the emitter layer 7, which in turn gives rise to the graded energy level between the emitter contact layer 1a and the base layer 3. The emitter layer 7 can also be formed using a chemical vapor deposition (CVD) process may be used.

As shown in FIG. 9B, a tungsten layer having a thickness of about 200 .ANG. is formed on the n type A1.sub.x Ga.sub.1-x As emitter layer 7. The tungsten layer is patterned by a usual photolithography technique to form comb-shaped base electrodes 2.

As shown in FIG. 9C, on the obtained structure, an n-type GaAs base layer 3 having a thickness of about 4000 .ANG. with a carrier concentration of 5.times.10.sup.16 cm.sup.-3 is formed by the MBE process. In place of the MBE process, a vapor phase epitaxy (VPE) process may be used.

As shown in FIG. 9D, an n.sup.+ type GaAs collector layer 4 having a thickness of about 2000 .ANG. is formed on the n.sup.- type GaAs base layer 3 by using the MBE or VPE continuously.

Finally, as shown in FIG. 2, an AuGe/Au layer having a thickness of about 4000 .ANG. is formed on the collector layer 4 and the emitter contact layer 1a to form a collector electrode 5 and an emitter electrode 6.

It is noted that the base electrodes 2 contact the emitter layer 7 and the base layer 3 via Schottky junction or an insulating layer 10.

In the present invention, in place of the GaAs, In.sub.y Ga.sub.1-y As may be used. In place of the A1.sub.x Ga.sub.1-x As, InP and Al.sub.Z In.sub.1-z As may be used.

Further, according to the present invention the order of the position of the emitter layer, the base layer, and the collector layer may be reversed.

In above-mentioned embodiment, a single semiconductor device was explained. However, the single semiconductor device can be easily changed to an IC device. For example, as shown in FIG. 10, on a semiinsulating GaAs substrate 1a each semiconductor layer such as a n.sup.+ type GaAs emitter layer 1 is formed. After that by a selective mesa etching process, a part of the surface of the n.sup.+ type GaAs emitter layer 1 is exposed whereby an emitter electrode 11 may be taken out therefrom.

FIG. 11A is a plan view of a comb-shaped base electrode 2.

In FIG. 11A reference numeral 2a denotes a contact portion.

FIG. 11B is a plan view of a lattice-shaped base electrode 2.