Semiconductor Memory Device Having Two Column Transfer Gate Transistor Groups Independently Provided for a Sense Amplifier and a Programmed Circuit

The present invention relates to a semiconductor memory device including a plurality of programmable read only memory (PROM) cells arranged in a matrix of rows and columns, and it particularly relates to two column transfer gate transistor groups independently provided for a sense amplifier and a programming circuit of the memory device.

FIG. 1 is a schematic diagram of the prior art memory device showing a part related to the present invention. In FIG. 1, a reference symbol QM shows a plurality of PROM cells arranged at intersection points of a matrix formed by a plurality of word-lines WL.sub.0 through WL.sub.m and bit-lines BL.sub.0 through BL.sub.n crossed each other. When an address signal A comes into both of a column decoder 1 and a row decoder 2, the decoders 1 and 2 produce column selecting signals Y.sub.0 through Y.sub.n and row selecting signals X.sub.0 through X.sub.m respectively. Column transfer gate transistors T.sub.0, T.sub.1, and T.sub.n are connected to bit-lines BL.sub.0, BL.sub.1, and BL.sub.n respectively, and each column transfer gate transistor consists of a field effect transistor having a source connected to both of a sense amplifier 3 and a programming circuit 4, a drain connected to the bit-line BL.sub.0, BL.sub.1, or BL.sub.n, and a gate connected to the column decoder 1 to receive the column selecting signal Y.sub.0, Y.sub.1, or Y.sub.n When the address signal A is applied to the memory device, one of the row selecting signals X.sub.0 through X.sub.m is applied to one of the word-lines W.sub.L through WL.sub.m, and one of the column selecting signals Y.sub.0 through Y.sub.n is applied to a gate of one of the column transfer gate transistors T.sub.0 through T.sub.n.

When the memory device is in a state of programming a data signal given from the exterior of the memory device, the state will be called as "a programming mode" hereinafter, a PROM cell must be selected from the PROM cells arranged in the matrix, by both of a row selecting signal (X.sub.0, X.sub.1, or X.sub.m) and a column selecting signal (Y.sub.0, Y.sub.1, or Y.sub.n), and the programming circuit 4 is connected to the selected PROM cell by a selected column transfer gate transistor (T.sub.0, T.sub.1, or T.sub.n so that the data signal applied from the exterior of the memory device is transferred and programmed into the selected PROM cell.

When the memory device is in a state of reading a data signal stored in a selected PROM cell, the state will be called as "a reading mode" hereinafter, the PROM cell is selected the same of the above, and the sensing amplifier is connected to the selected PROM cell by a selected column transfer gate transistor (T.sub.0, T.sub.1, or T.sub.n) so that the data signal stored in the selected PROM cell is read out and transferred to the sense amplifier 3 and amplified.

In FIG. 1, the source of every transfer gate transistor is connected to both of the sense amplifier 3 and the programming circuit 4. However, functionally, either of the sense amplifier 3 or the programming circuit 4 is selected by switching circuits, which are not depicted in FIG. 1, located in the sense amplifier 3 and the programming circuit 4 respectively and controlled by a read-write selecting signal 6 applied from the exterior of the memory device.

FIG. 2 is a schematic diagram of the prior art showing the relation between the column decoder 1 and the selected column transfer gate transistor T.sub.i (i indicates one of the numerals 0 through n). In FIG. 2, the same reference numeral or symbol as in FIG. 1 designates the same unit or part as in FIG. 1, and a metal oxide semiconductor (MOS) transistor is used for all transistors; wherein, a transistor having no mark is an n-channel enhancement type transistor, a transistor having a black dot is an n-channel depletion type transistor, and a transistor having an arrow mark is a p-channel type transistor. When the address signal A consisting of binary signals a.sub.i, a.sub.j, and a.sub.k are applied to a NAND gate 101 of the column decoder 1 so that the binary signals are all in a high (H) level, the output level of the NAND gate 101 becomes low (L), and a buffer inverter 102 of the column decoder 1 produces a column selecting signal Y.sub.i having an H level, so that a column transfer gate transistor T.sub.i becomes conductive. As a result, when the memory device is in the reading mode, the sensing amplifier 3 is connected to the selected PROM cell on a bit-line BL.sub.i, and when the memory device is in the programming mode, the programming circuit 4 is connected to the selected PROM cell. A power supply voltage V.sub.ppi for the NAND gate 101 and the buffer inverter 102 is variable. When the memory device is in the programming mode, the power supply voltage V.sub.ppi becomes a high voltage (for example 21 volts (V)) so that the bit-line is held high with a high voltage (for example 15 V) for programming the data signal into the selected PROM cell. When the memory device is in the reading mode, the voltage V.sub.ppi is switched to a low voltage (for example 5 V).

Recently, a memory device is required to have a fast access time, particularly in the reading mode. However, in the prior art, there is a problem that the memory device cannot operate at high speed in the reading mode because the column transfer gate transistor is commonly used for programming and reading out the data signal. In FIG. 2, a large current is required to flow through the transistor T.sub.i, in the programming mode, for programming the data signal into the selected PROM cell on the bit-line BL.sub.i. Therefore, a channel width of the transistor T.sub.i must be large, which causes an increase in p-n junction capacitance formed between a substrate and a source or drain region of the transistor T.sub.i. This large stray capacitance becomes a heavy load for the sensing amplifier 3 and the PROM cell, so that a data sensing speed obtained in the sense amplifier 3 becomes slow. Furthermore, large capacitance formed between the gate of T.sub.1, T.sub.2, or T.sub.n and its channel also becomes a heavy load for the column decoder 1, so that a rise-time and a fall-time of the column selecting signal (Y.sub.i) are lengthened, which also slow the data access time. A memory device having the PROM cells is usually used in the reading mode, and it is not necessary for the speed of programming the data signal into the selected PROM cell to be high. Thus, the problem stated above is how to realize the fast access time in the reading mode. Increasing the sensitivity of the sense amplifier 3 could be considered for increasing the data reading speed; however, if the sensitivity increases, another problem occurs in that an error due to the noise occurs because the sense amplifier 3 becomes much too critical; such kind of the error cannot be allowed to occur in the memory device. Thus, in the art of designing and fabricating the memory device, a fast access time in the reading mode has been anxiously awaited.

An object of the present invention is to realize a faster access time of the memory device in the reading mode.

The object is achieved by providing two groups of column transfer gate transistors. One is a first group of first column transfer gate transistors for programming the data signals into the selected PROM cells, and the other is a second group of second column transfer gate transistors for reading the data signals from the PROM cells. The two groups are independently provided to the memory device.

FIG. 1 is a schematic diagram of the prior art memory device;

FIG. 2 is a schematic diagram showing a part relating to a column decoder and a column transfer gate transistor of the memory device;

FIG. 3 is a schematic diagram of a memory device firstly embodying the present invention;

FIG. 4 is a schematic diagram showing a part relating to a column decoder and a column transfer gate transistor of the memory device firstly embodying the present invention;

FIG. 5 is a schematic diagram of a memory device secondly embodying the present invention; and

FIG. 6 is a schematic diagram showing a part relating to a column decoder and a column transfer gate transistor of the memory device secondly embodying the present invention.

FIG. 3 is a schematic diagram of a memory device firstly embodying the present invention. In FIG. 3, the same reference numeral or symbol as in FIG. 1 designates the same element or unit as in FIG. 1. The point of the present invention is that the column transfer gate transistors in the prior art memory device shown in FIG. 1 is independently separated into two groups: a first group of first column transfer gate transistors T.sub.W0 through TW.sub.n and a second group of second column transfer gate transistors T.sub.S0 through T.sub.Sn as shown in FIG. 3. The first column transfer gate transistor T.sub.W0, T.sub.w1, or T.sub.wn is for transferring a data signal from the programming circuit 4 to the selected PROM cell on a bit-line BL.sub.0, BL.sub.1, or BL.sub.n in the programming mode, and the second column transfer gate transistor T.sub.S0, T.sub.S1, or T.sub.Sn is for reading out and transferring a data signal stored in a selected PROM cell on the bit-line BL.sub.0, BL.sub.1, or BL.sub.n using the sense amplifier 3 in the reading mode. The first column transfer gate transistors T.sub.W0 through TW.sub.n and the second column transfer gate transistors T.sub.S0 through T.sub.Sn are selected by a write column selecting signal WY.sub.0, WY.sub.1, or WY.sub.n and a read column selecting signals RY.sub.0, RY.sub.1, or RY.sub.n respectively. The write and read column selecting signals are provided in a column decoder 1-2.

FIG. 4 is a schematic diagram showing a part relating to the column decoder 1-2, a first column transfer gate transistor T.sub.Wi, and a second column transfer gate transistor T.sub.Si of the memory device firstly embodying the present invention. In FIG. 4, the same reference numeral or symbol as in FIG. 3 designates the same unit or part as in FIG. 3, all transistors comprise the MOS transistors and their symbols such as the black dot and the arrow indicate the same kinds of the transistors as in FIG. 2.

In this first embodiment, the column decoder 1-2 has two NAND gates 103 and 104 and two buffer inverters 105 and 106. The NAND gate 103 and the buffer inverter 105 are for the programming mode, and the NAND gate 104 and the buffer inverter 106 are for the reading mode. Therefore, a high power supply voltage V.sub.pp (21V for example) is applied to both of the NAND gate 103 and the buffer inverter 105 and a low power supply voltage V.sub.cc (5 V for example) is applied to both of the NAND gate 104 and the buffer inverter 106. The address signal A consisting of binary signals a.sub.i, a.sub.j, and a.sub.k is applied to both of the NAND gates 103 and 104. An inverted reading signal Ris applied to the NAND gate 103 so that the level of the inverted reading signal Ris L in the reading mode and an H in the programming mode. When the address designated by the address signal A is coincides with that of a selecting PROM cell on the bit-line BL.sub.i, the NAND gate 104 makes flow a current. Therefore, the output of the NAND gate 104 becomes an L level, so that the output of the buffer inverter 106, which is equal to a read column selecting signal RY.sub.i, becomes an H level, which makes the second transfer gate transistor T.sub.Si conductive. In the above condition, when the memory device is in the reading mode, the NAND gate 103 cannot make flow its current because the level of the inverted reading signal Rbecomes L, and the read-write selecting signal 6 selects the sense amplifier to operate. Accordingly, the data signal stored in the selected PROM cell is read out and amplified. When the address signal A designates the address of the selecting PROM cell and the memory device is in the programming mode, the NAND gate 103 makes flow a current because the level of the inverted reading signal Rbecomes H. Therefore, the output of the buffer inverter 105, which is equal to a write column selecting signal WY.sub.i, outputs an H level, so that the first column transfer gate transistor T.sub.Wi becomes conductive. In this condition, the NAND gate 104 and the second column transfer gate transistor T.sub.Si also operate as stated above. However, only the programming circuit 4 operates because of the read-write selecting signal 6. In the above, even though the currents ineffectively flow through the NAND gate 104, the buffer inverter 106, and the second column transfer gate transistor T.sub.Si wasting the power consumption of the memory device, the ineffective power consumption does not make much difference to the power consumption in the all memory device. Because the first column transfer gate transistor T.sub.Wi wastes more current than the above ineffective currents in the programming mode.

Thus, in the first embodiment of the present invention, only the second column transfer gate transistor T.sub.Si operates and the first column transfer gate transistor T.sub.Wi does not operate when the memory device is in the reading mode.

FIG. 5 is a schematic diagram of a memory device secondly embodying the present invention. In FIG. 5, the same reference numerals or symbol as in FIG. 3 designates the same element or unit as in FIG. 3. FIG. 6 is a schematic diagram showing a part relating to a column decoder 1-3 and the first and the second column transfer gate transistors T.sub.Wi and T.sub.Si shown in FIG. 5. In FIG. 6, the same reference numeral or symbol as in FIG. 4 designates the same element or unit as in FIG. 4. In the second embodiment, the column decoder 1-3 consists of a NAND gate 107, a switching buffer inverter 108, and a buffer inverter 109 as shown in FIG. 6. Thus, in the second embodiment, there is only one NAND gate, which is a point different from the first embodiment having two NAND gates. When the address designated by the address signal A consisting of the signals a.sub.i, a.sub.j, and a.sub.k coincides with the address of the selecting PROM cell placed on the bit-line BL.sub.i and the memory device is in the programming mode, the output of the NAND gate 107 becomes an L level, and a read signal R is in an L level, so that the output of the switching buffer inverter 108, which is equal to a write column selecting signal WY.sub.i, becomes an H level, which allows to make the first column transfer gate transistor T.sub.Wi conductive. In the above condition, similarly to the first embodiment, the second column transfer gate transistor T.sub.Si also becomes conductive. However, only the programming circuit 4 operates because of the read-write selecting signal 6. When the address signal A designates the address of the selecting PROM cell and the memory device is in the reading mode, the level of the read signal R becomes equal to the V.sub.pp level, so that the write column selecting signal WY.sub.i becomes an L signal, which makes the first column transfer gate transistor T.sub.wi non-conductive and only the second column transfer gate transistor T.sub.Si is conductive.

In the first and the second embodiments stated above, as the column transfer gate transistor of the prior art is separated into the first and the second column transfer gate transistors T.sub.Wi and T.sub.Si, the second column transfer gate transistor T.sub.Si can be made in a narrow channel width because the transistor T.sub.Si requires only a little current to transfer the data signal from the selected PROM cell to the sense amplifier 3. Therefore, the load for the sensing amplifier 3 becomes drastically lighter than that in the prior art. Accordingly, the data sensing speed becomes very fast. Furthermore, for the column decoder 1-2 or 1-3, the load capacitor becomes light, so that both of the rise-time and the fall-time of the read column selecting signal RY.sub.i are shorter than those of the column selecting signals of the prior art.

Concretely explaining the above, the stray capacitance of the second column transfer gate transistor T.sub.S0, T.sub.S1, or T.sub.Sn becomes approximately one eighth of the first column transfer gate transistor T.sub.W0, T.sub.W1, or T.sub.Wn. Therefore, the memory access time is improved to 120 nanoseconds (n-sec) from 150 n-sec which is the time required in the prior art. Incidentally, a current flowing through the second column transfer gate transistor is 100 microamperes. Whereas, a current flowing through the first column transfer gate transistor is several milliamperes. Since the column transfer gate transistors T.sub.0 through T.sub.n of the prior art are separated into two groups in the present invention, the size of the memory device chip increases a little. However, in the first embodiment for example, the increasing ratio is several percent compared with the prior art. The value of several percent is small compared with twenty percent of the improved ratio of the access time.