Current Source Having a Wide Range of Output Voltages

The present invention relates to a current source having a wide range of output voltages, in which source the emitter-collector path of a main transistor, arranged to define the value of the current of the current source, is arranged in series with the emitter-collector path of at least one output transistor.

Such a current source is known from U.S. Pat. No. 3,940,683.

By arranging at least one output transistor in series it is possible to obtain output voltages higher than those normally attainable with the I.C. fabrication process for a transistor, but the maximum output voltage then differs substantially from the available supply voltage, which difference increases as the number of output transistors increases.

The invention proposes a current source of the type defined in the opening paragraph, whose current is comparatively large and which can operate at output voltages ranging between one collector-emitter voltage of an output transistor in the saturation mode V.sub.CEsat and a value as close as possible to the supply voltage.

The principle underlying the invention is to combine each output transistor with an associated control transistor of the opposite type whose emitter potential is fixed by coupling this control transistor to another stage, and to operate the output transistors in the BV.sub.CEO mode for low output voltages.

The current source in accordance with the invention is therefore characterized in that it comprises n output transistors, where n.gtoreq.2, the first output transistor having its collector connected to the emitter of the main transistor, the p.sup.th transistor, where 1<p.ltoreq.n, having its collector connected to the emitter of the (p-1).sup.th transistor, the emitter of the n.sup.th transistor constituting the output of the current source, and in that every q.sup.th output transistor is associated with a q.sup.th control transistor of the opposite type, whose base includes at least one diode poled in the forward direction and referred (i.e. coupled) to a q.sup.th reference potential, whose collector is connected to the base of the corresponding q.sup.th output transistor, and whose emitter is connected to the collector of the (q-r).sup.th output transistor if q>r and to the collector of the main transistor as well as to a supply voltage source if q.ltoreq.r, where r.gtoreq.1.

It is to be noted that U.S. Pat. No. 3,940,683 discloses a circuit of different design, consisting of a current source comprising cascaded transistors in which only the main transistor includes a diode poled in the forward direction in its base.

In a preferred embodiment r is smaller than or equal to the integer contained in b minus one, b being the ratio between the BV.sub.CEO values of the npn and pnp transistors, for example, r=2 and p=5.

In an advantageous embodiment said reference potentials are each fixed at the maximum value corresponding to the minimum possible values for the collector-emitter voltages of the output transistors in the saturation mode V.sub.CEsat.

The invention will now be described in more detail, by way of non-limitative example, with reference to the accompanying drawings, in which:

FIGS. 1 to 3 by way of illustration show test circuits not previously published by the Applicant, and

FIG. 4 shows an embodiment of the invention.

In FIG. 1 a pnp-type main transistor T.sub.0 has its emitter coupled to a supply voltage source V.sub.c via a resistor R.sub.0 and has its collector connected to the emitter of a transistor T.sub.1 whose collector is connected to the emitter of a transistor T.sub.2. The transistors T.sub.1 and T.sub.2 have their bases connected to two diodes in series, which diodes (D.sub.1, D'.sub.1) and (D.sub.2, D'.sub.2) are poled in the forward direction and serve to ensure that the transistors T.sub.1 and T.sub.2 are operated in the BV.sub.CEO mode for low levels of the output voltage V.sub.s. The number of diodes needed is dictated by the values of the voltages to be handled by these diodes. For this purpose the cathodes of the diodes D'.sub.1 and D'.sub.2 (points A and B respectively) are brought to potentials determined by the current sources (T".sub.1, R".sub.1) and (T".sub.2, R".sub.2) respectively and by the values of the resistors R.sub.1 and R.sub.2, which are respectively arranged between points A and B and the common mode terminal.

A transistor T.sub.3 having its base and collector short-circuited and cooperating with a current source I.sub.3 constitutes a conventional current mirror with the transistors T.sub.0, T".sub.1 and T".sub.2. The output voltage V.sub.s is available on the collector of the transistor T.sub.2. This output voltage varies depending on the load applied to the collector of the transistor T.sub.2.

When the output voltage V.sub.s is low (for example of the order of 0.7 V) the transistors T.sub.1 and T.sub.2 will operate in the BV.sub.CEO mode, while the transistor T.sub.0 remains in a normal mode of operation. When the output voltage V.sub.s approximates to the value of the supply voltage V.sub.c (for example, 30 V) the transistors T.sub.1, T.sub.2 and T.sub.0 will operate in the saturation mode.

The problem with this circuit arrangement is that it is difficult to realize integrated pnp transistors supplying a collector current which is adequate for specific uses, for example 1 mA for driving a varicap diode of a tuner in a radio or TV receiver.

In FIG. 2 this current problem is solved by employing cells comprising a pnp transistor and an npn transistor. The collector current of the pnp transistor is divided by the current gain .beta. of the associated npn transistor, which itself can supply an adequate current.

In FIG. 2 each cell comprises an npn transistor (T.sub.10 . . . T.sub.15) and a pnp transistor (T'.sub.10 . . . T'.sub.15), the collector of the pnp transistor being connected to the base of the associated npn transistor and the emitter of the pnp transistor being connected to the collector of the npn transistor. This type of cell, for use in current sources, is known per se, from GB 1,285,621 (FIG. 9) or German patent application DE-OS 2,157,626 or DE-OS 2,738,205. The transistors T'.sub.11 to T'.sub.15 have diodes D.sub.11, D.sub.12, D.sub.13, D.sub.14 and D'.sub.14, D.sub.15 and D'.sub.15 respectively, poled in the forward direction, connected to their bases and each referred to a given fixed potential. The transistors T.sub.16 and T.sub.17 are arranged to form a current mirror with the transistor T.sub.10.

Thus, three pnp transistors have been replaced by six cells because the BV.sub.CEO of an npn transistor is smaller than that of a pnp transistor, in the present example by a factor of approximately 3.

The problem of this arrangement is that as V.sub.s, i.e. the output voltage available on the emitter of T.sub.15, increases its maximum value V.sub.smax is limited to

where

V.sub.BE npn =base-emitter voltage of an npn transistor .perspectiveto.0.8 V, V.sub.p =V.sub.CEsat pnp=the emitter-collector voltage of a saturated pnp transistor .perspectiveto.0.1 V,

which means that

FIG. 3 relates to a circuit arrangement which enables this difference to be reduced and to be brought to approximately 6 V.sub.CEsat npn. In order to achieve this the emitter of the transistors T'.sub.11 to T'.sub.15 are no longer connected to the collectors of the transistors T.sub.11 to T.sub.15, but are coupled to fixed reference potentials via resistors R'.sub.11 to R'.sub.15.

For low output levels the transistor T'.sub.15 should be operated fully in the BV.sub.CEO mode and the emitter voltage of the transistor T'.sub.15 should be fixed at approximately V.sub.s(min) +V.sub.BEnpn +BV.sub.CEO, V.sub.s(min) being the minimum value of the voltage V.sub.s.

Conversely, for high output levels the collector voltage of the transistor T'.sub.15 should be very close to V.sub.C. This implies inverse operation of this transistor and hence a limited use of this arrangement as regards the output levels.

The circuit arrangement in accordance with the invention shown in FIG. 4 comprises npn type transistors T.sub.30 to T.sub.35 whose collector-emitter paths are arranged in series in the same way as those of the transistors T.sub.10 to T.sub.15.

A transistor T'.sub.30 having its collector connected to the base of the transistor T.sub.30 and having its emitter connected to the supply voltage source V.sub.c is arranged as a conventional current mirror with the transistors T.sub.36 and T.sub.37. The transistors T'.sub.31 to T'.sub.35 constituting the control transistors associated with the output transistors T.sub.31 to T.sub.35 have their collectors connected to the bases of the transistors T.sub.31 to T.sub.35 respectively. The emitters of the transistors T'.sub.31 and T'.sub.32 are connected to the supply voltage source V.sub.C, and the emitters of the transistors T'.sub.33 to T'.sub.35 are connected to the collectors of the transistors T.sub.31 to T.sub.33 respectively. The bases of the transistors T'.sub.31 to T'.sub.35 are connected to diodes D.sub.31, D.sub.32, D.sub.33 and D'.sub.33, D.sub.34 and D'.sub.34, D.sub.35 and D'.sub.35 respectively, which diodes are poled in the forward direction and serve to enable operation in the BV.sub.CEO mode in the case of low output voltages V.sub.s on the emitter of the transistor T.sub.35. The base reference potential of the transistors T'.sub.31 to T'.sub.35 is determined by current sources formed by the transistors T".sub.31 to T".sub.35 arranged as a current mirror with the transistors T.sub.36 and T.sub.37, and by four resistors R.sub.32 to R.sub.35 arranged in series. The resistors R.sub.32 to R.sub.34 are arranged in parallel between the cathodes of the diodes D.sub.32 and D'.sub.33 (points A' and B'), D'.sub.33 and D'.sub.34 (points B' and C'), D'.sub.34 and D'.sub.35 (points C' and D') respectively. The resistor R.sub.35 is arranged between the cathode of the diode D'.sub.35 and the common-mode terminal.

This arrangement corresponds to a situation in which V.sub.c .ltoreq.6 BV.sub.CEO (npn) in order to ensure a stable voltage and for which:

For a low output voltage V.sub.s, the ratio b between the BV.sub.CEO of the npn and pnp transistors enables the collector of a control transistor to be connected to that of an output transistor which differs by b-1=2 places in rank. In general it is possible to realize a shift by a number of ranking places equal to the maximum of (aliquot part of b)-1, i.e E(b)-1. The integer part E(b) of a number "b" is the portion of the number to the left of the decimal point.

For high output voltages the emitter potential of, for example, the transistor T'.sub.35 is equal to the collector potential of the transistor T.sub.33, so that the drawback of the experimental circuit shown in FIG. 3 is avoided, because the emitter voltage of the transistors T'.sub.33, T'.sub.34 and T'.sub.35 varies as a functiion of the output voltage V.sub.s.

Moreover, as will now be shown, the maximum voltage available on the output is closer to V.sub.c than in the experimental circuit of FIG. 2.

Let V.sub.BE be the base-emitter voltage of a transistor (approximately 0.7 V).

Let V.sub.n be the emitter-collector voltage of a saturated npn transistor.

Let V.sub.p be the emitter-collector voltage of a saturated pnp transistor.

For high output voltages V.sub.s the transistors T.sub.30 to T.sub.35 and T'.sub.30 to T'.sub.35 are saturated.

The emitter voltage of T.sub.30 can reach the value

The emitter voltage of T.sub.31 can reach the value

The emitter voltage of T.sub.32 can reach the value

The emitter voltage of T.sub.33 can reach the value

The emitter voltage of T.sub.34 can reach the value

The maximum output voltage V.sub.s available on the emitter of the transistor T.sub.35 can reach the value

By way of example a method of fabricating bipolar integrated circuits, enabling analog and digital circuits to be integrated simultaneously, has the following characteristic values:

The maximum permissible voltage is then:

For the number of cascaded transistors in FIG. 4 the circuit can be powered with 30 V, which for example enables a varicap diode to be operated between approximately 0.7 V and 28 V. Since the diodes are formed by means of npn transistors, which can handle a maximum voltage of 20 V (operation in the BV.sub.CEO mode), the voltages to be handled being higher than said value for the bases of the transistors T'.sub.33 to T'.sub.35, two diodes are required for these transistors.

A requirement to be met is that the transistors T.sub.30 and T'.sub.30 should not come into the avalanche region because these are the two transistors which limit the current.

It is advantageous to provide the resistor bridge R.sub.32 to R.sub.35 in order to ensure that the base potential of the transistors T'.sub.33 to T'.sub.35 has the maximum value corresponding to the minimum possible value for the collector-emitter voltages of the transistors T.sub.30 to T.sub.32. The collector voltage of the transistor T.sub.31 is, for example, V.sub.B' +3V.sub.BE, V.sub.B' being the voltage on point B'. The potentials on points A', C' and D' are referred to as V.sub.A', V.sub.C' and V.sub.D'.

For example, the following relationship may be used:

where

V.sub.D31 is the voltage across the diode D.sub.31

V.sub.BE (T'.sub.31)=the base-emitter voltage of the transistor T'.sub.31 in the BV.sub.CEO region.

The voltages on points B', C' and D' are then dictated by the requirement imposed by the above relationship.

Thus, the circuit shown in FIG. 4 enables the advantages of the circuits shown in FIGS. 2 and 3 to be obtained without their drawbacks. The circuits shown in FIG. 4 has the additional advantage that the difference between the collector currents of the transistors T.sub.30 and T.sub.35 is small in comparison with the situation in FIG. 3, because the currents drawn by the pnp transistors are re-injected into the npn transistors.

Another advantage of this circuit arrangement is that it can operate even in the case where the transistors T'.sub.33 to T'.sub.35 are in the BV.sub.CEO mode, the main current being limited by the transistor T.sub.30 .