Semiconductor Memory Device Having a Register

The present invention generally relates to a semiconductor memory device, and in particular to a semiconductor memory device having a register in addition to memory cells. More particularly, the present invention relates to a random access memory device having a register which can be suitably used as a memory for image processing.

Generally, data write-in and read-out operations with respect to a memory cell of a conventional random access memory device (hereafter simply referred to as a RAM device) are carried out per a predetermined data unit consisting of 1, 4 or 8 bits, (for example). However, such operations cannot sufficiently satisfy various needs of customers. In particular, in the field of image processing, it is required to employ a RAM device which has a very large amount of the storage capacity and can transfer data at a high-speed. Currently, a RAM device capable of satisfying the above requirement has been proposed. For example, 64 kbit and 256 kbit dynamic random access memory devices exclusively designed for the image processing are available.

As the memory capacity per one semiconductor device increases, there exists another requirement for a higher-grade random access memory capable of transferring data at a higher speed and also performing the image processing more simply. From this viewpoint, currently there has been considerable activity in the development of a RAM device which has a register built therein in addition to memory cells to thereby provide special functions. For example, the built-in register may be used as a mask register, which can control, per one bit unit, data to be written into a memory cell. Further, the use of the built-in register makes it possible to update, within one reference cycle, data made up of a predetermined number of bits which exceeds a number of input pins of the RAM device. The RAM device having these special functions can perform the complex image processing at a high-speed. However, it is to be noted that it is impossible to transfer data stored in the built-in register to an external circuit and to directly know the contents of the built-in register. Therefore, validiting the operation of the RAM device becomes very complicated. For example, it is very difficult to find whether an erroneous operation arises from the built-in register or data itself. This disadvantage leads to an increase in a time term taken to develop the RAM device, a more complicated testing procedure thereof, and an increase in cost.

Accordingly, a general object of the present invention is to provide a novel and useful semiconductor memory device having a register in which the disadvantages of the conventional one have been eliminated.

A more specific object of the present invention is to provide a semiconductor memory device device having a register capable of writing data into a built-in register and reading out data therefrom. Thereby, the validation test of the operation of the DRAM device can be performed with ease. Additionally, a time taken to develop the RAM device can be decreased, and an efficiency in the delivery inspection can be improved.

Another object of the present invention is to provide a semiconductor memory device device having a register capable of accessing the built-in register while accessing the memory cells.

The above objects of the present invention can be achieved by a memory device device having a register comprising a memory cell array has a series of memory cells; a data bus; an input/output circuit provided between the memory cell array and the corresponding data bus; a register for storing predetermined data; and a transfer gate being connected between the data bus and the register. The device also comprises a first data buffer for transferring data on the data bus to an external circuit; and a second data buffer for transferring data derived from the external circuit to the data bus. In addition to the above elements, the device comprises a controlling circuit for disconnecting the input/output circuit from the data bus and turning OFF the transfer gate in a first operation mode and for connecting the input/output circuit to the data bus and turning ON the transfer gate in a second operation mode. In the first operation mode, a data read or write operation is performed between the memory cell array and the external circuit via the data bus and either one of the first and second buffers. Alternatively in the second operation mode the data read or write operation is performed between the register and the external circuit via the transfer gate, the data bus and either one of the first and second buffers.

Other objects, features and advantages of the present invention will become apparent from the following detailed description when read in conjunction with the accompanying drawings.

FIG. 1 is a block diagram of a preferred embodiment of the present invention;

FIG. 2 is a view showing how to combine FIGS. 2A through 2C;

FIGS. 2A through 2C are circuit diagrams of the embodiment shown in FIG. 1;

FIG. 3 is a circuit diagram of a mode discrimination circuit shown in FIGS. 1 and 2A;

FIG. 4 is a circuit diagram of a circuit for controlling connection/disconnection of a sense amplifier and input/output gate shown in FIGS. 1 and 2A;

FIG. 5 is a circuit diagram of a 1/4 column address decoder shown in FIG. 2A;

FIG. 6 is a view for showing connections between a column decoder and a data bus;

FIG. 7 is a circuit diagram of a column address decoder and the sense amplifier and input/output gates;

FIG. 8 is a view showing signal states of signals used in embodiment;

FIGS. 9(A) through 9(I) show waveforms of signals used in a register operation mode in the embodiment;

FIGS. 10(A) through 10(I) show waveforms of signals used in a normal operation mode in the embodiment;

FIGS. 11(A) through 11(G) show waveforms of signals used in a block operation mode in the embodiment; and

FIGS. 12(A) through 12(G) show waveforms of signals in a read transfer mode and a write transfer mode in the embodiment.

FIG. 1 is a block diagram of a preferred embodiment of the present invention. The illustrated configuration is a RAM device of a 4-bit structure designed for the image processing. Referring to FIG. 1, the RAM device includes four memory cell arrays 1 through 4, each of which has a memory capacity of 256 Kbits. The RAM device also includes an address buffer 5 which enters an address signal composed of address bits A.sub.0 through A.sub.N (N=7 in the illustrated embodiment), a row address decoder 6, column address decoders 7 through 10 and blocks 11 through 14 each including a sense amplifier and an input/output gate (an I/O gate). The column address decoders 7 through 10 and blocks 11 through 14 are associated with the memory cell arrays 1 through 4, respectively. Data registers 15 through 18 convert parallel data which is outputted from the memory cell arrays 1 through 4 per one row to corresponding serial data. Pointers 19 through 22 select the respective beginning bits of data when the data is read out in the serial form from the data registers 15 through 18. The use of the pointers 19 through 22 can provide an easier scrolling processing. Serial input/output buffers 23 through 26 are used for reading out data from the memory cell arrays 1 through 4 and writing data therein per one row unit. The serial input/out buffers 23 through 26 are controlled by a serial port enable signal (SE) and a timing signal (TIM) which are supplied from a transfer controller 27. References SD.sub.0 though SD.sub.3 represent serial data.

The transfer controller 27 inputs a mask mode enable/write enable signal (ME/WE) and a transfer enable/output enable signal (TR/OE), both of which are supplied from a memory controlling circuit (not shown) such as a central processing unit. The transfer controller 27 controls a data transferring operation between the memory cell arrays 1 through 4 and the data registers 15 through 18, respectively. Further the transfer controller 27 controls input and output operations of the serial input/output buffers 23 through 26. A write clock generator 28 inputs the mask mode enable/output enable signal TR/WE, and generates a write clock signal, which is then supplied to input/output buffers 35 through 38. A clock generator 29 inputs a row address strobe signal (RAS) and a column address strobe signal (CAS) which are supplied from the memory controlling circuit, and generates inner clock signals .phi..sub.A and .phi..sub.B from the received signal. The clock generator 29 also supplies a refresh address counter 30 with a count signal. The refresh address counter 30 counts the count signal supplied from the clock generator 29 and supplies the address buffer 5 with an address signal for refreshing the memory cell arrays 1 through 4 in order to maintain the data therein.

Selectors 31 through 34 are used for selecting one datum from among data supplied from color data registers 39 and 40, and data DQ.sub.0 through DQ.sub.3 supplied from the external circuit. The input/output buffers 35 through 38 are controlled by a normal operation mode/block operation mode switching signal B and a register operation mode setting signal R (described later), the transfer enable/output enable signal TR/OE, and the write clock signal derived from the write clock generator 28. The color data registers 39 (#1) and 40 (#2) are used for storing color data which are frequently used during the image processing. A mask register 41 has a function of inhibiting, per one bit unit, a write-in operation with respect to data DQ.sub.0 through DQ.sub.3 supplied from the external circuit (not shown).

A control circuit 42 is provided in the RAM device according to the embodiment of the present invention. The control circuit 42 has a function of reading out data stored in the built-in registers consisting of the color data registers 39 and 40 and the mask register 41 to the external circuit, and of writing data supplied from the external circuit into the built-in registers. The control circuit 42 is supplied with a special function signal (SF) and a low active write enable signal (WE) which are fed from the memory controlling circuit. The control circuit 42 is also provided with row address bits RA.sub.0 and RA.sub.1 which are a part of the row address signal. The control circuit 42 is further supplied with the clock signals .phi..sub.A and .phi..sub.B which are derived from the clock generator 29. The control circuit 42 produces the register operation mode setting signal R and the normal operation mode/block operation mode switching signal B from the special function signal SF and the write enable signal WE, and outputs them in synchronism with the clock signals .phi..sub.A and .phi..sub.B. The register operation mode setting signal R and the normal operation mode/block operation mode switching signal B are fed to the column decoder 7, and also to the input/output buffers 35 through 38 via a timing adjustment circuit 43. When the register operation mode setting signal R is kept at a high-level (hereafter simply referred to "H"), a write-in operation or a read-out operation may be performed between the registers 39, 40 and 41 and the external circuit. When the normal operation mode/block operation mode switching signal B determines a mode to be selected at the time of writing data into the memory cell arrays 1 through 4 or reading out data therefrom. In the present embodiment, there are two modes which may be selected depending on the normal operation mode/block operation mode switching signal; one of which is a normal mode, and the other of which is a block write-in mode. These modes will be described in detail later. The control circuit 142 also produces register selecting signals a.sub.1, a.sub.2 and a.sub.3, which are supplied to transfer gates T.sub.1, T.sub.2, and T.sub.3 associated with the registers 39, 40 and 41, respectively. When the register operation mode is selected, any one of the registers 39, 40 and 41 is selected by the register selecting signals a.sub.1, a.sub.2 and a.sub.3.

FIGS. 2A through 2C are detailed block diagrams showing the configuration shown in FIG. 1. To begin with, referring to FIG. 2A, the selector 31 is provided with respect to the first data bit DQ.sub.0 out of the 4-bit data DQ.sub.0 through DQ.sub.3. The selector 31 selects one signal from among an output of a selector S.sub.1, a lowest digit bit C.sub.10 of the color register 39, and a lowest digit bit C.sub.20 of the color register 40. The selectors 32, 33 and 34 are provided with respect to the second, third and fourth data bits of the 4-bit data DQ.sub.0 through DQ.sub.3. The selectors 32, 33 and 34 have functions similar to that of the selector 31. A register decoder D.sub.2 determines which one of the input signals is to be selected, depending on a value of the first data bit DQ.sub.0. The register decoder D.sub.2 is activated when the register operation mode setting signal R is set at "H". A sense buffer 351 and a write amplifier 352 are provided with respect to the lowest digit bits C.sub.10 and C.sub.20 of the color registers 39, and 40. The input/output buffer 35 shown in FIG. 1 is composed of the sense buffer 351 and the write amplifier 352. Similarly the input/output buffers 36, 37 and 38 are composed of sense buffers 361, 371 and 381, and write amplifiers 362, 372 and 382, respectively. The enable/disable states of the write amplifiers 352, 562, 372 and 382 are controlled by an enable/disable controlling signal T consisting of the normal operation mode/block operation mode switching signal B and an output of a timing adjustment circuit TA.sub.3 which delays the register operation mode setting signal R by a predetermined time. The write amplifiers 352, 362, 372 and 382 provided with a lowest bit digit M.sub.0 of the 4-bit mask register 41 via a timing adjustment circuit TA.sub.4. When the digit M.sub.0 is 0, outputs of the write amplifiers 352, 362, 372 and 382 are masked. The output terminals of the write amplifiers 352, 363, 372 and 382 are connected to a data bus DB.sub.1 with respect to the memory cell array 1, as shown in FIG. 2A. The enable/disable states of the sense buffers 351, 361, 371, and 381 are controlled by an output signal of a timing adjustment circuit TA.sub.2, which delays the register operation mode setting signal R by a predetermined time. Additionally, the enable/disable state of the sense buffer 351 is controlled by an output signal of a timing adjustment circuit TA.sub.1, which delays the normal operation mode/block operation mode setting signal B. The sense buffers 361, 371 and 381 are connected to the data bus DB.sub.1 as shown in FIG. 2A. The sense buffer 351 is connected to the data bus DB.sub.1 via a selector S.sub.5, which is controlled by a 1/4 address decoder D.sub.1 (this is omitted in FIG. 1 for the sake of simplicity).

The color registers 39 and 40 each having the 4-bit structure are connected to the data bus DB.sub.1 through the transfer gates T.sub.1 and T.sub.2, respectively. The transfer gates T.sub.1 and T.sub.2 are controlled by the register selecting signals a.sub.1 and a.sub.2, respectively. The lowest digit bits C.sub.10 and C.sub.20 of the color registers 39 and 40 are supplied to the selectors 31 through 34 with respect to the memory cell array 1. The second lowest digit bits C.sub.11 and C.sub.21 of the color registers 39 and 40 are supplied to selectors 131 through 134 with respect to the memory cell array 2, as shown in FIG. 2B. The third lowest highest digit bits C.sub.12 and C.sub.22 of the color registers 39 and 40 are supplied to the selectors 231 through 234, as shown in FIG. 2B. The highest digit bits C.sub.13 and C.sub.23 of the color registers 39 and 40 are supplied to the selectors 331 through 334, as shown in FIG. 2C. As shown in FIG. 2B, write amplifiers 452, 462, 472 and 482, a sense amplifier 451 and a selector S.sub.6 are provided with respect to the memory cell array 2 which are coupled with a data bus DB.sub.2. With respect to the memory cell array 3 coupled with a data bus DB.sub.3, there are provided write amplifiers 552, 562, 572 and 582, a sense amplifier 551 and a selector S.sub.7. As shown in FIG. 2C, there are provided write amplifiers 652, 662, 672 and 682, a sense amplifier 651 and a selector S.sub.8 with respect to the memory cell array 4 which is coupled with the data bus DB.sub.4.

Returning to FIG. 2A, the mask register 41 is connected to the data bus DB.sub.1 through the transfer gate T.sub.3, which is controlled by the register selecting signal a.sub.3. The lowest digit bit M.sub.0 of the mask register 41 is supplied to the write amplifiers 352, 362, 372 and 382 with respect to the memory cell array 1 via the timing adjustment circuit TA.sub.4, as shown in FIG. 2A. The second lowest digit M.sub.1 of the mask register 41 is supplied to write amplifiers 452, 462, 472 and 482 with respect to the memory cell array 2 via a timing adjustment circuit TA.sub.5, as shown in FIG. 2B. The third lowest digit M.sub.2 of the mask register 41 is fed to write amplifiers 552, 562, 572 and 582 with respect to the memory cell array 3 via a timing adjustment circuit TA.sub.6, as shown in FIG. 2B. The highest digit M.sub.3 of the mask register 41 is supplied to write amplifiers 652, 662, 672 and 682 with respect to the memory cell array 4 via a timing adjustment circuit TA.sub.7, as shown in FIG. 2C. Thereby the write-in operation can be inhibited for each digit bit.

The control circuit 42 consists of a register decoder 421 and a mode discrimination circuit 422. The register decoder 421 determines levels of the register selecting signals a.sub.1, a.sub.2 and a.sub.3, depending on the two bits RA.sub.0 and RA.sub.1 out of the row address signal. For example, when the bit RA.sub.0 is at "L", and the bit RA.sub.1 is at "L", the register selecting signal a.sub.3 is set at "H", and the other signals a.sub.1 and a.sub.2 are set at "L".

FIG. 3 is a circuit diagram of the mode discrimination circuit 422. The mode discrimination circuit 422 includes latch circuits 422a and 422b, inverters 421c and 421d, and AND gates 421e, 421f and 421g. The latch circuits 421a and 421b input the special function signal SF and the write enable signal WE in response to the clock o.sub.CA derived from the clock generator 29. Outputs of the latch circuits 421a and 421b are fed to the AND gates 421e and 421f and also to inputs of the inverters 421c and 421d, respectively. An output of the inverter 421c is supplied to the AND gates 421f and 421g. An output of the inverter 421d is supplied to the AND gate 421g. The clock signal .phi..sub.B derived from the clock generator 29 is supplied to the AND gates 421e, 421f and 421g. An output of the AND gate 421e is the register operation mode setting signal R. An output of the AND gate 421f is a normal operation mode setting signal B.sub.N, and output of the and gate 421g is a block operation mode setting signal B.sub.B. The normal operation mode/block operation mode switching signal consists of the signals B.sub.N and B.sub.B. The relationship between the input and output of the mode discrimination circuit 422 is shown in TABLE 1.

As described in detail later, when the RAM device is set in the register operation mode, the sense amplifier and I/O gate 11 is disconnected from the data bus DB.sub.1. This is achieved by a bus connection/disconnection controlling circuit 45 (this is omitted in FIG. 1 for the sake of simplicity).

FIG. 4 is a circuit diagram of the bus connection/disconnection controlling circuit 45. As shown, the circuit 45 consists of an inverter 45a and an AND gate 45b. An input of the inverter 45a is supplied with the register mode setting signal R, and an output thereof is fed to the AND gate 45b. The AND gate 45 is also provided with the normal operation mode/block operation mode switching signal B, which is obtained by subjecting the normal operation mode setting signal B.sub.N and the block operation setting signal B.sub.B to an OR operation by an OR gate 44 shown in FIG. 2A (which is omitted in FIG. 1 for the sake of simplicity). When the RAM device is set in the register operation mode, an output (.phi..sub.CA) of the AND gate 45b which is supplied to each column of the column decoder 7, is kept at "L". The column decoder 7 includes, as shown in FIG. 7, an AND gates 71a, 72a, 73a, . . . for each column. Therefore, during the register operation mode, the AND gates 71a, 72a, 73a, . . . are closed and thereby the sense amplifier and I/O gate 11 is disconnected from the data bus DB.sub.1. Thus, the write-in operation and the read-out operation between the color registers 39 and 40 and the external circuit can be achieved.

FIG. 5 is a circuit diagram of the 1/4 address decoder D.sub.1 shown in FIG. 2. The 1/4 address decoder D.sub.1 is composed of inverters 51a and 51b, AND gates 52a through 52f, and OR gates 53a through 53d. The normal operation mode setting signal B.sub.N is supplied to the inverter 51a and the AND gate 52a, and the block operation mode setting signal B.sub.B is supplied to the inverter 51b and AND gate 52b. Outputs of the inverters 51a and 51b are applied to the AND gates 52b and 52a, respectively. An output of the AND gate 52a is fed to the AND gates 52c through 52f, and an output of the AND gate 52b is delivered to the OR gates 53a through 53d. An address bit A.sub.0 of the column address signal and its inverted bit A.sub.0 are supplied to the AND gates 52c and 52d, respectively and an address bit A.sub.1 and its inverted bit A.sub.1 are supplied to the AND gates 52e and 52f, respectively. Outputs of the AND gates 52c through 52f are supplied to the OR gates 53a through 53d. When the RAM device is set in the normal operation mode where the signal B.sub.N is set at "H", and the signal B.sub.B is set at "L", all the gates of AND gates 52c through 52f are opened, and therefore, the address bits A.sub.0, A.sub.0, A.sub.1 and A.sub.1 are allowed to pass therethrough. At this time, because the output of the AND gate 52b is kept at "L", the above address bits are also permitted to pass through the OR gates 53a through 53d. As a result, a column may be selected depending on values of the address bits. On the other hand, when the RAM device is set in the block operation mode where the signal B.sub.N is set at "L" and the signal B.sub.B is set at "H", the output of the AND gate 52b is set at "H". Therefore, all the outputted address bits A.sub.0.sup.*, A.sub.0.sup.*, A.sub.1.sup.* and A.sub.1.sup.* are maintained at "H", and consequently four columns can be selected at one time. In FIG. 5, the other address bits A.sub.2 -A.sub.n (n=7 in the example of FIG. 1) are supplied directly to the column address decoder 7. This will be described in detail later.

FIG. 6 shows connections between the data bus DB.sub.1 and each column in the column address decoder cell 7. As shown, each column is connected to two bits out of the 8-bit data bus DB.sub.1. FIG. 7 shows a circuit configuration of the column address decoder 7 and the sense amplifier and I/O gate 11. As illustrated, the column address decoder 7 is constructed by one AND gate 71a for each of the columns. The sense amplifier and I/O gate 11 is constructed by two MOS transfer gates 72a and 72b and one sense amplifier SA provided for each column. In FIG. 7, a symbol MC is a memory cell.

A description is now given of an operation of the embodiment having the above-described structure with reference to FIG. 8 which is a view showing an operation truth table as well as FIGS. 9 through 12 which are timing charts of the operation of the embodiment. The operation mode of the embodiment can be classified mainly into the register operation mode, the normal operation mode and the block operation mode. A description of the operation is given in this sequence.

As shown in FIGS. 9(A) and 9(E), when the row address strobe signal RAS is switched to "L", the row address is entered into the memory cell arrays 1 through 4. At this time, the transfer enable/output enable signal TR/OE of FIG. 9(D) and the special function signal SF are kept at "H" and "L", respectively. At this time, the column address strobe signal CAS of FIG. 9(B) is kept at "H". Then, as shown in FIG. 9(H), the write enable signal WE which is a low-active signal is kept at "L". Therefore, the mode discrimination circuit 422 outputs the register operation mode setting signal R which is set at "H". At this time, the normal operation mode setting signal B.sub.N and the block operation mode setting signal B.sub.B are maintained at "L". Because the register operation mode setting signal R is set at "H", the register decoder 421 is enabled. On the other hand, the sense amplifier and I/O gate 11 is disconnected from the data bus DB.sub.1, and therefore the memory cell array 1 is disconnected therefrom. This is because the register operation mode setting signal R is set at "H", and therefore the AND gate 45b shown in FIG. 4 produces the control signal .phi..sub.CA which is set at "L". Because the write enable signal WE is kept at "L", an inner control signal W is kept at "H", and therefore the timing adjustment circuit TA.sub.3 is activated. As a result, the register operation mode setting signal R is allowed to be applied to the write amplifier 352, 362, 372 and 382 via the timing adjustment circuit TA.sub.3. Thereby, the write amplifiers 352, 362, 372 and 382 are all enabled. On the other hand, an inner control signal W which is a low-active signal is set at "L", when the write enable signal WE is set at "L". Thereby, the register operation mode setting signal R is prevented from being transmitted by the timing adjustment circuit TA.sub.2, and all the the sense amplifiers 351, 361, 371 and 381 are disabled. The timing adjustment circuits TA.sub.2 and TA.sub.3 are provided in order to set the sense amplifiers 351, 361, 371 and 381 and the write amplifiers 352, 362, 372 and 382 in the enable state after the memory cell array 1 is completely disconnected from the data bus DB.sub.1.

The selectors 31 through 34 selects the outputs of the selectors S.sub.1 through S.sub.4, respectively, because they are supplied with the delayed register operation mode setting signal R which is set at "H". At this time, the selectors S.sub.1 through S.sub.4 select the data DQ.sub.0 through DQ.sub.3, respectively, because they are supplied with the delayed register operation mode setting signal R which is set at "H". Before the write enable signal WE of FIG. 9(H) is switched to "L", as shown in FIG. 9(A), in synchronism with the fall of the row address strobe signal RAS, the row address derived from the row address decoder 6 is entered into the memory cell array 1. At this time, two address bits RA.sub.0 and RA.sub.1 out of the row address signal is used for selecting any one of the registers 39, 40 and 41. For example, when address bit RA.sub.0 is set at "L", and the address bit RA.sub.1 is set at "L", the register selecting signal a.sub.3 is set at "H", and thereby the transfer gate T.sub.3 is turned ON. As a result, the mask register 41 becomes connected to the data bus DB.sub.1. In this manner, the data DQ.sub.0 is written into the lowest digit bit M.sub.0 of the mask register 41 via the selector S.sub.1, the selector 31, the write amplifier 352, the data bus DB.sub.1 and the transfer gate T.sub.3. Similarly, the data DQ.sub.1 through DQ.sub.3 are written into the regions M.sub.1 through M.sub.3 of the mask register 41.

As shown in FIGS. 9(A) and 9(E), at the time of the fall of the row address strobe signal RAS supplied from the memory controlling circuit, the special function signal SF is set at "H". At this time, the column address strobe signal CAS of FIG. 9(B) and the transfer enable/output enable signal TR/OE of FIG. 9(D) are kept at "H". Then, as shown in FIG. 9(H), the write enable signal WE is kept at "H". Therefore, the mode discrimination circuit 422 outputs the register operation mode setting signal R which is set at "H" as in the case of the write-in operation described before. At this time, the normal operation mode setting signal B.sub.N and the block operation mode setting signal B.sub.B are maintained at "L". Because the register operation mode setting signal R is set at "H", the register decoder 421 is activated. On the other hand, the sense amplifier and I/O gate 11 is disconnected from the data bus DB.sub.1, and therefore the memory cell array 1 is disconnected therefrom. This is because the register operation mode setting signal R is set at "H", and therefore the AND gate 45b shown in FIG. 4 produces the control signal .phi..sub.CA set at "L". The write enable signal WE is kept at "H", and thereby the inner control signal W is kept at "L". Therefore, the timing adjustment circuit TA.sub.3 is disabled, so that the write amplifier 352, 362, 372 and 382 are also disactivated. On the other hand, the low-active inner control signal W is set at "H", when the write enable signal WE is set at "H". Thereby, the register operation mode setting signal R is allowed to pass through the timing adjustment circuit TA.sub.2. Consequently, all the the sense amplifiers 351, 361, 371 and 381 are activated.

As shown in FIG. 6, the selector S.sub.5 selects only a data line DB.sub.1a positioned at the highest order of the data lines of the data bus DB.sub.1 in response to the output of the 1/4 address decoder D.sub.1. Thereby, the sense buffer 351 becomes connected to the bit lines DB.sub.1a through the selector S.sub.5. In this manner, the data stored in the region M.sub.0 of the mask register 41 is applied to the sense buffer 351 through the selector S.sub.5. And the data stored in the regions M.sub.1 through M.sub.3 of the mask register 41 are applied to the sense buffers 361, 371 and 381, respectively. As a result, the data stored in the mask registers 41 can be transferred to the external circuit as the data DQ.sub.0 and DQ.sub.3.

The register operation mode with respect to the color register 39 or 40 is the same as the operation with respect to the mask register 41.

When the row address strobe signal RAS is switched to "L" as shown in FIG. 10(A), the row address is supplied to the memory cell arrays 1 through 4. At this time, the special function signal SF is kept at "L", as shown in FIG. 10(E). At this time, the column address strobe signal CAS of FIG. 10(B) and the transfer enable/output enable signal TR/OE of FIG. 10(D) are maintained at "H". In the write-in operation of the normal operation mode, the write enable signal WE is switched to "L". Therefore, the mode discrimination circuit 422 produces the register operation mode setting signal R which is set at "L". Thereby, the register decoder 421 is disabled, and all the register selecting signals a.sub.1 through a.sub.3 are set at "L". Hence, all the transfer gates T.sub.1 through T.sub.3 are turned OFF, and the color registers 39 and 40 and the mask register 41 are disconnected from the data bus DB.sub.1. On the other hand, the normal operation mode/block operation mode switching signal B which is a result of the OR operation performed by the OR gate 44 shown in FIG. 2A, is kept at "H", and the register operation mode setting signal R is kept at "L". As a result, the AND gate shown in FIG. 4 sets the output .phi..sub.CA at "H", so that the column decoder 7 is enabled. Therefore, memory cell array 1 is connected to the data bus DB.sub.1. Similarly, the column decoders 8, 9 and 10 are enabled by the application of the control signal .phi..sub.CA set at "H" which is derived from the AND gate 45b shown in FIG. 4, so that they are connected to the data buses DB2, DB3 and DB4. The inner control signal W and W are set at "H" and "L", respectively, when the write enable signal WE of FIG. 10(H) is switched to "L". Therefore, the timing adjustment circuits TA.sub.2 and TA.sub.3 are disabled and enabled, respectively, and thereby the sense buffers 351, 361, 371 and 381 are disabled, while the write amplifiers 352, 362, 372 and 382 are enabled. At this time, the selector S.sub.1 selects the output of the data DQ.sub.0 and the selector 31 selects the output of the selector S.sub.1. Then in response to the fall of the column address strobe signal CAS of FIG. 10(B), the column address is supplied to the memory cell arrays 1 through 4. Then the data DQ.sub.0 is written into the memory cell array 1 per four-bit unit via the selectors S.sub.1 through S.sub.4, the selectors 31 through 34, the write amplifiers 352, 362, 372 and 382, the data bus DB.sub.1 and the column decoder 7 in this sequence. Similarly, the data DQ.sub.2 through DQ.sub.4 are written into the memory cell arrays 2 through 4 per four-bit unit.

When the row address strobe signal RAS is switched to "L" as shown in FIG. 10(A), the row address is supplied to the memory cell arrays 1 through 4. At this time, the special function signal SF is kept at "L", as shown in FIG. 10(E). At this time, the column address strobe signal CAS of FIG. 10(B) and the transfer enable/output enable signal TR/OE of FIG. 10(D) are maintained at "H". In the read-out operation of the normal operation mode, the write enable signal WE is switched to "H". At this time, the mode discrimination circuit 422 produces the register operation mode setting signal R which is set at "L" as in the case of the write-in operation of the normal operation mode described before. Hence, all the transfer gates T.sub.1 through T.sub.3 are turned OFF, and the color registers 39 and 40 and the mask register 41 are disconnected from the data bus DB.sub.1 as in the case of the write-in operation of the normal operation mode. On the other hand, the normal operation mode/block operation mode switching signal B which is a result of the OR operation performed by the OR gate 44 shown in FIG. 2A, is kept at "H", while the register operation mode setting signal R is kept at "L". As a result, the AND gate 45b shown in FIG. 4 sets the output .phi..sub.CA at "H", so that the column decoder 7 is enabled. Therefore, memory cell array 1 is connected to the data bus DB.sub.1. Similarly, the column decoders 8, 9 and 10 are enabled by the application of the control signal .phi..sub.CA set at "H" which is derived from the AND gate 45b shown in FIG. 4, so that they are connected to the data buses DB2, DB3 and DB4. The inner control signal W and W are set at "L" and "H", respectively, because the write enable signal WE is maintained at "H" as shown in FIG. 10(F). Therefore, the timing adjustment circuits TA.sub.2 and TA.sub.3 are enabled and disabled, respectively, and thereby the sense buffers 351, 361, 371 and 381 are enabled and the write amplifiers 352, 362, 372 and 382 are disabled. At this time, the data which is outputted to the data bus DB.sub.1 per four-bit unit is selected by the selector S.sub.5, depending on a value of the column address CA.sub.0 composed of the address bits A.sub.0.sup.* and A.sub.0.sup.* and a value of the CA.sub.1 composed of the address bits A.sub.1.sup.* and A.sub.1.sup.*. The selected data is outputted as the DQ.sub.0 via the sense buffer 351. Similarly, the selected data are read out from the memory cell arrays 2 through 4 as the data DQ.sub.1 through DQ.sub.3, respectively.

In this operation mode, four mutually adjacent columns can be selected at the same time. This corresponds to nibble bits of the conventional dynamic random access memory. In the following description, it is assumed that data to be written into cells are the contents stored in the color register 39 or 40. Therefore, the data stored in the color register 39 or 40 can be written, at one time, into memory cells per a block unit corresponding to arbitrary four color registers. For example, in the case where the color register is composed of 4 bits, the data can be written into the memory cells per 16-bit unit. Either one of the color registers 39 and 40 can be selected, depending on the level states of the input data DQ.sub.0 through DQ.sub.3. For example, in the case where the data DQ.sub.0 is set at "L", the contents of the color register 40 are data to be written into memory cells in the first columns of four cell blocks (which correspond to four bits by four columns) which are selected by the column address signal. On the other hand, the DQ.sub.0 is set at "H", the data stored in the color register 39 is data to be written into memory cells in the first columns of the four memory cell blocks. In the case where the data DQ.sub.1 is kept at "H", the contents of the color register 39 are data to be written into memory cells in the second columns of the selected memory cell blocks. Alternatively in the case where the data DQ.sub.1 is kept at "L", the contents of the color register 40 are data to be written into memory cells in the second columns of the selected memory cell blocks. Likewise, the data DQ.sub.2 is used as data for instructing which one of the color registers 39 and 40 should be selected to be written into memory cells in the third columns of the memory cell blocks. And the data DQ.sub.3 is used as data for instructing which one of the color registers 39 and 40 should be selected to be written into memory cells in the fourth columns of the memory cell blocks. For example, when all the data DQ.sub.1 through DQ.sub.3 are set at "L", the contents stored in the color register 40 are written into memory cells in all of the four columns of one memory cell array.

The block operation mode is further described with reference to FIGS. 11(A) through 11(G). As shown, when the row address strobe signal RAS falls, the column address strobe signal CAS and the transfer enable signal TR/OE are kept at "H". And, at this time, the special function signal SF and the write enable signal WE are kept at "L". Then, the row address is entered into the memory cell arrays 1 through 4. Subsequently, when the column address strobe signal CAS falls and the write enable signal WE is kept at "L", the columns of the memory cell arrays 1 through 4 into which data is to be written. In the block operation mode, the data is written into memory cells per four-bit unit. Therefore, as described before with reference to FIG. 5, the four column address bits A.sub.0.sup.*, A.sub.0.sup.*, A.sub.1.sup.* and A.sub.1.sup.* are set to 1, the column address which is selected per the block unit is determined by the other column address bits in addition to the column address bits A.sub.0.sup.*, A.sub.0.sup.*, A.sub.1.sup.* and A.sub.1.sup.*.

This is described by referring to FIGS. 12(A) through 12(G). When the column address strobe signal CAS and the write enable signal WE are both set at "L" at the time of the fall of the row address strobe signal RAS, data with respect to one row of each of the memory cell arrays 1 through 4 can be transferred to the data registers 15 through 18 per one row unit at a high-speed. On the other hand, when the column address strobe signal CAS and the write enable signal WE are set at "H" and "L" at the time of the fall of the row address strobe signal RAS, data can be transferred to memory cells with respect to one row of each of the memory cell arrays 1 through 4 at a high-speed.

As described above, according to the present invention, the contents of the built-in registers such as registers 39, 40 and 41 can be arbitrarily read out and transferred to the external circuit, and also data derived from the external circuit can be written into the built-in registers. Therefore, it becomes possible to directly know the contents of the built-in registers at any time. This results in an improvement in the validation test of the operation of the RAM device. Additionally, it becomes possible to easily make sure cause of the erroneous operation of the RAM device, for example, to ascertain whether or not the erroneous operation is caused by a fault with respect to the built-in registers.

The present invention is not limited to the embodiment and variations and modifications may be made without departing from the scope of the present invention.