Image Processing Apparatus

1. Field of the Invention

The present invention relates to an image processing apparatus for obtaining a reproduced image of a high quality.

2. Related Background Art

It has already been proposed to reproduce an image including halftones with a dither method or a density pattern method. However, in either method, a satisfactory tonal rendition can only be obtained with a large threshold value matrix, the use of which however, results in a low resolution or in an image texture with marked periodicity of the threshold matrixes. Consequently, an image of a high quality cannot be obtained.

In order to avoid the above-mentioned drawback, it is conceivable, in the dither method, to obtain multi-level dot information through the use of plural dither matrixes. However, such method requires a complex circuit structure in order to synchronize different dither matrixes, and inevitably gives rise to a large and complicated system. Consequently such method is associated with a certain limitation.

Processing of image information is preferably conducted in a multi-level state where the number of bits per pixel is large, but a limited number of bits per pixel is desirable for transmission or storage of image information.

Also it is already known that a correction of a digital input image signal to a desired contrast results in a loss in the number of tonal levels. In order to overcome such drawback it is possible to expand the dynamic range of the input image signal by increasing the number of bits of said image signal, but such increase in the amount of information of the input image signal not only results in the increase in the number of signal lines but also requires a complex and inevitably expensive structure for information storage or processing.

An object of the present invention is to eliminate the above-mentioned drawbacks.

Another object of the present invention is to provide an improvement on the image processing apparatus.

Still another object of the present invention is to provide an image processing apparatus capable of providing a reproduced image of a high image quality.

Still another object of the present invention is to provide an image processing apparatus capable of providing an excellent image with a simple structure.

Still another object of the present invention is to provide an image processing apparatus capable of providing an excellent tonal rendition with a relatively limited amount of information.

Still another object of the present invention is to provide an image processing apparatus capable of providing a reproduced image of a high resolution, a satisfactory tonal rendition and a high image quality.

Still another object of the present invention is to provide an image processing apparatus capable of providing a reproduced image of a high image quality with a high speed.

The foregoing and still other objects of the present invention will become fully apparent from the following description, which is to be taken in combination with the attached drawings.

FIG. 1 is a block diagram of an image processing apparatus constituting a first embodiment of the present invention;

FIGS. 2A to 2G are wave form charts showing signals in the circuit shown in FIG. 1;

FIG. 3 is a circuit diagram of a second embodiment;

FIGS. 4A to 4D and FIGS. 5A to 5D are wave form charts showing signals in the circuit shown in FIG. 3;

FIG. 6 is a block diagram of a third embodiment;

FIGS. 7A to 7M are wave form charts showing signals in the circuit shown in FIG. 6;

FIG. 8 is a chart showing the relationship between input image signal and record density in the absence of gamma (contract) correction;

FIG. 9 is a chart showing examples of gamma correction for each line in the third embodiment;

FIG. 10 is a chart showing the relationship between input image signal and record density after gamma correction;

FIG. 11 is a view showing an example of an output pattern according to the third embodiment;

FIG. 12 is a block diagram of a fourth embodiment of the image processing apparatus;

FIGS. 13A-13K are wave form charts showing signals in the circuit shown in FIG. 12;

FIG. 14 is a chart showing a conversion characteristic of a pulse width modulated signal in the fourth embodiment; and

FIG. 15 is a schematic view of a laser beam printer in which the present invention is applicable.

Now the present invention will be clarified in detail by description of the preferred embodiments thereof, shown in the attached drawings.

FIG. 1 is a block diagram of an image processing apparatus constituting a first embodiment of the present invention, wherein a digital data output device 1 effects A/D conversion on image data from an unrepresented CCD sensor or an unrepresented television camera, and releases digital data of a predetermined number of bits including density information. Said digital data may be temporarily stored in a memory or may be entered from an external device, for example, through communication. Said digital data output device 1 releases pixel data for one a line (e.g., one scan line or raster line) in consecutive manner, and the data of a first pixel are at first latched in a first latch circuit 2, and then latched in a second latch circuit 3 in response to succeeding image clock signals.

A first adding circuit 4 adds the image data latched in the first latch circuit 2 with the succeeding image data, and a second adding circuit 5 adds the data obtained by addition in the first adding circuit 4 with the data latched in the second latch circuit 3. In this manner the second adding circuit 5 releases a value obtained by adding the data of three consecutive pixels. In the first embodiment there are employed two adding circuits 4 and 5, but it is also possible to add the data of three consecutive pixels with a single adding circuit. Said added data of three consecutive pixels is then converted into an analog value by a D/A converter 6, and supplied, through an amplifier 7, to a terminal of a comparator 10.

A pulse pattern generator 8 generates a pulse pattern signal in synchronization with the data of three pixels. In the present embodiment said pulse pattern signal is triangular, but it may also be sawtooth shaped, trapezoidal or sinusoidal. The wave form of said pulse pattern signal is suitably selected according to the size of dot or the characteristics of the recording or display unit. Said pulse pattern generator 8 can be easily constructed, for example, with usual components such as resistors and capacitors. Said pulse pattern signal is matched with the dynamic range of the image data in an amplifier 9, and supplied to the other input terminal of the comparator 10. The analog image data supplied from the D/A converter 6 is compared in the comparator 10 with the pulse pattern signal, and is subjected to pulse width modulation for every three pixels. In the present embodiment, the digital image data released from the digital data output device 1 contains 4 bits or 17 levels per pixel, but the image signal after the addition in the second adding circuit 5 contains 49 levels per pixel. After pulse width modulation, said image signal of 49 levels is supplied, for example, to a modulating circuit for modulating a laser beam. Said laser beam is turned on and off according to the pulse width to form an image containing intermediate tones (or halftones) on an unrepresented recording medium.

In synchronization with horizontal synchronization signals generated by a horizontal synchronization signal generator 14 for respective lines, a counter 12 reduces the frequency of a reference clock signal, supplied from a reference clock generator 11, for example to 1/8 thereby generating an image clock signal which is employed as a transfer clock signal for image data transfer or a synchronization clock signal for the adding circuits. Said horizontal synchronization signal may be internally generated or supplied from the outside. In a case where the present invention is applied to a laser beam printer, said horizontal synchronization signal corresponds to the already known beam detection signal, indicating the beam scanning position. A ternary counter 13 reduces the frequency of the clock signal from the counter 12 further to 1/3 thereby generating a clock signal for the pulse pattern generator 8, adding circuit 5 and D/A converter 6.

FIG. 2 is a wave form chart showing various signals in the circuit shown in FIG. 1. Fig. 2A indicates the reference clock signal of a predetermined high frequency generated by the reference clock generator 11, FIG. 2B indicates the aforementioned horizontal synchronization signal, and FIG. 2C indicates the image clock signal obtained by reducing the frequency of the reference clock signal in the counter 12. As explained before, the pixel clock signal in Fig. 2C is synchronized with the horizontal synchronization signal. FIG. 2D indicates a pulse pattern synchronization clock signal, obtained by reducing the frequency of the image clock signal, from the counter 12, to 1/3 in the ternary counter 13. The clock signal FIG. 2D is utilized as a synchronization signal for pulse pattern generation and is supplied to the pulse pattern generator 8. FIG. 2E indicates an image signal obtained by direct D/A conversion of the output signal from the digital data output device 1, without the additions. In FIG. 2F, the broken line indicates the pixel data after addition of three consecutive pixels, while the solid line indicates the triangular signal from the pulse pattern generator 8, after amplification in the amplifier 9. In these charts the image density is higher at a lower position. The comparator 10 compares the added signal, as represented by the broken line in FIG. 2F with the pulse pattern signal, as represented by the solid line in FIG. 2F to obtain a binary pulse-width modulated signal as shown in FIG. 2G.

As explained above, in the present embodiment, the digital image data of three consecutive pixels are added, then converted into analog image data and compared with a triangular wave of a predetermined period. As the result there is obtained an almost continuous pulse width modulation enabling one to obtain a reproduced image of a satisfactory tonal rendition.

In the present embodiment, since the pulse pattern synchronization clock signal synchronized with the horizontal synchronization signal is formed from the reference clock signal of a frequency higher than that of the synchronization signal for pulse pattern generation, the fluctuation of the pulse patterns generated by the pulse pattern generator 8, for example the aberrations of the pulse patterns between the first and second lines, is equal to 1/24 of the cycle of the pulse pattern.

The use of pulse patterns of such reduced fluctuation enables almost continuous pulse width modulation of the density information, thus providing a reproduced image of a high image quality.

In the present embodiment, the pulse pattern is generated for every three image clock pulses, but it may also be generated more or less frequently, in consideration of the response speed, resolution or the like of the apparatus.

Also in the present embodiment, the pulse patterns are generated in the same manner on all lines, but it is preferable to displace the synchronization signal for pulse pattern generation by a pixel for each line. In this manner the center of each pulse modulated signal is displaced in succession from line to line, so that the output image macroscopically appears as a diagonal screen pattern which looks natural to the human eyes. Also, such method is desirable in consideration of the resolving power, since said centers of pulse-width modulated signals are more evenly distributed over the entire image. FIG. 3 is a block diagram of a second embodiment, capable of displacing the synchronization signal for pulse pattern generation by a pixel for every line in the above-explained manner.

In FIG. 3, components of equivalent functions as those in FIG. 1 are represented by same numbers. In the circuit shown in FIG. 3, the ternary counter 13 generates a pulse pattern synchronization clock signal for every three image clock pulses, in synchronization with the horizontal synchronization signal as explained before. D-flip-flops 15 and 16 generate synchronization signals which are respectively delayed by 1 and 2 image clock signals from said pulse pattern synchronization clock signal generated by the counter 13. In response to the signal from the horizontal synchronization signal generator 14, a ternary counter 17 generates three line gate signals, which are respectively supplied to AND gates 18-20. More specifically, in response to each horizontal synchronization signal, the output terminals of the counter 17 cyclically generate said gate signals which are supplied to the AND gates 18-20. In this manner the synchronization signal for pulse pattern generation is switched for every line. The synchronization clock signals supplied from the AND gates 18-20 are supplied, through an OR gate 21, to the pulse pattern generator 8.

FIG. 4A indicates an image clock signal generated by the counter 12 and corresponds to the signal shown in FIG. 2C. FIGS. 4B, 4C and 4D respectively show the output clock signals from the ternary counter 13, flip-flop 15 and flip-flop 16. The clock signal shown in FIG. 4B corresponds to the clock signal shown in FIG. 2D. FIG. 5 shows the horizontal synchronization signal and the output signal from the ternary counter 17. In response to the horizontal synchronization signal shown in FIG. 5A, the ternary counter 17 generates three line gate signal shown in FIGS. 5B, 5C and 5D, of which one is selected in succession and supplied to the pulse pattern generator 8.

In this manner the circuit shown in FIG. 3 provides pulse patterns which are displaced by a pixel for every line, so that the centers of the pulse width modulated signals are displaced in succession from line to line.

FIG. 6 shows a third embodiment of the present invention, wherein components equivalent to those in FIG. 1 are represented by the same numbers.

A digital data output device 1 effects A/D conversion on image data from an unrepresented CCD sensor or an unrepresented television camera, and releases digital data of a predetermined number of bits including density information. Said digital data may be temporarily stored in a memory or may be entered from an external device for example through communication. Said digital data output device 1 releases pixel data of a line in consecutive manner, and the data of a first pixel are at first latched in a first latch circuit 2, and then latched in a second latch circuit 3 in response to a succeeding image clock signal.

A first adding circuit 4 adds the image data latched in the first latch circuit 2 with the succeeding image data, and a second adding circuit 5 adds the data obtained by addition in the first adding circuit 4 with the data latched in the second latch circuit 3. In this manner the second adding circuit 5 releases a value obtained by adding the data of three consecutive pixels. In the present embodiment there are employed two adding circuits 4 and 5, but it is also possible to add the data of three consecutive pixels by means of a single adding circuit.

In the present third embodiment, the digital image data from the digital data output device 1 have 65 density levels, but the signal after the addition of three consecutive pixels in the adding circuit 5 has 193 density levels. The thus-added signal is subjected to a gamma correction in a correction circuit 22 composed of a correction map ROM. Said correction is conducted in different manner from line to line, and is repeated for every three lines. The corrected image signal is converted into analog data by the D/A converter 6, then corrected in amplitude by the amplifier 7 and supplied to a terminal of the comparator 10. On the other hand, the pulse pattern generator 8 generates a triangular pulse pattern synchronized with every three consecutive pixels, and said pulse pattern is matched, in the amplifier 9, with the dynamic range of the image signal and supplied to the other terminal of the comparator 10. Said pulse pattern generator 8 can be easily constructed with usual components such as resistors and capacitors. The comparator 10 compares the input image signal with the repeated triangular pulse pattern, thereby pulse-width modulating the image information of every three pixels and generating a pulse-modulated binary signal. After pulse width modulation, said image signal is supplied, for example, to a modulating circuit for modulating a laser beam. Said laser beam is turned on and off according to the pulse width to form an image containing intermediate tones on an unrepresented recording medium.

In synchronization with horizontal synchronization signal generated by the horizontal synchronization signal generator 14 for respective lines, the counter 12 reduces the frequency of the reference clock signal, supplied from the reference clock generator 12, for example to 1/8 thereby generating the image clock signal which is employed as the image clock signal for image data transfer. A ternary counter 23 reduces the frequency of said image or pixel clock signal further to 1/3, thereby generating three pulse pattern synchronization signals, mutually displaced by a pixel clock signal, for generating pulse patterns. The counters 12, 23 effect counting operations in synchronization with the horizontal synchronization signal. Also in response to the horizontal synchronization signal, a ternary counter 24 releases, in succession, three signals mutually spaced by the period of a line. Said signals are supplied to a gate 25 for selecting three pulses pattern synchronization clock signals supplied from the counter 23, and are also utilized for selecting the correction map for each line in the correction circuit 22.

FIG. 7 is a wave form chart showing various signals in the circuit shown in FIG. 6. FIG. 7A indicates the reference clock signal generated by the reference clock generator 11, and FIG. 7B indicates the horizontal synchronization signal. Said horizontal synchronization signal may be generated internally, or supplied from the outside. In a case where the present invention is applied to a laser beam printer, said horizontal synchronization signal corresponds to an already known beam detection signal indicating the scanning position of the beam. FIG. 7C indicates the pixel clock signal released from the counter 12, in synchronization with the horizontal synchronization signal. As explained before, said pixel clock signal is formed by reducing the frequency of the reference clock signal to 1/8. The ternary counter 23 further reduces the frequency of the pixel clock shown in FIG. 7C to 1/3 to generate pulse pattern synchronization clock signal shown in FIGS. 7D-7F of every three consecutive pixels, which are mutually displaced by a pixel clock and of which one is selected for each line and supplied to the pulse pattern generator 8 through AND gates 25a-25c and an OR gate 25d. FIG. 7G shows a case where the digital image signal from the digital data output device 1 is directly subjected to D/A conversion. In FIGS. 7H-7J, broken lines indicate signals obtained by addition of pixel data of three pixels in the adding circuit 5, correction in the correction circuit 22 and the D/A conversion in the D/A converter 6. The correction of the added signal is conducted in respectively different manners for different lines, so that three different signals are obtained after correction even when same input image signal is entered in three lines. The broken lines in FIGS. 7H-7J indicate a case of same signals supplied in three consecutive lines, and it will be understood that the forms of image signals become different in different lines after the correction. In these charts the image density is higher at a lower position.

The solid lines in FIGS. 7H-7J indicate triangular pulse patterns released from the pulse pattern generator 8. As will be apparent from these charts, the triangular patterns are displaced by a pixel clock from line to line. The comparator 10 compares the corrected image signal with the pulse pattern to generate the pulse-width modulated binary data as shown in FIGS. 7K-7M. The comparator 10 releases the signal shown in FIGS. 7K, 7L and 7M respectively in the first, second and third lines.

As explained in the foregoing, in the third embodiment, the image data obtained by adding the data of three consecutive pixels are corrected, then converted into analog image data and compared with a triangular wave of a predetermined frequency. As the result there is provided an almost continuous pulse width modulation, and there is obtained a reproduced image of satisfactory tonal rendition (or tonality).

Also in said third embodiment, since the number of density levels is increased by the addition of information of plural pixels, a gamma correction does not reduce the number of density levels and a smooth tonal rendition is obtained.

Furthermore, in said third embodiment, in which the synchronization signal for pulse pattern generation is successively displaced by a pixel from line to line, the centers of the pulse-width modulated signals are likewise displaced, so that the resulting image macroscopically appears as a diagonal screen pattern which is natural to the human eyes. Also such pattern is desirable in consideration of the resolving power since such centers are more evenly distributed over the entire image.

Though the pulse pattern employed in the third embodiment is triangular, it can also be of sawtooth shape, sinusoidal or trapezoidal. The form of the pulse pattern is selected in consideration of the linearity of the output device to the pulse width and the mode of growth of each dot. For example, each dot grows on both sides in the case of a triangular or sinusoidal pattern, while each dot grows on one side only in the case of a saw-tooth pattern.

In the following there will be explained the gamma correction effected in the correction circuit 22. FIG. 8 shows an example of the relationship between the input image signal and the recording density, obtained where the image signal is multi-width modulated and recorded on a laser beam printer without correction. In this case, if a same pulse-width modulation is applied, the density rises steeply in the beginning but only gradually increases afterwards in any of three lines, and the linearity is far from desirable. A broken line in Fig. 8 indicates an ideal relationship between the input image signal and the record density. In the third embodiment, correction is conducted in a different manner for each line and is repeated for every three lines. In this example the correction circuit 22 is constructed in such a manner that an input-output relationship shown in FIG. 9(line (a)) is obtained for the first line, a relationship shown in FIG. 9(line (b)) is obtained for the second line, and a relationship shown in FIG. 9(line (c)) is obtained for the third line. In this manner there is obtained a relationship of a very good linearity as shown by Fig. 10(line (c)). In FIG. 10(line (a)) is obtained when the correction line shown in FIG. 9(line (a)) is solely used, and a relationship shown in FIG. 10(line (b)) is obtained when the correction line shown in FIGS. 9(line (a)) and 9(line (b)) are combinedly used.

FIG. 11 shows an example of output pattern obtained with the circuit of the third embodiment. In this example the input data have a constant density over the entire area, but pulse-width modulation as represented by hatched areas is obtained due to different correction from line to line. Also as explained before, the centers of growth of dots are displaced by a pixel between the neighboring lines. In FIG. 11 a square block corresponds to a pixel.

In the foregoing explanation of the third embodiment, the pulse pattern is generated for every three pixel clock pulses, but its frequency can be suitably increased or decreased. Also the number of pixels to be together added is not limited to three but can be suitably determined, in consideration of the response speed or resolving power of the apparatus.

It is also possible to select different cycle periods for the pulse pattern generation and for the addition of pixel data.

Also in the foregoing description, the pulse patterns are displaced by a pixel between the neighboring lines, but the amount of such displacement may be selected to be larger than or equal to zero. In the case of zero displacement, the dot pattern appears as vertical lines.

Also, in the foregoing description, the same correction is repeated for every three lines, but said number of lines can be suitably selected. Also it is possible to treat plural pixels as a block (which can be an entire line if desired), and to apply different corrections to different blocks, repeating the same correction for every predetermined number of blocks. It is furthermore possible to apply different corrections for different pixels. Furthermore, the gamma correction may be made selectable. As an example, the characteristic line may be made adjustable between points A and B in FIG. 9.

Furthermore, the gamma correction may be made prior to the addition of data, instead of after the addition of data as explained before.

FIG. 12 shows a fourth embodiment of the present invention, wherein components equivalent functions to those in FIG. 1 are represented by same numbers.

A digital data output device effects A/D conversion on image data from an unrepresented CCD sensor or an unrepresented television camera, and releases digital data of a predetermined number of bits including density information. Said digital data may be temporarily stored in a memory or may be entered from an external device for example through communication. Said digital data output device 1 releases pixel data of a line in consecutive manner, and the data of a first pixel are at first latched in a first latch circuit 2, and then latched in a second latch circuit 3 in response to a succeeding pixel clock signal. The data latched in first and second latch circuits 2, 3 and the data of a succeeding pixel, i.e., the data of three consecutive pixels, are added in an adding circuit 26.

In the present embodiment, the digital image data released from the output device 1 contain 65 density levels, but the signal added in said adding circuit 26 contains 193 density levels. The thus-added signal is converted into an analog value in the A/D converter 6, then corrected in amplitude by the amplifier 7, and supplied to a terminal of the comparator 10. On the other hand, pulse pattern generators 8a, 8b, 8c selectively generate three pulse patterns synchronized with said three pixels. Said pulse pattern generators can be easily constructed with usual components such as resistors and capacitors. Said pulse patterns are respectively amplified in amplifiers 9a, 9b, 9c and are supplied, through a mixing circuit 27, to the other terminal of the comparator 10. The comparator 10 compares the input image signal with the pulse patterns repeatedly generated, thereby pulse-width modulating the image information of every three pixels and releasing a corresponding pulse-width modulated binary signal. Said modulated image signal is supplied, for example, to a modulating circuit for modulating a laser beam. Said laser beam is turned on and off according to the width of the pulses to form an image containing intermediate tones on an unrepresented recording medium.

The pulse pattern generators 8a, 8b and 8c respective generate a sinusoidal pulse pattern, a triangular pulse pattern and an inverted sinusoidal pulse pattern.

The counter 12 reduces the frequency of the reference clock signal, supplied from the reference clock generator 11, for example to 1/8, thus forming the pixel clock signal for transferring pixel data. The ternary counter 13 further reduces the frequency of said pixel clock signal to 1/3, thus generating the pulse pattern synchronization clock signal for generating the pulse patterns. In this manner the ternary counter 13 generates synchronization pulses for every three pixels, in synchronization with the horizontal synchronization signal generated for each line by the horizontal synchronization signal generating circuit 14. Said horizontal synchronization signal may be generated internally or entered from the outside. In case the present invention is applied to a laser beam printer, the horizontal synchronization signal corresponds to an already known beam detection signal indicating the scanning position of the beam. The pulse pattern synchronization clock signal supplied from the ternary counter 13 is supplied, either through a gate 28, 29 or 30, to one of the pulse pattern generator 8a, 8b, 8c, according to the selection of one of the terminals A, B and C of a gamma selector 31.

When said terminal A of the gamma selector 31 is selected, said pulse pattern synchronization clock signal is supplied, through the AND gate 28, to the pulse pattern generator 8a.

Likewise, when the terminal B is selected, said clock signal is supplied to the pulse pattern generator 8b, and, when the terminal C is selected, said clock signal is supplied to the pulse pattern generator 8c.

The terminals A, B, C of the gamma selector 31 may be manually selected by the operator or automatically selected for example by a control circuit such as a CPU according to the characteristics of an output device.

FIG. 13 is a wave form chart showing various signals in the circuit shown in FIG. 12. In FIG. 13A indicates the reference clock signal generated by the reference clock generator 11. FIG. 13B indicates the aforementioned horizontal synchronization signal, and FIG. 13C represents the pixel clock signal generated by the counter 12 in synchronization with said horizontal synchronization signal. FIG. 13D represents the pulse pattern synchronization clock signal, obtained by reducing the frequency of said pixel clock signal to 1/3 in the ternary counter 13. FIG. 13E indicates the analog level when the image signal from the digital data output device 1 is directly subjected to D/A conversion, wherein the image density is higher at a lower position. In the present embodiment, due to the addition of data of three consecutive pixels, the analog image signal obtained from the D/A converter 6 assumes a form as represented by a broken line in FIGS. 13F-13H. The solid lines in FIGS. 13F-13H indicate pulse patterns which are generated respectively by the pulse pattern generators 8a, 8b, 8c and of which one is selected in the present embodiment. FIGS. 13I-13K represent the output signals of the comparator 10, indicating a fact that the character of the binary data is varied according to the selection of the pulse pattern generator even if a same image signal is supplied to the comparator 10. More specifically the output binary signal assumes a form as shown in FIG. 13I, 13J or 13K respectively when the pulse pattern generator 8a, 8b or 8c is selected.

As explained in the foregoing, in the present embodiment, the digital image data of three consecutive pixels are added, then converted into analog image data and compared with a selected pulse pattern of a predetermined frequency. In this manner there is obtained an almost continuous pulse width modulation, leading to a reproduced image of satisfactory tonal rendition.

Also, in the present embodiment, since the pulse pattern synchronization clock signal synchronized with the horizontal synchronization signal is formed with a reference clock signal of a frequency higher than that of the synchronization signal for pulse pattern generation, the fluctuation of the pulse patterns generated by the pulse pattern generator, for example, the aberration of the pulse patterns between the first and second lines becomes equal to 1/24 of the cycle period of the pulse pattern.

The use of pulse patterns of such reduced fluctuation enables substantially continuous pulse width modulation of the density information, thus allowing obtain a reproduced image of a high quality.

FIG. 14 shows the relationship between the input image signal and the modulated pulse width or the image density. In FIG. 14, curve (a) FIG. 14A represents a characteristic when a sinusoidal pulse pattern is selected. Also curves (b) and (c) respectively correspond to the cases of triangular and inverted sinusoidal pulse patterns. Also a finer selection of gamma or contract is rendered possible by selecting variable non-linear amplifiers as the amplifiers 9a, 9b and 9c in FIG. 13.

As explained in the foregoing, the fourth embodiment is capable of selecting the pulse pattern for example according to the characteristics of an output device to be employed, and allows to effect a gamma correction without loss in the number of density levels and to achieve an image reproduction with a high quality.

In the fourth embodiment, the pulse pattern is generated at a cycle period of every three pixels, but said cycle period may be selected shorter or longer. Also the number of pixels to be added is not limited to three but can be suitably determined, in consideration of the response speed, resolution etc. of the apparatus.

It is also possible to select different cycle periods for the pulse pattern generation and for the addition of pixel data.

Also, in the foregoing description of the fourth embodiment, the pulse patterns are generated in the same manner in all lines, but it is similarly desirable to displace the generation of pulse patterns by a pixel between the neighboring lines. In this manner the centers of growth of pulses are displaced from line to line, so that the output pattern macroscopically appears as a diagonal screen pattern which is natural to the human eyes. Also such manner is desirable in consideration of the resolving power, since said centers of growth of pulses are more evenly distributed throughout the entire image. Furthermore, the selection of the pulse pattern need not be the same throughout the entire image but may be varied in a part of the image or from line to line.

FIG. 15 is a schematic perspective view of a scanning optical system of a laser beam printer (raster scanning print unit) in which the present invention is applicable. The optical system is provided with a semiconductor laser capable of emitting a laser beam modulated according to the aforementioned pulse width modulated signal. The light beam modulated by a semiconductor laser 34 is collimated by a collimating lens 33 and is deflected by a rotary polygon mirror 35 having plural reflecting faces. The deflected light beam is focused onto a photosensitive drum 32, thus an f-.theta. lens. In said scanning operation, the light beam is reflected, at the start position of a scanning line, by a mirror 37 and is guided to a beam detector 38, which generates a beam detection signal. As already known, said signal is utilized as the horizontal synchronization signal. As explained in the foregoing, the horizontal synchronization signal in the present embodiment is composed of said beam detection signal.

The beam detection signal is detected in each line of laser beam scanning and serves as a timing signal for sending the pulse-width modulated signal to the semiconductor laser.

The present invention is applicable to various image processing apparatus such as facsimile or laser beam printer.

The present invention is not limited to the foregoing embodiments but is subjected to various modifications and variations within the scope and spirit of the appended claims.