Circuitry for and Method of Generating Vertical Drive Pulse in Video Signal Receiver

1. An apparatus for generating a vertical drive pulse for defining a vertical scanning period of a display screen in response to a vertical synchronizing signal included in a video signal to be displayed, said apparatus receiving video signals in accordance with at least first and second broadcasting systems having different cycles of the vertical synchronizing signals, said apparatus comprising: gate means (59; 70) for passing said vertical synchronizing signal included in said video signal to be displayed; counter means (60; 360) for counting a clock signal and generating said vertical drive pulse and a plurality of timing signals (.phi.1 to .phi.8; .psi.1 to .psi.15) synchronous with said clock signal, said clock signal having a frequency integral times that of a horizontal synchronizing signal included in said video signal, said plurality of timing signals including at least a first timing signal (.phi.6; .psi.10) for defining a first gate period corresponding to said first broadcasting system, a second timing signal (.phi.7; .psi.11) for defining a second gate period corresponding to said second broadcasting system and a third timing signal (.phi.8; .psi.12) for defining a third gate period including said first and second gate periods; means (62, 63, 65; 362,363,365) for deciding whether said video signal to be displayed is that of said first broadcasting system or that of said second broadcasting system in response to said vertical synchronizing signal from said gate means; and gate period set means (66, 67; 366, 367) for selecting either said first or second timing signal in response to a decision result output from said decision means and supplying the selected timing signal to said gate means thereby to set a signal passage period in said gate means, said gate period set means further including means (66, 69; 423) for selecting said third timing signal and applying the same to said gate means when said vertical synchronizing signal is not received in a predetermined period set for respective said first and second broadcasting systems.

2. An apparatus in accordance with claim 1, wherein said first and second timing signals partially overlap with each other in a certain range.

3. An apparatus in accordance with claim 1, further including: input selection means (62; 362) for receiving an output signal from said gate means and generating a signal corresponding to said vertical synchronizing signal, and means (63) for generating a reset pulse in response to said output signal from said input selection means, said reset pulse resetting counting operation of said counter means for generation of said vertical drive pulse therefrom, said counter means generating timing signals (.phi.3, .phi.4; .psi.6, .psi.7) providing the basis of discrimination between said broadcasting systems, said decision means including: means (131, 132, 135, 136, 137, 139, 143, 142; 547, 548, 551, 552, 553, 555, 558, 559) for comparing phases of said reset pulse and said timing signals providing the basis of discrimination between said broadcasting systems.

4. An apparatus in accordance with claim 2, wherein said gate means receives all of externally supplied said vertical synchronizing signals.

5. An apparatus in accordance with claim 3, wherein said gate period set means includes synchronization detection means (66; 366) for deciding whether or not said reset pulse is generated within a gate period defined by said first or second timing signal in response to the output of said decision means and said reset pulse and for controlling timing signal selection operation in said gate period set means in accordance with the result of said decision.

6. An apparatus in accordance with claim 5, wherein said counter means generates fourth and fifth timing signals (.phi.1, .phi.2; .psi.3, .psi.1) for self-reset operation corresponding to said first and second broadcasting systems, and said input selection means includes: first signal passage means (71a) for passing the output of said gate means and said fourth timing signal, second signal passage means (71b) for passing the output of said gate means and said fifth timing signal, and means (70) for selectively passing the output of either said first or second signal passage means in response to outputs of said decision means and said synchronization detection means.

7. An apparatus in accordance with claim 5, wherein said gate period set means includes: first selection means (68) for selectively passing either said first or second timing signal in response to the output of said decision means, and second selection means (69) for selectively passing either the output of said first selection means or said third timing signal in response to the output of said synchronization detection means and supplying the selected output to said gate means.

8. An apparatus in accordance with claim 1, wherein said counter means generates a fourth timing signal (.psi.8) for defining a gate period shorter than that defined by said first timing signal and a fifth timing signal (.psi.9) for defining a gate period shorter than that defined by said second timing signal, said apparatus further comprising: phase detection means (418, 421, 422) for detecting whether or not said vertical synchronizing signal is supplied in a determined cycle specific to either one of said broadcasting system, said gate period set means including: means (423, 427, 428, 430) for selectively outputting one of said first to fifth timing signals in response to the outputs of said broadcasting system decision means, said synchronization detection means and said phase detection means, said selective output means selectively outputting either said fourth or fifth timing signal in response to the output of said broadcasting system decision means when said phase detection means indicates that said vertical synchronizing signal is supplied in said specific phase.

9. An apparatus in accordance with claim 8, wherein said counter means derives sixth sand seventh timing signals (.psi.1, .psi.2) respectively corresponding to said cycles of said vertical synchronizing signals specific to said broadcasting systems and eighth and ninth timing signals (.psi.5, .psi.3) for self-reset operation corresponding to respective said broadcasting systems, said apparatus further comprising: selection means (362) for selectively passing one of said sixth to ninth timing signals and the output of said gate means in response to the outputs of said broadcasting system decision means, said phase detection means and said synchronization detection means, and means (63) for generating a reset pulse in response to the output of said selection means, said reset pulse generated from said reset pulse generating means resetting counting operation of said counter means.

10. An apparatus in accordance with claim 9, wherein said selective passage means includes: first selective passage means (425a) for passing the output of said gate means and said eighth timing signal, second selective passage means (425b) for passing the output of said gate means and said ninth timing signal, third selective passage means (424) for selectively passing the output of either said first or second selective passage means in response to the outputs of said broadcasting system decision means and said synchronization detection means, fourth selective passage means (429) for selectively passing either said sixth or seventh timing signal in response to the output of said broadcasting system decision means, and fifth selective passage means for selectively passing the output of either said third or fourth selective passage means in response to the output of said phase detection means and supplying the selected output to said reset pulse generating means.

11. An apparatus in accordance with claim 8, wherein said gate signal selective passage means includes: first selective passage means (427) for passing either said fourth or fifth timing signal in response to the output of said broadcasting system decision means, second selective passage means (428) for selectively passing either said first or second timing signal in response to the output of said broadcasting system decision means, third selective passage means (430) for selectively passing the output of either said first or second selective passage means in response to the output of said phase detection means, and fourth selective passage means (423) for selectively passing either the output of said third selective passage means or said third timing signal in response to the output of said synchronization detection means and supplying the same to said gate means.

12. An apparatus in accordance with claim 8, further comprising: first signal selection means (418, 419) for selectively passing either said sixth or seventh timing signal in response to the output of said broadcasting system decision means, and second signal selection means (421) for selecting either a set of the output of said gate means and a 10-th timing signal from said counter means or a set of the output from said first signal selection means and said reset pulse in response to the output of said phase detection means and supplying the same to said phase detection means.

13. An apparatus in accordance with claim 12, further including means (419) for delaying said timing signal selected by said first signal selection means by a period for one cycle of said clock signal and supplying the delayed timing signal same to said second signal selection means.

14. An apparatus in accordance with claim 12, further comprising means (420) provided between an input of said second signal selection means and an output of said gate means for holding a supplied signal for a prescribed period.

15. An apparatus in accordance with claim 1, wherein said counter means counts a clock signal having a frequency of even number multiples of that of said vertical synchronization signal.

16. A vertical drive pulse generator comprising: a gate circuitry (59) for passing vertical synchronizing signals included in video signals of at least first and second broadcasting systems received from an input terminal (57) in response to a control signal, said vertical synchronizing signals of said first and second broadcasting systems being different in frequency from each other; a reset pulse generator (63) for generating a signal corresponding to said vertical synchronizing signal received from said gate circuitry as the reset pulse; a counter circuit (60) counting a clock signal having a frequency integral times that of a horizontal synchronizing signal included in said video signal for generating a first timing signal (.phi.6) entering an active state for a period corresponding to a period in which arrival of said vertical synchronizing signal of said first broadcasting system is expected while generating a second timing signal (.phi.7) entering an active state for a period corresponding to a period in which arrival of said vertical synchronizing signal of said second broadcasting system is expected on the basis of results of said counting, said counter circuitry generating said vertical drive pulse in response to said reset pulse; a broadcasting system decision circuitry 965) comparing the phases of said reset pulse and a third timing signal (.psi.4) providing timing forming the basis of a decision of said broadcasting system from said counter circuitry for deciding whether said arriving vertical synchronizing signal is that of said first broadcasting system or that of said second broadcasting system; a synchronization detection circuitry (66) for detecting whether or not said reset pulse is generated in a period defined by said first or second timing signal; and a gate signal selection circuitry (67) for selectively passing one of said first and second timing signals and a fourth timing signal (.psi.8) generated from said counter (60) in response to the outputs of said broadcasting system decision circuitry and said synchronization detection circuitry and applying the same to said gate circuitry for defining a gate period for making said gate circuitry capable of passing signals during supply of the selected timing signal, said first and second timing signals partially overlapping with each other in a gate period, said fourth timing signal defining a gate period including said gate periods defined by said first and second timing signals.

17. A circuit for generating a vertical drive pulse, comprising: a gate circuitry (59) for passing vertical synchronizing signals included in video signals in accordance with at least first and second broadcasting systems applied to an input terminal (57), said first and second broadcasting systems having different vertical synchronizing signal frequencies; an input selector (362) generating a signal corresponding to said vertical synchronizing signal passed through said gate circuitry; a reset pulse generator (63) for generating a reset pulse in response to said signal from said input selection circuit; a counter (360) counting a clock signal having a frequency integral times that of a horizontal synchronizing signal included in said video signal for generating a first timing signal (.psi.10) corresponding to a wide period in which arrival of said vertical synchronizing signal of said first broadcasting system is expected, a second timing signal (.psi.8) corresponding to a narrow period in which arrival of said vertical synchronizing signal is expected, a third timing signal (.psi.11) corresponding to a wide period in which arrival of said vertical synchronizing signal of said second broadcasting system is expected, a fourth timing signal (.psi.9) corresponding to a narrow period in which arrival of said vertical synchronizing signal is expected, a fifth timing signal (.psi.1) having a cycle corresponding to a vertical synchronizing signal cycle defined by said first broadcasting system and a sixth timing signal (.psi.2) having a cycle corresponding to a vertical synchronizing signal cycle defined by said second broadcasting system on the basis of values of said counting, counting operation of said counter circuit being reset in response to said reset pulse from said reset pulse generator, said counter circuit generating said vertical drive pulse upon reset; a broadcasting system decider (365) for deciding whether said reset pulse is generated within a period defined corresponding to said first broadcasting system or within a period defined corresponding to said second broadcasting system in response to said reset pulse; a first signal selector (94180) for selecting one of said fifth and sixth timing signals in response to a decision output from the broadcasting system decision circuit; a phase comparator (422) for comparing the phases of the output from said gate circuitry and an output signal from said first signal selector; a gate signal selector (367) for applying one of said first to fourth timing signals to said gate circuitry as said control signal in response to the output signal of said phase comparator and a decision output of said broadcasting system decider; and a synchronization detection circuit (366) for detecting, in response to said reset signal, that said counter circuitry is not reset in response to said vertical synchronizing signal from said gate circuitry but reset by a timing signal generated by said counter itself in a self-reset state, said gate signal selector applying a seventh timing signal (.psi.12) from said counter to said gate circuitry as said control signal in response to an output signal of said synchronization detector, said seventh timing signal defining a gate period corresponding to a wide period in which arrival of said vertical synchronizing signals of said first and second broadcasting systems is expected and including said gate periods defined by said first and third timing signals, said gate periods defined by said first and third timing signals partially overlapping with each other in a certain range.

18. A method of generating a vertical drive pulse being synchronous with a vertical synchronizing signal included in an externally supplied video signal in accordance with a vertical countdown system, said method comprising: a step of receiving and passing vertical synchronizing signals included in video signals in accordance with at least first and second broadcasting systems by and through a gate circuit (59); a step of generating a reset pulse corresponding to said passed vertical synchronizing signal; a step of counting a signal having a frequency integral times that of a horizontal synchronizing signal of said video signal for generating at least a first timing signal (.phi.6) corresponding to a period in which arrival of said vertical synchronizing signal of said first broadcasting system is expected, a second timing signal (.phi.7) corresponding to a period in which arrival of said vertical synchronizing signal of said second broadcasting system is expected and a third timing signal (.phi.8) corresponding to a period including said periods defines by said first and second timing signals, said counting operation being reset by said reset pulse, said vertical drive pulse being generated in response to said reset pulse; a step of deciding whether said vertical synchronizing signal arriving at said gate circuit is that of said first broadcasting system or that of said second broadcasting system in response to said reset pulse; and a synchronization detecting step of detecting whether or not said counting operation is reset by said vertical synchronizing signal from said gate circuit in response to said reset pulse signal, a step of supplying either said first or third timing signal to said gate circuit in response to the result of decision at said broadcasting system deciding step and the result of detection at said synchronization detecting step thereby to set a signal passage period of said gate circuit in three types of gate periods defined by said first timing signal, said second timing signal and said third timing signal, respectively, said gate periods defined by said first timing signal and said second timing signal partially overlapping with each other in a certain range.

19. A method of generating a vertical drive pulse being synchronous with a vertical synchronizing signal included in an externally supplied video signal, comprising: a step of receiving and passing vertical synchronizing signals included in video signals of at least first and second broadcasting signals by and through one gate circuit (59), said vertical synchronizing signals of said first and second broadcasting systems having different cycles; a step o generating a reset signal corresponding to said passed vertical synchronizing signal, said vertical drive pulse being generated in response to said reset signal; a step of counting a signal having a frequency integral times that a horizontal synchronizing signal included in said video signal for generating a first timing signal (.psi.10) defining a wide period in which arrival of said vertical synchronizing signal of said first broadcasting system is expected, a second timing signal (.psi.8) defining a narrow period in which arrival of said vertical synchronizing signal of said first broadcasting system is expected, a third timing signal (.psi.11) defining a wide period in which arrival of said vertical synchronizing signal of said second broadcasting system is expected, a fourth timing signal (104 9) defining a narrow period in which arrival of said vertical synchronizing signal of said second broadcasting system is expected, a fifth timing signal (.psi.1) having a cycle corresponding to that of said vertical synchronizing signal of said first broadcasting system, a sixth timing signal (.psi.2) having a cycle corresponding to that of said vertical synchronizing signal of said second broadcasting system and a seventh timing signal (.psi.12) defining a wide period in which arrival of said vertical synchronizing signal of either said first or second broadcasting system is expected, on the basis of the results of said counting; a step of deciding whether said vertical synchronizing signal arriving at said gate circuit is of said first broadcasting system or said second broadcasting system, on the basis of said reset signals; a step of selecting either said fifth timing signal or said sixth timing signal according to the result of said decision at said broadcasting system deciding step; a step of comparing the phases of a signal corresponding to said vertical synchronizing signal supplied from said gate circuit and said selected one of said fifth and sixth timing signals, a step of applying one of said first to fourth timing signals to said gate circuit as a control signal on the basis of the result of phase comparison at said phase comparing step and the result of said decision at said broadcasting system deciding step for making said gate circuit capable of signal passage for a period defined by said selected timing signal; a step of detecting, in response to said reset signal, whether or not said counting operation is reset in response to said vertical synchronizing signal from said gate circuit in a self-reset state; and a step of applying said seventh timing signal to said gate circuits as said control circuit in response to the result of said decision at said self-reset detecting step.