Analog-to-Digital Converter of Successive-Approximation Type

1. Field of the invention

The present invention relates to an analog-to-digital converter, and more particularly to an improvement in an analog-to-digital converter of the successive-approximation type having a string of resistors as a voltage divider.

2. Description of the Background

Prior analog-to-digital converters of the successive-approximation type successively compare an analog input voltage with a divided voltage from a string resistor circuit, and thereby convert the analog input voltage into a digital form. However, it is recognized that a high resolving power of the analog-to-digital converter causes a great increase in the number and resistance values of the resistors of the string resistor circuit, and further causes an increase in the length of a settling time necessary for analog-to-digital conversion. This results in a lowering of the speed of the analog-to-digital converter of this type. Furthermore, it is, in general, known that the string resistor circuit is fabricated by a plurality of diffusional or polysilicone resistors in the form of a semiconductor integrated circuit. This causes an increase in a resistance value of each of the resistors.

It is, therefore, a primary object of the present invention to provide an analog-to-digital converter of the successive-approximation type in which an additional string of low resistance elements are effectively utilized to enhance speed in the rise time of a divided voltage from a string of high resistance elements up to an optimum level, thereby to precisely ensure analog-to-digital conversion at a high resolving power and high speed. A method for doing so is also contemplated.

According to the present invention, the primary object is accomplished by providing an analog-to-digital converter of the successive-approximation type for converting an analog level into a digital value. The analog-to-digital converter comprises;

A source of reference voltage for generating a reference voltage;

successive-approximation logic circuit means for successively generating selection signals defined by a plurality of significant bits in the digital value;

a string of high resistance elements connected to the source of reference voltage to provide a series of voltage dividers for successively dividing the reference voltage into a series of divided voltages;

switch matrix circuit means coupled with the high resistance elements for generating the divided voltages therefrom when activated in response to the selection signals from the logic circuit means;

a comparison means for successively comparing the analog level with the divided voltages applied thereto from the switch matrix circuit means and for generating a series of comparison signals respectively indicative of the significant bits in the digital value; and

output means coupled with the comparison means for generating an output digital signal defined by the significant bits when applied with all the comparison signals from the comparison means, the output means being associated with the logic circuit means for causing it to generate the selection signals in response to the comparison signals from the comparison means;

wherein a string of low resistance elements are connected to the source of reference voltage to apply therethrough the reference voltage to at least one of the voltage dividers during a short period of time immediately after the one of the voltage dividers has been activated.

Other objects, features and advantages of the present invention will become more apparent from the following detailed description of preferred embodiments and certain modifications thereof when taken together with the accompanying drawings, in which:

FIG. 1 is a block diagram of an analog-to-digital converter in accordance with the present invention;

FIG. 2 is a detailed circuit diagram of the divided voltage generator shown in block form in FIG. 1;

FIG. 3 illustrates waveforms obtained at various points in the divided voltage generator;

FIG. 4 is a graph for explaining operation of the divided voltage generator;

FIG. 5 illustrates a modification of the divided voltage generator; and

FIG. 6 is a graph for explaining operation of the modified divided voltage generator.

FIG. 1 shows an eleven-bit string resistor analog-to-digital or A-D converter of the successive-approximation type in accordance with the present invention. The A-D converter comprises a sampling pulse generator 10 which repetitively produces a sampling pulse with a predetermined time period t.sub.1 when the A-D converter is at steady-state operation. In this case, the predetermined time period t.sub.1 indicates a settling time which corresponds to time necessary for a rise of a divided voltage from a divided voltage generator 100 up to an optimum level, as described below. A clock generator 20 produces a clock pulse with a predetermined frequency in sequence. A reference voltage source 30 generates a positive reference voltage V.sub.ref (for instance 5(V)). A sample hold circuit 40 takes an analog input voltage in response to a sampling pulse from sampling pulse generator 10 and holds the taken analog input voltages as a sample hold voltage. A preset counter 50 repetitively counts clock pulses from clock generator 20 up to a predetermined preset value, which corresponds to the time t.sub.1 and generates latch and selection signals Sa and Sb respectively with the predetermined time period t.sub. 1 (see FIG. 3). In this case, timing in generation of the latch signal Sa is determined slightly prior to that in generation of the selection signal Sb. The predetermined preset value corresponds to the settling time as mentioned above.

An enable pulse generator 60 is responsive to the start of operation of the A-D converter to produce an enable pulse Sc (see FIG. 3) with a predetermined pulse width corresponding to a predetermined short time period t.sub.0. Then, the pulse generator 60 starts to count the clock pulses from clock generator 20 and generates an enable pulse Sc repetitively upon the count reaching a predetermined number corresponding to the predetermined time period t.sub.1. The pulse generator 60 stops the generation of the enable pulse Sc after the counted number reaches a number corresponding to 5t.sub.1. Thereafter, the pulse generator 60 repeats generation and s top of an enable pulse Sc, as described above, at each time when the counted number of clock pulses reaches to a number corresponding to 11t.sub.1. In the embodiment, the above-mentioned short time period t.sub.0 indicates the time necessary for rise of a divided voltage from divided voltage generator 100 up to a level close to the optimum level as described above.

Upon initial receipt of a sampling pulse from sampling pulse generator 10, an output decoder 70 generates an eleven-bit decode 70 is responsive to a selection signal Sb from preset counter 50 and a sampling pulse from generator 10 to decode a latch comparison signal from a data latch output circuit 90, as described below, so as to generate an eleven-bit decode signal Sd indicative of the decoded contents. The decoding operation of output decoder 70 is performed repetitively in response to selection signals from preset counter 50 and sampling pulses from sampling pulse generator 10. In this case, the eleven decode signals Sd define respectively eleven bits of most to least significant bits in a value of a digital signal corresponding to an analog input voltage. In other words, a series of the decode signals Sd define divided voltages appearing from voltage divider 100 and corresponding to the most to least significant bits respectively. A comparator 80 compares a sample hold voltage from sample hold circuit 40 with a divided voltage from divided voltage generator 100 to generate a comparison signal. This comparing operation of comparator 80 is performed each time the sample hold circuit 40 is responsive to a sampling pulse from generator 10 to produce a sample hold voltage. This means that the comparing operation of comparator 80 is performed upon each lapse of the settling time. A data latch output circuit 90 is responsive to a latch signal Sa from preset counter 50 to latch a comparison signal from comparator 80 so as to generate the same signal as a latch comparison signal. When the number of the latch comparison signals from comparator 80 increases up to eleven, the data latch output circuit 90 produces an eleven-bit digital output signal corresponding to an analog input voltage.

As shown in FIGS. 1 and 2, the divided voltage generator 100 comprises a line decoder 110 and a row decoder 120 which are connected to output decoder 70. The line decoder 110 is responsive to a decode signal Sd from output decoder 70 to decode the five lowest bits of a value of the decode signal Sd so as to generate a 32-bit decode signal indicative of the decoded contents at its 32 output terminals. This means that on a basis of the decoded contents as described above, one of the 32 output terminals of line decoder 110 is activated and the remaining output terminals of line decoder 110 are maintained deactivated respectively. In this case, one output terminal of line decoder 110 shown at the uppermost position in FIG. 2 corresponds to the highest-order position, whereas one terminal of line decoder 110 shown at the lowermost position in FIG. 2 corresponds to the lowest-order position. The row decoder 120 is responsive to a decode signal Sd from output decoder 70 to decode the high-order six bits of the value of the decode signal Sd so as to generate a 64-bit decode signal indicative of the decoded contents at its 64 output terminals. This means that on the basis of the decoded contents as described above, one of the 64 output terminals of row decoder 120 is activated, and the remaining output terminals of row decoder 120 are maintained deactivated respectively. In this case, one output terminal of row decoder 120 shown at the extreme left position in FIG. 2 corresponds to the highest-order position, whereas one output terminal of row decoder 120 shown at the extreme right position corresponds to the lowest-order position.

A complementary semiconductor switch circuit 130 comprises 32 semiconductor switches S.sub.1 -S.sub.32. Each switch is formed of a pair of field effect transistors of the metal-oxide-semiconductor type or MOSFETs connected with each other in the form of the complementary type. Each of the semiconductor switches S.sub.1 -S.sub.32 has a pair of gates, both of which are connected to the output terminals of line decoder 110, drains which are connected to main string resistor circuit 140, and sources which are commonly connected together, and to comparator 80. The semiconductor switch S.sub.1, S.sub.2, . . ., or S.sub.32 is made conductive in response to activation of an associated output terminal of line decoder 110 corresponding to and connected to the pair of gates of the switch S.sub.m indicates one of switches S.sub.1 -S.sub.32. Upon being made conductive, the semiconductor switch S.sub.m, which receives at its pair of drains a divided voltage from a main string resistor circuit 140, applies the divided voltage through its pair of sources and to the investing input of comparator 80.

As shown in FIG. 2, the main string resistor circuit 140 comprises a string of 64.times.32 resistors R.sub.1 -R.sub.2048 which have a high resistance value respectively and are connected in series with each other. The resistors R.sub.1 -R.sub.2048 are divided into 64 groups, each of which is composed of 32 resistors R.sub.m and alternately arranged in parallel with each of 64 row lead wires X.sub.1 -X.sub.64. An array of 64.times.32 MOSFETs M.sub.1 -M.sub.2048 are arranged respectively to correspond with the resistors R.sub.1 -R.sub.2048. The MOSFETs M.sub.1 -M.sub.2048 each function as semiconductor switch elements respectively and are divided into 64 groups, each of which is composed of 32 MOSFETs M.sub.m -M.sub.m. In this case, the reference character M.sub.m indicates one of MOSFETs M.sub.1 -M.sub.2048. The MOSFETs M.sub.m -M.sub.m of each one group have their gates commonly connected to one of row lead wires X.sub. 1 -X.sub.64 sources of the MOSFETs M.sub.m -M.sub.m of each group are connected respectively to common terminals Z.sub.1 -Z.sub.2048 between respective pairs of resistors R.sub.m -R.sub.m connected in series to each other. The drains of one MOSFET from each group, in a same line position, are commonly connected to one lead wire connected to a drain of one of the semiconductor switches S.sub.m. Drains of MOSFETs M.sub.1 -M.sub.32 are connected to line lead wires Y.sub.1 -Y.sub.32 respectively, drains of MOSFETs M.sub.33 -M.sub.64 are connected to line lead wires Y.sub.32 -Y.sub.1 respectively, drains of MOSFETs M.sub.64 -M.sub.96 are connected to line lead wire Y.sub.1 -Y.sub.32 respectively, . . ., and drains of MOSFETs M.sub.2048 are connected to line lead wires Y.sub.1 -Y.sub.32. In this embodiment, the resistor R.sub.1, at one end of the series string of resistors, is connected to the reference voltage source 30, and the resistor R.sub.2048 at the other end of the series string of resistors, is grounded. The line lead wires Y.sub.1 -Y.sub.32 are connected respectively to the commonly connected sources of semiconductor switch elements S.sub.1 -S.sub.32 of semiconductor switch circuit 30, and the row lead wires X.sub.1 -X.sub.32 of semiconductor switch circuit 30, and the row lead wires X.sub.1 -X.sub.64 are connected respectively to the output terminals cf row decoder 120.

In operation of the main string resistor circuit 140, the resistors R.sub.1 -R.sub.2048 divide the reference voltage V.sub.ref from reference voltage source 30 during non-conduction of any of MOSFETs M.sub.1 -M.sub.2048 into divided voltages and generate the divided voltages respectively at the common terminals Z.sub.1 -Z.sub.2048. When one of the output terminals of the row decoder 120 is activated, the corresponding row lead wire X.sub.n makes conductive 32 MOSFETs M.sub.m -M.sub.m connected thereto. When one of the switch elements S.sub.1 -S.sub.32 of semiconductor switch circuit 130 is made conductive, the corresponding line lead wire Y.sub.m receives the divided voltage from the source of the conducting MOSFETs M.sub.m connected thereto and applies the same divided voltage through the conducting one of switch elements S.sub.1 -S.sub.32 to the inverting input of comparator 80. This means that the comparator 80 receives a divided voltage appearing at the common terminal Z.sub.m, which terminal is defined by the decoded results of line decoder 110 corresponding to the five low-order bits of a value of a decode signal from output decoder 70 and by the decoded result of row decoder 120 corresponding to the six high-order bits of the value of the decode signal from output decoder 70.

As shown in FIGS. 1 and 2, a subsidiary string resistor circuit 150 is connected to the reference voltage source 30, the enable pulse generator 60 and the main string resistor circuit 140. The subsidiary string resistor circuit 150 comprises a semiconductor switch element in the form of a MOSFETs Ms which is connected at its gate to the output terminal of enable pulse generator 60. A drain of MOSFET Ms is grounded and a source of MOSFET Ms is connected to the output terminal of reference voltage source 30 through a string of 32 resistors R.sub.s32 -R.sub.s1. Then, the MOSFET Ms is made conductive in response to a enable from pulse generator 60.

The resistors R.sub.s1 -R.sub.s32 have a low resistance value respectively and are connected in series to each other. The resistor string R.sub.s1 -R.sub.s32 receive the reference voltage V.sub.ref from reference voltage source 30 at one end at resistor R.sub.s1 in response to conduction of MOSFET Ms, and divides V.sub.ref so as to generate divided voltages respectively at common terminals Z.sub.s1, Z.sub.s2 . . ., -Z.sub.s31 between respective pairs of resistors R.sub.s1, R.sub.s2, R.sub.s3, . . ., R.sub.s31, R.sub.s32. 31 MOSFETs M.sub.s1 -M.sub.s31 are provided as a semiconductor switch elements respectively. Sources of MOSFETs M.sub.s1 -M.sub.s31 are connected respectively to the common terminals Z.sub.s1 -Z.sub.s31 of resistors R.sub.s1 -R.sub.s32, whereas drains of MOSFETs M.sub.s1 -M.sub.31 are connected respectively to the common terminals Z.sub.64, Z.sub.128, Z.sub.192 . . ., Z.sub.1984 of the main string resistor circuit 140. In this case, each suffix of the reference characters Z.sub.128, Z.sub.192 . . ., Z.sub.1984 corresponds to integer times as large as 64. Furthermore, a total of the resistance values of resistors R.sub.s1 -R.sub.32 is smaller than a total of the resistance values of resistors R.sub.1 -R.sub.2048.

As shown in FIG. 2, 31 logic circuits 150.sub.s1 -150.sub.s31 (FIG. 2 indicates only the logic circuits 150.sub.s1, 150.sub.s31) are provided in the subsidiary string resistor circuit 150. The logic circuit 150 comprises an inverter 151 which is connected at its input terminal to the row lead wire X.sub.2 of the main string resistor circuit 140 to generate an inverter signal with a high level or low level when the row decoder 120 is activated or deactivated at its output terminal connected to the row lead line X.sub.2. AND-gate 152 has one input terminal connected to the output terminal of the inverter 151 and the other to enable pulse generator 60 to generate a gate signal with a high level in response to the enable pulse from enable pulse generator 60 and the inverter signal with high level from inverter 151. The gate signal from AND-gate 152 disappears in response to at least one of the enable pulses from enable pulse generator 60 and the inverter with a low level from inverter 151.

The inverter 153 is responsive to the gate signal from AND-gate 152 to generate an inverted signal with a low level. The inverter signal from inverter 153 rises to a high level in response to the disappearance of the gate signal from AND-gate 152. This means that MOSFET M.sub.s1 is made conductive or non-conductive in response to the inverter signal with low level or high level from inverter 153. The logic circuits 150.sub.s2 -150.sub.s30 have respectively the same construction as that of the logic circuit 150.sub.s1. The logic circuit 150.sub.s2 is connected among a gate of MOSFET M.sub.s2, the row lead wire X.sub.4 and the output terminal of enable pulse generator 60, the logic circuit 150.sub.s3 is connected among a gate of MOSFET M.sub.s3, the row lead wire X.sub.6 and the output terminal of the enable pulse generator 60, . . ., and the logic circuit 150.sub.s30 is connected among a gate of MOSFET M.sub.s30, the row lead wire X.sub.60 and the output terminal of enable pulse generator 60. In this case, each suffix of the reference characters X.sub.4, X.sub.6, . . ., X.sub.30 corresponds to integer times as large as 2. Thus, the logic circuits 150.sub.s2 -150.sub.s30 have respectively the substantially same function as that of the logic circuit 150.sub.s1. This means that the logic circuits 150.sub.s2 -150.sub.s30 make respectively MOSFETs M.sub.s30 selectively conductive in relation to activation of the row lead wires X.sub.4 -X.sub.60 and an enable pulse from enable pulse generator 60.

The logic circuit 150.sub.s31 is an AND-gate which is connected at its output terminal to a gate of MOSFET M.sub.s31 and connected at its input terminals to the row lead wire X.sub.62 and the output terminal of enable pulse generator 60. Then, the logic circuit 150.sub.s31 generates a gate signal with high level in response to an enable pulse from enable pulse generator 60 when the row lead wire X.sub.62 is deactivated by row decoder 120. The gate signal from logic circuit 150.sub.s31 disappears when the row lead wire X.sub.62 is activated or when the enable pulse from enable pulse generator 60 disappears. This means that MOSFET M.sub.s31 is made selectively conductive in response to the gate signal from logic circuit 150.sub.s31. In the embodiment, the subsidiary string resistor circuit 150 is formed by a semiconductor integrated circuit together with the main string resistor circuit 140.

In operation of the A-D converter, the sampling pulse generator 10 sequentially produces a sampling pulse with the predetermined period of time t.sub.1, the clock generator 20 generates a clock pulse in sequence, the reference voltage source 30 produces a reference voltage V.sub.ref, the preset counter 50 generates latch and selections signals Sa and Sb with the time period t.sub.1 sequentially in accordance with the number of clock pulses from clock generator 20, and the enable pulse generator 60 generates an enable pulse Sc with the time period t in sequence in accordance with the number of clock pulses from clock generator 20.

When the sampling pulse first appears from the sampling pulse generator 10 during this state, the sample hold circuit 40 takes an analog input voltage to hold the taken analog input voltage as a sample hold voltage, and the output decoder 70 generates a first decode signal Sd in response to the first sampling pulse from sampling pulse generator 10. In this example, a value of the decode signal Sd corresponds to (10000000000), that is it defines a most significant bit or MSB (see FIGS. 3, 4) of the value of the digital output signal from data latch output circuit 90.

The line decoder 110 of divided voltage generator 100 is responsive to the decode signal Sd from output decoder 70 to decode the lowest order five bits (and which are 00000 at this time) of the decode signal Sd, and which produces a decode signal indicative of the decoded contents. Semiconductor switch circuit 130 is responsive to the decode signal from line decoder 110 to make conductive one of switch elements S.sub.1 -s.sub.32 which therefore maintains it at an activated condition which here is a high level the line lead wire Y.sub.m connected thereto. In this case, the reference character Y.sub.m indicates one of the line lead wires Y.sub.1 -Y.sub.32. The row decoder 120 decodes the six highest order bits (100000) of the decode signal Sd to generate a decode signal indicative of the decoded contents in response to which one of the row lead wires X.sub.1 -X.sub.64 is selected, to make conductive a group of MOSFETs M.sub.m -M.sub.m connected thereto. In this instance, assuming that decode signal Sd is 100 . . . 00, the above-mentioned selections of the one line lead wire Y.sub.m and the one row lead wire X.sub.n (or open of lead wires X.sub.1 -X.sub.64) provide a half (V.sub.ref /2) of the reference voltage as the divided voltage which is issued from the semiconductor which circuit 130 to comparator 80.

When an enable pulse Sc first appears from the enable pulse generator 60, MOSFET Ms as subsidiary string resistor circuit 150 is rendered conductive to ground the resistor R.sub.s32. After one of the row lead wires X.sub.1 -X.sub.64 is selected as previously described, the logic circuit of subsidiary resistor string circuit 150 connected to the selected one of the line lead wires X.sub.1 -X.sub.64 is responsive to the first enable pulse Sc from enable pulse generator 60 to make conductive the MOSFET connected thereto. In other words, such a conducting MOSFET of the subsidiary string resistor circuit 150 shorts the common terminals of the main and subsidiary string resistor circuits 140, 150 respectively connected thereto.

When the respective ones Y.sub.m, Y.sub.n of the line and row lead wires of main string resistor circuit 140 are selected and the respective one common terminals of the main and subsidiary string resistor circuits 140 and 10 are shorted, an electric current corresponding to the reference voltage V.sub.ref from reference voltage source 30 flows MOSFET Ms via the resistor R.sub.s1 -R.sub.s32 in accordance with the first and second time constants without flowing into the resistors of the main string resistor circuit 140. Since the resistance of resistors R.sub.s1 -R.sub.s32 are less than R.sub.1 -R.sub.2048, the first time constant, which is defined by the resistors R.sub.s1 -R.sub.s32 and a floating capacity of various electric elements arranged near the resistors R.sub.s1 -R.sub.s32, is determined to be considerably smaller than the second time constant defined by the resistor R.sub.1 -R.sub.2048 and a floating capacity of various electric elements arranged near the resistors R.sub.1 -R.sub.2048. Thus, an electric potential appearing at the common terminals which are shorted as described above rapidly rises, as shown by the reference character L.sub.1 in FIG. 4, owing to flowing of the electric current into the resistors R.sub.s1 -R.sub.s32.

When the first enable pulse from enable pulse generator 60 drops after its duration to a low level, MOSFET Ms of the subsidiary string resistor circuit 150 is made non-conductive, and simultaneously the common terminals, which are shorted as described above are disconnected from each other by non-conduction of the MOSFET connected therebetween. Then, the electric current corresponding to the reference voltage V.sub.ref from reference voltage generator 30 flows into the resistors of main string resistor circuit 140. As a result, the electric potential appearing at the common terminal which is disconnected as described above in the main string resistor circuit 140 rises slowly with the second time constant, as shown by the reference character L2 in FIG. 4, and precisely reaches a half (V.sub.ref /2) of the reference voltage in a stable manner. Therefore, the semiconductor switch circuit 130 applies to the comparator 80 a divided voltage from main string resistor circuit 140 which has been rapidly risen up to (V.sub.ref /2) in a stable manner. From this description, it will be understood that the subsidiary string resistor circuit 150 causes the divided voltage to rise rapidly from switch circuit 130 nearly up to (V.sub.ref /2) during the predetermined time period t.sub.0, and that thereafter the main string resistor circuit 140 rises slowly the divided voltage up to (V.sub.ref /2). Thus, even though resolving power of main string resistor circuit 140 is high, the divided voltage may be quickly raised to (V.sub.ref /2) in precision with the predetermined time period t.sub.1 of settling time. Furthermore, unnecessary electric power consumption may be restrained because of effective operation of the subsidiary string register circuit 150 only within the predetermined short period of time t.sub.0.

Upon receiving the divided voltage from switch circuit 130, as previously described, the comparator 80 compares the divided voltage with a sample hold voltage from sample hold circuit 40 to generate a comparison signal. The first latch and selection signals Sa and Sb are produced by preset counter 50, and the data latch output circuit 90 is responsive to the latch signal Sa to latch the comparison signal from comparator 80 so as to produce a latched comparison signal. The output decoder 70 is responsive to the first selection signal Sb to receive the latched comparison signal from data latch output circuit 90 to produce a second decode signal Sd. In this instance, a value of the second decode signal Sd corresponds to a bit next to the MSB (II000 . . . 00) in a value of the digital output signal from data latch output circuit 90. Thereafter, a divided voltage from switch circuit 130 rapidly rises by the main and subsidiary string resistor circuits 140, 150, as shown by the reference characters L.sub.3, L.sub.4 in FIG. 4, precisely up to reach (3 V.sub.ref /4). This effect operations of the comparator 80, data latch output circuit 90 and output decoder 70 in the same manner as that as previously described.

After this state, the same operation as that as previously described in repeated until the enable pulse generator 60 produces a fifth enable pulse Sc. When successive comparison regarding five bits from the MSB to the fifth bit in high order ends successive comparison regarding the sixth to eleventh bits is performed solely by the main string resistor circuit 140 without any use of the subsidiary string resistor circuit 150. When latched eleven comparison signals from comparator 80 in relation to the MSB to LSB, the data latch output circuit 90 generates a digital output signal defining the latched eleven comparison signals.

As understood from the above description, when one common terminal Z.sub.m of main string resistor circuit 140 corresponding to the MSB is selected, the selected common terminal Z.sub.m and the corresponding one common terminal of the subsidiary string resistor circuit 10 are shorted and maintained at the same electric potential. In this case, the reference character Z.sub.m indicates one of common terminals Z.sub.1 -Z.sub.2048. Then, an electric current corresponding to the reference voltage V.sub.ref from reference voltage source 30 flows rapidly into the resistors R.sub.s1 to R.sub.s32 and MOSFET Ms of subsidiary string resistor circuit 150 during the lapse of the predetermined short period of time to after selection of the one common terminal Z.sub.m. When the common terminals which are shorted as described above are disconnected from each other after the lapse of the short period of time t.sub.0, the electric current from reference voltage source 30 flows slowly into only the resistors of the main string resistor circuit 140. Thus, the divided voltage appearing at the common terminal Z.sub.m which is selected as mentioned above, is rapidly charged nearly up to (V.sub.ref /2) by the subsidiary string resistor circuit 140 within (t.sub.1 -t.sub.0). This means that a comparison signal to be latched by the data latch output circuit 90 after lapse of the predetermined time period t.sub.1 may be issued from the comparator 80 when a sample hold voltage from sample hold circuit 40 is compared with the divided voltage which rises precisely up to (V.sub.ref /2) in a short time and appears from switch circuit 130 in stability.

Regarding the second to fifth MSB's, each divided voltage from switch circuit 130 is charged by the string resistor circuits 150, 140, as previously described, up to each optimum level, precisely in stability with the predetermined period of time t.sub.1, in sequence. Thus, each comparison signal to be latched by the data latch output circuit 90 with each period of time t1 is issued by the comparator 80 at each time when each sample hold voltage from sample circuit 40 is successively compared with each divided voltage which is precisely stabilized in each optimum level in a short time. The six low order bits use the recognition that each divided voltage to be issued from switch circuit 130 hardly changes as shown in FIG. 4. For this reasons, each divided voltage may be effected using only by the main string resistor circuit 150. As a result, analog to digital conversion in the A-D converter of this type may be performed precisely in high speed regardless of how high the resolving power thereof, for instance, more than 11 bits.

For the actual practice of the present invention, it is preferable that for precisely effecting A-D conversion, the resistors of the main and subsidiary string resistor circuit 140, 150 are formed with the same resistive material as each other.

Although in the above embodiment the logic circuits 150.sub.s1 -150.sub.s31 of subsidiary string resistor circuit 150 are connected respectively to the row lead lines X.sub.2 -X.sub.62 and the enable pulse generator 60, they may be modified to be connected only to the enable pulse generator 60 such that they are activated only in response to the enable pulse from enable pulse generator 60 to make MOSFETs M.sub.s1 -M.sub.s32 conductive.

For the actual practice of the present invention, the subsidiary string resistor circuit 150 may be also adapted to used in the remaining bits except the five bits in high-order.

FIG. 5 illustrates a modification of the previous embodiment in which a divided voltage generator 100A is used in place of the divided voltage generator 100 as previously described. The divide voltage generator 100A comprises a respective pair of line decoders 110A, 110B, row decoders 120A, 120B and semiconductor switch circuits 130A, 130B. Each of the line decoders 110A, 110B has the same construction as that of line decoder 110 as previously described. Thus, each of line decoders 110A, 110B has the same function as that of the line decoder 110 in relation to a decode signal Sd from line decoder 110. Each of the row decoders 120A, 120B has the substantially same construction as that of the row decoder 120 as previously described. In this case, the decoder 120A has 32 output terminals which are connected respectively to the row lead wires X.sub.1 to X.sub.32, whereas the row decoder 120B has 32 output terminals which are connected respectively to the remaining row lead wires X.sub.33 to X.sub.64. Then, the row decoder 120A is responsive to a decode signal Sd from output decoder 70 to decode three high order bits of a value of the decode signal Sd so as to generate a 32-bit decode signal indicative of the decoded contents at its 32 output terminals. Meanwhile, the row decoder 120B is responsive to the decode signal Sd to decode three bits next to the above-mentioned three bits in the decode signal Sd so as to generate a 32-bit decode signal indicative of the decoded contents at its 32 output terminals. Each of the semiconductor switch circuits 130A, 130B has t he same construction as that of the semiconductor switch circuit 130. The semiconductor switch circuit 130A effects the same function as that of switch circuit 130 in relation to a decode signal from line decoder 110A, whereas the semiconductor switch circuit 130B effects the same function as that of switch circuit 130 in relation to a decode signal from line decoder 110B.

As shown in FIG. 5, a main string resistor circuit 140A is connected to the row decoder 120A, semiconductor switch circuit 130A and subsidiary string resistor circuit 150, whereas a main string resistor circuit 140B is connected to the row decoder 120B, semiconductor switch circuit 130B and subsidiary string resistor circuit 150. Each of the main string resistor circuits 140A, 140B has the substantially same construction as that of the main string resistor circuit 140. In this case, the main string resistor circuit 140A comprises a string of resistor R.sub.1 -R.sub.1024, MOSFETs M.sub.1 -M.sub.1024 and row lead wires X.sub.1 -X.sub.32, as previously described and comprises line lead wires Y.sub.1A -Y.sub.32A corresponding respectively to the line lead wires Y.sub.1 -Y.sub.32 as previously described. Meanwhile, the main string resistor circuit 140B comprises a string of resistors R.sub.1025 -R.sub.2048, MOSFETs M.sub.1025 -M.sub.2048 and row lead wires X.sub.33 -X.sub.64, as previously described and comprises line lead wires Y.sub.1B -Y.sub.32B corresponding respectively to the line lead wires Y.sub.1 -Y.sub.32, as previously described. The line lead wires Y.sub.1A -Y.sub.32A are connected respectively to drains of semiconductor switches S.sub.1 -S.sub.32 of switch circuit 130A, whereas the line lead wires Y.sub.1B -Y.sub.32B are connected respectively to drains of semiconductor switches S.sub.1 -S.sub.32 of switch circuit 130B. In addition, a string of the resistors R.sub.1 -R.sub.1024 are connected in series with a string of the resistor R.sub.1025 -R.sub.2048. Each length of the line lead wires Y.sub.1A -Y.sub.32 and Y.sub.1B -Y.sub.32B is equal to a half length of each line wire Y.sub.1 -Y.sub.32.

In the modification, each of the preset counter 50 and enable pulse generator 60 is arranged for starting count of the number of clock pulses from clock generator 20 upon lapse of a predetermined delay time t.sub.n after start of the A-D converter. The output decoder 70 is arranged to simultaneously generate a decode signal Sd defining MSB and a pair of decode signals Sd, Sd defining the bit next to MSB.

When the A-D converter is conditioned in its operation, the output decoder 70 is responsive to a first sampling pulse from sampling pulse generator 80 to produce first and second decode signals Sd--Sd which are simultaneously applied to the divided voltage generator 100A. At the same time, an electric current corresponding to the reference voltage V.sub.ref from reference voltage source 30 flows into the resistors R.sub.1 -R.sub.1024 and R.sub.1025 -R.sub.2048. Upon receiving the first decode signal Sd the line decoder 110A decodes five bits in low-order of a value of the first decode signal Sd to produce a decode signal. Then, the switch circuit 130A is responsive to the decode signal from line decoder 110A to make conductive one of switch elements S.sub.1 -S.sub.32 which activates one of the line lead wires Y.sub.1A -Y.sub.32A.

Upon receiving the first decode signal Sd, the row decoder 120A decodes three bits in high-order of a value of the first decode signal Sd to generate a decode signal. Then, one of the row lead wires X.sub.1 -X.sub.32 is activated in response to the decode signal from row decoder 120A to make conductive MOSFETs Mm connected thereto. Thus, a divided voltage appearing at a common terminal Zm corresponding to the activated line and row lead wires, as previously described, is applied by the corresponding MOSFET Mm through the conductive switch element Sm to the comparator 80.

Then one of the received second decode signals Sd from output decoder, the row decoder 120A decodes a value of one of the second decode signals Sd, as previously described, to generate a decode signal, in response to which another one of the row lead wires X.sub.1 -X.sub.32 is activated to make conductive MOSFETs Mm connected thereto. At this stage, any switch element of switch circuit 130A may not be conducted by the line decoder 110A related to one of the second decode signals Sd. When the remaining received second decode signal Sd from output decoder 70, the row decoder 120B decodes a value of the remaining second decode signal Sd, as previously described, to generate a decode signal in response to which another one of the row lead wires X.sub.33 -X.sub.64 is activated to make conductive MOSFETs Mm connected thereto. At this stage, any switch element of switch element 130B may not be conducted by the line decoder 110B related to the remaining second decode signal Sd. In this case, rising rate in each of divided voltages appearing respectively at common terminals of the resistors R.sub.1 -R.sub.2048 and line and row lead wires Y.sub.1A -Y.sub.32A, Y.sub.1B -Y.sub.32B and Y.sub.1 -Y.sub.32.

Upon lapse of the time duration t.sub.n after start of the A-D converter, each of the preset counter 50 and enable pulse generator 60 starts to count the number of clock pulses from clock generator 20. When latch and selection signals Sa and Sb appears from preset counter 50, the data latch output circuit 90 is responsive to the latch signal Sa to latch a comparison signal appearing from comparator 80 at this stage. In this instance, the divided voltage which is applied to the comparator 80 from switch circuit 130A fully rises, as shown by a solid line L.sub.1a in FIG. 6, with lapse of the time duration (t.sub.n +t.sub.1) after start of the A-D converter. This means that comparing operation of comparator 80 is performed precisely in stability on a basis of the divided voltage from switch circuit 130A.

When the sample hold voltage from sample hold circuit 40 is higher than the divided voltage from switch circuit 130A, the output decoder 70 produces again one of the second decode signals Sd in response to which the line decoder 110A activates another one of the line lead wires Y.sub.1A -Y.sub.32A. Then, a divided voltage or (3 V.sub.ref /4) appearing at the common terminal Zm defined by respective another ones of the row and line lead wires X.sub.1 -X.sub.32 and Y.sub.1A -Y.sub.32A, as previously described in applied by the conducted corresponding MOSFET Mm through the switch circuit 130A to comparator 80. In this case, the divided voltage, which is applied to comparator 80, as previously described, rapidly, rises up to (3 V.sub.ref /4), as shown by a solid line L.sub.2a in FIG. 6, because of the above-mentioned operation of the string resistor circuit 150 responsive to a first enable pulse issued from enable pulse generator 60. The rising rate of the divided voltage is further facilitated by decrease of the floating capacity in the string resistor circuit 140A. This means that comparing operation of comparator 80 is precisely performed on a basis of the divided voltage which has been conditioned rapidly in stability. When the sample and hold voltage from sample hold circuit 40 is lower than the divided voltage (3 V.sub.ref /4) from switch circuit 130A, the output decoder 70 produces again a second decode signal Sd in response to which the line decoder 110B activates another one of the line lead wires Y.sub.1B -Y.sub.32B by way of the switch circuit 130B. Then, a divided voltage or (V.sub.ref /4) appearing at the common terminal Z.sub.m, which is defined by respective another ones of the row lead wires X.sub.33 -X.sub.64 and Y.sub.1B Y.sub.32B, as previously described, is applied by the conducted corresponding MOSFET M.sub.m in the string resistor circuit 140B through the switch circuit 130B to the comparator 80. In this case, comparing operation of comparator 80 is precisely performed on a basis of the divided voltage which has been conditioned rapidly in stability in the same manner as that as previously described. In addition, A-D conversion regarding the remaining bits is performed in the substantially same manner as that as previously described.

From the above description, it should be understood that because initial selections of divided voltages corresponding to MSB and the bit next to MSB are simultaneously realized upon start of A-D conversion, the divided voltage corresponding to MSB may enoughly rise up to (V.sub.ref /2) within (t.sub.n +t.sub.1) and the divided voltage corresponding to the bit next to MSB may enoughly rise up to (3 V.sub.ref /4) or (V.sub.ref /4) within (t.sub.n +2t.sub.1). This means that A-D conversion regarding MSB and the bit next to MSB may be effected precisely in stability. Furthermore, this effect may be facilitated by the subsidiary string resistor circuit 140. In addition, the settling time may become short owing to decrease of floating capacity caused by decrease in length of the line lead wires and the number of MOSFETs in each of string resistor circuits 140A, 140B.

For the actual practices of the present invention, the number of division of the main string circuit may be changed in necessity.

Having now fully set forth the preferred embodiments and certain modifications of the concept underlying the present invention, various other embodiments as well as certain variations and modifications of the embodiment herein shown and described will obviously occur to those skilled in the art upon becoming familiar with said underlying concept. It is to be understood, therefore, that within the scope of the appended claims, the invention may be practiced otherwise than as specifically set forth herein.