Output Circuit of a Static Random Access Memory Circuit

This invention relates to an output circuit of a static random access memory circuit (hereinafter called a SRAM).

FIG. 4 is an output circuit of a conventional SRAM, and FIG. 5 is a timing chart of the output circuit in FIG. 4.

In FIG. 4, multiple memory cells arranged in a matrix in a memory cell block (not shown) each contain "1" or "0" data, and when one memory cell is selected by an address signal AD, the "1" or "0" data stored in that memory cell is read out. If the data being read out is a "1", the internal data S in FIG. 4 becomes a high level (an H level) and the internal data S becomes a low level (an L level). On the contrary, if the data being read out is a "0", the internal data S in FIG. 4 becomes an L level and the internal data S becomes an H level. An output control circuit 2 controls the gates of MOS FETs Q.sub.1 and Q.sub.2 of a data output circuit 1 according to the potential levels of the internal data S and S, and establishes the output Do at an H level or an L level. For example, when the internal data S is an H level and the internal data S is an L level (in other words, when the data stored in the selected memory cell is a "1"), both MOF FET gates Q.sub.1 and Q.sub.2 of the data output circuit 1 are set at an L level, and only the P-channel MOS FET Q.sub.1 is turned on, and the output Do is pulled up to an H level. On the contrary, when the internal data S is an L level and the internal data S is an H level (in other words, when the data stored in the selected memory cell is a "0"), both MOS FET gates Q.sub.1 and Q.sub.2 of the data output circuit 1 are set to an H level, and only the N-channel MOS FET Q.sub.2 is turned on, and the output Do is pulled down to an L level.

Therefore, when the address signal AD changes, the internal data S and S change from an H level to an L level or vice versa, and according to this change, the output control circuit 2 controls the gate potentials of MOS FETs Q.sub.1 and Q.sub.2 of the data output circuit 1, and the final output Do changes from an H level to an L level or vice versa. FIG. 5 shows such voltage changes.

In the conventional composition, however, the output Do changes largely from an H level (.perspectiveto.Vcc) to an L level (.perspectiveto.0 V), or from an L level (1/30 V) to an H level (.perspectiveto.Vcc). Generally, since the load connected to the output terminal of the SRAM has an extremely high capacity, if the potential change of the output Do is large, the transition time until the output Do settles at a stable value of an H level or an L level is long, and the reading operation of the SRAM cannot be increased in speed. Besides, since the output Do voltage changes by a large amount, a large momentary current flows through MOS FETs Q.sub.1 and Q.sub.2 of the output circuit 1.

It is hence a primary object of this invention to present an output circuit of a SRAM capable of operating the SRAM at high speed by shortening the transition time of the output potential.

It is a second object of this invention to present an output circuit of a SRAM having a reduced momentary current flowing through the MOS FET of the data output circuit.

Summing up, this invention is intended to set the output voltage of the data output circuit at an intermediate voltage by detecting the transition of an address signal before the data in the memory cell is read out, and then pulling up the output voltage of the data output circuit from the intermediate voltage to an H level or then pulling the output voltage down from the intermediate voltage to an L level, depending on the data being read out from the memory cell.

In this way, the output voltage always changes from the intermediate voltage to an H level or an L level, and the transition time of the output voltage may be shortened, and therefore, the reading speed of the SRAM may be increased. Furthermore, the momentary current flowing through the data output circuit can be reduced.

FIG. 1 is a block diagram of an output circuit of a SRAM in accordance with a more practical embodiment of the present invention;

FIG. 2 is a timing chart of essential parts of FIG. 1;

FIG. 3 is a block diagram of an output circuit system of SRAM in a more practical embodiment of the invention;

FIG. 4 is a block diagram of an output circuit of a conventional SRAM; and

FIG. 5 is a timing chart of essential parts of FIG. 4.

Referring now to FIGS. 1 and 2, an embodiment of the invention is described below. In FIG. 1, a memory cell block 4 contains, among others, a memory cell matrix, an address decoder for selecting a memory cell in the memory cell matrix and a data reading circuit for reading out the data stored in each memory cell. In a fashion similar to that of the prior art, "1" or "0" data is read out from the memory cell (not shown) when selected by address signal AD. Depending on whether this data read out from the memory cell is a "1" or a "0", the internal data S and S become an H level or an L level. The data S and S are supplied to the output control circuit 2, and also to an intermediate potential or voltage setting circuit 3. On the other hand, MOS FETs Q.sub.5 and Q.sub.6 are connected between data wires of internal data S and S and a reference potential, and the pulse generated by an address transition detector 5 for detecting transitions of the address signal AD is supplied to the gates of the MOS FETs Q.sub.5 and Q.sub.6. Therefore, the internal data S and S both first change to an L level every time the address signal AD is changed, and thereafter they change to the level depending on the data in the selected memory cell. The output of the intermediate potential setting circuit 3 is supplied to the gates of the MOS FETs Q.sub.1 and Q.sub.2 of the data output circuit 1, together with the output of the output control circuit 2. The output Do of the data output circuit 1 is supplied to the intermediate potential setting circuit 3 in order to control the action of the intermediate potential setting circuit 3.

The operation of thus composed output circuit of a SRAM in accordance with this embodiment is explained below.

When a certain memory cell is selected by an address signal AD, the internal data S and S are determined depending on the data stored in that memory cell. Accordingly, depending on the internal data S and S, the output control circuit 2 controls the on/off switching of MOS FETs Q.sub.1 and Q.sub.2 in the data output circuit 1, so that the output Do is established at an L level or an H level. At this time, the intermediate potential setting circuit 3 is in an inactive state.

Next, when the address signal AD is changed in order to select other memory cell, the address transition detector 5 instantly detects the transition of the address signal AD, and generates a detection pulse P. The detection pulse P is supplied to the gates of MOS FETs Q.sub.5 and Q.sub.6 to turn on both Q.sub.5 and Q.sub.6, thereby changing both internal data S and S to an L level. In this way, the internal data S and S change to an L level for a specific period before the internal data S and S change to the level corresponding to the data in the memory cell, so that the transition of the address signal AD may be detected. Thus, when the internal data S and S both become an L level, the intermediate potential setting circuit 3 is set in an active state. When the intermediate potential setting circuit 3 is placed in its active state, the output Do is an, if it is H level at that moment, lowered to to an intermediate voltage point. Or, if the output Do is an L level at that moment, the output Do is pulled up to the intermediate voltage point.

Afterwards, the data of the memory cell selected by the address signal AD is read out, and the internal data S and S change to an H level or an L level, when the intermediate potential setting circuit 3 is again placed in its inactive state, and thereafter the output control circuit 2 controls the on/off switching of MOS FETs Q.sub.1 and Q.sub.2 of the data output circuit 1 depending on the state of the internal data S and S, and the output Do is changed from the intermediate voltage to an H level or from the intermediate voltage to an L level. FIG. 2 shows the changes of the address signal AD, data S, and output Do level at this time.

Thus, according to the embodiment in FIG. 1, after transition of the address signal AD, and before the levels of the internal data S and S are changed to the level corresponding to the data read out from the memory cell, the voltage level of the output Do is detected by the intermediate potential setting circuit 3 so that the output Do may be preliminarily set to an intermediate voltage. Therefore, afterwards, when the internal data S and S are changed to the level corresponding to the data read out from the memory cell, the output Do may be always changed from the intermediate voltage level to an H level or from the intermediate voltage level to an L level. Accordingly, the transition time of the output Do may be shortened, and high speed reading of the SRAM may be realized. It is also possible to reduce the momentary current flowing through MOS FETs Q.sub.1 and Q.sub.2 of the data output circuit 1.

FIG. 3 shows a more practical embodiment of this invention.

In FIG. 3, an output control circuit 2 is composed of inverters 21, 22, and 23. An intermediate potential setting circuit 3 is composed of an inverter 31, NOR gate 32, NAND gate 33, N-channel MOS FET Q.sub.3, and P-channel MOS FET Q.sub.4. The output Do of a data output circuit 1 is supplied to one of the input terminals of NOR gate 32, and NAND gate 33, respectively. The internal data S is supplied to the gate of the MOS FET Q.sub.1 of the data output circuit 1 by way of the inverter 21 of the output control circuit 2, and is also supplied into the other input terminal of NAND gate 33 by way of the inverter 31 of the intermediate potential setting circuit 3. On the other hand, the internal data S is supplied to the gate of MOS FET Q.sub.2 of the data output circuit 1 by way of the inverters 22 and 23 of the output control circuit 2, and is also supplied to the other input terminal of NOR gate 32 of the intermediate potential setting circuit 3. The outputs of the NOR gate 32 and NAND gate 33 are respectively supplied to the gates of MOS FETs Q.sub.3 and Q.sub.4. The source and drain of MOS FET Q.sub.3 are respectively connected to the output terminal of the inverter 21 and a reference potential point, while the source and drain of MOS FET Q.sub.4 are respectively connected to the supply voltage potential Vcc and the output terminal of the inverter 23.

The operation of the circuit shown in FIG. 3 is as follows.

When a certain memory cell is selected and a data "1" stored in that memory cell is read out, the internal data S is at an H level and the internal data S is at an L level, and the output Do is at an H level. At this time, the output of NOR gate 32 becomes an L level, and the MOS FET Q.sub.3 is turned OFF. By contrast, the output of NAND gate 33 becomes an H level, and the MOS FET Q.sub.4 is turned OFF. That is, the intermediate potential setting circuit 3 is in an inactive state, and the output Do is fixed at an H level. When the a data "0" stored in the memory cell is read out, the intermediate potential setting circuit 3 is in its inactive state in the same fashion as stated above, and the output Do is fixed at an L level.

Next, by the transition of the address signal AD, when another memory cell is accessed, the change of address signal AD is detected, and a detection pulse P is generated, and the MOS FETs Q.sub.5 and Q.sub.6 are both turned on, and the internal data S and S potentials are lowered to and L level. As a result, if the previous output Do is at an H level, the two inputs of the NAND gate 33 both become an H, and the output of the NAND gate 33 becomes an L level, and the MOS FET Q.sub.4 is placed in its active state. On the other hand, the two inputs of the NOR gate 32 are respectively at an H level an L level, and the output of the NOR gate 32 is at an L level, and the MOS FET Q.sub.3 remains in its OFF state. Therefore, the gate of MOS FET Q.sub.2 of the data output circuit 1 becomes an H level, and the MOS FET Q.sub.2 is placed in its active state, and the output Do is pulled down to the intermediate voltage between an H level and the reference potential (e.g.-GND). On the contrary, when the output Do before the generation of the detection pulse P is an L level, the MOS FET Q.sub.1 of the data output circuit 1 is placed in its active state, and the MOS FET Q.sub.2 is turned off, and the output Do is pulled up to the intermediate voltage between an L level and the supply potential (e.g.-Vcc).

In consequence, when "1" or "0" data is read out from the selected memory cell, the internal data, S and S are changed to an H level or an L level, and correspondingly the MOS FETs Q.sub.1 and Q.sub.2 of the data output circuit 1 are controlled in on/off switching, and the output Do is pulled up (or down) from the intermediate potential to an H level (or an L level).

According to the embodiment in FIG. 3, in this way, the transition of address signal AD is detected, and the potential of the output Do is preliminarily set at intermediate voltage, and then, when data is to be output at Do from the memory cell, the voltage is changed from the intermediate voltage to an H level or an L level, and therefore the transition time of the output Do is shortened, and high-speed reading is realized, and the momentary current flowing through the data output circuit may be decreased.

Incidentally, in the embodiments shown in FIG. 1 and FIG. 3, MOS FETs Q.sub.5 and Q.sub.6 are provided in order to detect the transition of the address signal, and the MOS FETs Q.sub.5 and Q.sub.6 are turned on by the address transition detection pulse P, and the internal data S and S are first changed to an L level, but this invention is not limited to this method alone. For example, it may be possible to connect the MOS FETs Q.sub.5 and Q.sub.6 between the wires of internal data S and S and the voltage supply (Vcc), and change the internal data S and S to an H level for a specific period. In this case, too, by only rearranging the logic gates of the intermediate potential setting circuit 3, the same operation as in the embodiment in FIG. 3 may be realized. Besides, instead of changing the internal data S and S to an L level or an H level for a specific period by the transition of address signal, a signal to express such a transition of the address signal (for example, the address transition detection pulse in FIG. 1 or FIG. 3) may be directly supplied to the intermediate potential setting circuit. In this case, again, the same operation as in the embodiment in FIG. 3 may be realized by only rearranging the logic gates.