Semiconductor Device With Multi-Level Wiring in a Gate Array

The present invention relates to a semiconductor device, especially to a multiple-layer wiring structure or a logic gate cell structure which enables an automatic layout in very large scale integrated circuits (hereinafter referred to as "VLSI"), and further enables a high-speed operation and a high integration.

A hand-crafted layout design of a logic LSI can yield a high degree of circuit integration but the integration comes at the expense of time and a high cost. Therefore, the layout design by a hand-craft has become a non-realistic technique except for the design of those parts of general-purpose LSIs which are to be mass-produced. An automatic layout design is more practical. In this automatic layout design, placement of elements and wiring are carried out automatically using standard cells which are designed with their operations verified beforehand. It is usually described as "a standard cell system" or "a gate array system".

However, in this automatic design technique, it is quite difficult for a placement wiring program to attain the high density wiring that can be done by a layout designer. Conventionally in the automatic layout design a double layer wiring system is used whereby a vertical and a horizontal wiring are provided from different wiring layers respectively. Furthermore, in automatic layout designs of silicon gate MOS devices which have high integration and low power consumption, two kinds of wiring systems are used.

The first kind of wiring system is that which uses a double-layer wiring structure which consists of a gate metal layer composed of polysilicon (polycrystalline silicon) or the like constituting the gates of MOS transistors as a first (for example, vertical) wiring layer, and a low-resistance metal wiring layer composed of aluminum or the like for connection to the sources or drains of MOS transistors as a second (for example, horizontal) wiring layer.

In FIG. 1 shows this first kind of wiring structure. The numeral 1 indicates a cell bench where standard cells which will be described later are placed. The numeral 2 indicates a wiring region designated as the horizontal wiring channel. The numeral 3 indicates a standard cell which is obtained by implementing a logic gate, for example, an inverter, a 2-input NOR gate, or 3-input NAND gate, in a cell according to a layout design. The numeral 4 indicates a vertical wiring composed of a gate metal layer. The numeral 5 indicates a horizontal wiring composed of an aluminum wiring layer. The numeral 6 and 7 indicate a power supply wiring and a ground wiring respectively. The numeral 8 indicates an aluminum wiring used as a lead for a drain electrode. The numeral 9 indicates a contact for connecting between the diffused region and the aluminum wiring layer or between the gate metal layer and the aluminum wiring layer. The numeral 10 and 11 indicate a P-type impurity region and an N-type impurity region respectively. The numeral 40 indicates a P-well region.

In this type of wiring structure, wirings for input/output terminals of cells are wired by using vertical wirings 4 and horizontal wirings 5 in accordance with information for connections between the cells. The power supply wiring 6 and ground wiring 7 in the standard cell run in the horizontal direction, being composed of an aluminum wiring respectively. An output terminal of a logic gate is let out by a vertical wiring 4 of a gate metal layer through an aluminum wiring 8 which connects the drains of a P-channel transistor and a N-channel transistor. The drain of the P-channel transistor consists of the region 10 which is constructed by diffusing P-type impurities into the N-type semiconductor substrate. The drain of N-channel transistor consists of the N-type impurity region 11 which is produced by diffusing N-type impurities into the P-well region 40 which is produced by diffusing P-type impurities into the semiconductor substrate. A logic LSI is layed out by using standard cells and wiring regions of such structure. This conventional structure has as its feature the capability of realizing the LSI by the conventional wiring process of a polysilicon gate and single-layer aluminum.

The second kind of wiring system is that which uses a double layer aluminum wiring structure, mainly aiming to improve the operation speed of the first kind of wiring system. The structure is shown in FIG. 2.

In FIG. 2, it is a fundamental arrangement that horizontal wirings are constructed of a first low-resistance metal wiring layer 5 (a first aluminum wiring layer) and that vertical wirings are constructed of a second low-resistance metal wiring layer 13 (a second aluminum wiring layer), whereby wiring is carried out between the standard cells. In addition, a gate metal wiring layer 4 which has high-resistance relative to the first and second low-resistance wiring layer 5, 13 is used only for wiring in the standard cell, not being used in the wirings region between the cells. The numeral 12 indicates a through hole for connecting between the first and the second aluminum wiring.

One advantage of this system resides in that wiring is carried out by using low-resistance wiring layers, which results in only a small resistance due to the wirings, which allows the device to obtain a higher gate operation speed. Another advantage of this system is the ability to easily calculate the delay time of the gate which should be used in logical verifications and timing verifications of LSIs from only capacities, for example, capacitances of the wirings input capacitances of the logic gate which is to be driven, and so on.

However, it is non-advantageous to use a gate metal layer which has generally a high-resistance per unit length as a vertical wiring layer in view of operation speed of a logic LSI in the conventional semiconductor device, especially in the double-layer wiring structure described above as a first kind of wiring system. That is, in this double-layer wiring structure, it is fundamentally necessary to construct feed through wirings (not shown in FIG. 1) which are vertical wirings provided between the cells by gate metal wiring layers resulting in the increased length of the gate metal wiring and hence an increase in wiring resistance. The length of the gate metal wiring becomes also considerably lengthy when there is provided a vertical wiring region in order to increase the wiring density. In this case, a large resistance arises in the wiring, and the operation speed of the logic gate decreases significantly. Accordingly, it is necessary to add an element in the placement/wiring program that replace the gate metal wiring by an aluminum wiring in those regions where a long gate metal wiring does not cross with an aluminum wiring in order to avoid a slow down of the operation speed. Without this element it is unable to use the program in a design of a high speed LSI. Furthermore, it becomes difficult to predict or calculate the delay time of a logic gate before the production thereof because of its resistance.

Additionally, in the double-layer wiring structure which is described above as a second kind of wiring system, there is a disadvantage in that the gate metal wiring is only used for providing gate electrodes and not used for providing wirings. Furthermore, it is necessary to provide excess regions composed of the first metal (horizontal) wiring layer in order to connect the gate metal with the second metal (vertical) wiring layer, resulting in less than optional operation speed and a lower degree of integration of LSIs. This is because it is impossible to make the second metal wiring layer in contact with the gate metal directly because of the thickness of the insulating layer that is inserted between the layers in the manufacturing process for MOS devices or the like. Providing excess regions composed of the first metal wiring layer also prevents providing a feed through above the excess regions using the second metal wiring layer.

The present invention is directed to solve the problems pointed out above, and has as its object a semiconductor device in which a high wiring density is achieved in logical VLSI without reduction in operation speed.

Other objects and advantages of the present invention will become apparent from the detailed description given hereinafter; it should be understood, however, that the detailed description and specific embodiment are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.

According to the present invention, the semiconductor device is of a multiple-layer wiring structure where each of the vertical wirings is provided by a vertical wiring layer, each of the horizontal wirings is provided by a horizontal wiring layer, either of the vertical or the horizontal wiring layer can be provided in plurality, one and another of the plurality of wiring layers constitute wiring including input and output terminals of logic gates respectively, and wiring is carried out along each wiring grid which is prepared for each of the plurality of wiring layers so that the lines of different grids are alternately arranged.

FIG. 1 is a pattern diagram of a conventional semiconductor device;

FIG. 2 is a pattern diagram of another conventional semiconductor device;

FIG. 3 is a pattern diagram of an embodiment of the present invention;

FIG. 4 is a detailed pattern diagram showing such a triple-layer wiring structure as shown in FIG. 3; and

FIG. 5 is a circuit diagram of an equivalent circuit of the wiring structure of FIG. 4.

FIG. 3 shows an embodiment of the present invention. The numeral 14 indicates a standard cell bench where standard cells which will be described later are arranged in the horizontal direction. The numeral 15 indicates a wiring region called the horizontal channel. The numeral 16 indicates a standard cell implementing a 2-input CMOS NOR gate designed to be produced by a CMOS process using a polysilicon gate, and a double-layer aluminum wiring system. The numeral 17 indicates vertical wirings comprising polysilicon. The vertical wirings 17, composed of a single-layer structure, where N-type impurities are diffused, constitute the gates of a P-channel transistor and an N-channel transistor which will be described later, and they also constitute input terminals of a 2-input NOR gate. The numeral 18 indicates a horizontal wiring produced from a first aluminum wiring layer. The numerals 19 and 20 indicate a power supply (V.sub.DD) wiring and a ground wiring respectively running horizontally, produced from the first aluminum wiring layer. The numeral 21 indicates a wiring for a lead of drain electrode comprising the first aluminum wiring layer. The numeral 22 indicates contacts for connecting between the diffused region and the first aluminum wiring layer, or between the polysilicon layer and the first aluminum wiring layer. The numeral 23 indicates a P-type impurity diffused region constituting the source or drain of a P-channel transistor. The numeral 24 indicates an N-type impurity diffused region which region is produced by diffusing N-type impurities into the P-well region constituting the source and drain of an N-channel transistor. The numeral 25 indicates a through hole for connecting between the first aluminum wiring and the second aluminum wiring. The numeral 26 indicates a wiring that is the output terminal of a 2-input NOR gate comprising, that is, produced from a second aluminum wiring layer. Thus, the drains of both transistors 23 and 24 are connected to each other by the first aluminum wiring 21, and the first aluminum wiring 21 is connected to the second aluminum wiring 26 via a through hole 25.

In the standard cell 16 implementing a NOR gate which has only one output, it is possible to provide two pieces of vertical wirings which run through the cell (they are called feed through wirings) above the two gate metal wirings 17 constituting input terminals of the cell. This means that a broad feed through region can be provided over the cells. The input and output terminals are designed to be located on the lines of the wiring grids (corresponding to 27 and 28 shown in FIG. 4) which are established for the gate metal wiring and the second aluminum wiring layer respectively. The horizontal length of the standard cell 16 is designed to be a multiple (even number multiple) of the interval of each of the vertical wiring grids, and the left and right end of the cell are located on the lines of the grid for an input terminal.

In summary, the first feature of the wiring structure and the cell structure of the present embodiment resides in the adaption of the triple-layer wiring structure where the gate metal wiring layer 17 comprising a polysilicon wiring layer, and the second low-resistance metal wiring layer 26 comprising a second aluminum wiring layer are constituted as vertical wirings respectively, and the first low-resistance metal wiring layer 18 is constituted as a horizontal wiring, thereby resulting in the efficient use of the gate metal wiring layer for wirings between the standard cells within one channel.

The second feature of the present embodiment resides in that the gate metal wiring which, produced from a first vertical wiring, constitutes an input terminal of a logic gate and the second aluminum wiring which, produced from a second vertical wiring layer, constitutes an output terminal of a logic gate or a feed through are arranged alternately, each along the lines of the vertical wiring grids. In other words, the lines of different grids are alternately arranged, thereby resulting in the high wiring density as a whole.

In the embodiment shown in FIG. 3, the horizontal wirings 18 are arranged along the lines of the horizontal wiring grid which is established for the horizontal wiring layer and has the same interval as that of the wirings 18. However, it is, of course, not only possible but desirable not to provide the horizontal wiring grid in view of increasing the wiring density in the wiring region 15, it being called as a y-direction grid free system. In such a y-direction grid free system, a horizontal wiring is arranged so as to have the permissible minimum distance between itself and an adjacent horizontal wiring which is a minimum distance allowed to be laid between two horizontal wirings, or is arranged so as to have the permissible minimum distance between itself and an adjacent contact for connecting between the horizontal wiring and the first or second vertical wiring, thereby resulting in the high wiring density.

In FIG. 4 which shows the detailed pattern of such a triple-wiring structure as shown in FIG. 3, the numerals 27 and 28 indicate a wiring grid for a first vertical wiring layer (a gate metal wiring layer) and a wiring grid for a second vertical wiring layer (a second aluminum wiring layer) respectively, the numeral 29 indicates a wiring region designated a vertical wiring channel, and the numeral 30 represented by diagonal lines indicates a feed through inhibiting region. The numeral 31 indicates a contact for connecting between the gate metal wiring and the first aluminum wiring, and the numeral 32 indicates a contact for connecting between the first aluminum wiring and the second aluminum wiring.

In this type of triple-layer wiring structure, the triple-layer wiring is realized by first vertical wirings and second vertical wirings located along the first vertical wiring grid 27 and the second vertical wiring grid 28 respectively, and further horizontal wirings (first aluminum wirings). The wirings in the wiring region 29 are constructed by using a double-layer wiring structure which consists of the second vertical wirings and the horizontal wirings, not using a high-resistance wiring layer (a gate metal wiring layer), whereby a high density wiring is realized as a whole while keeping a clearance between the wirings of each wiring layer as the minimum design rule. It is necessary to provide two kinds of contacts for connecting between the wiring layers, that is, the contacts 31 for connecting between the gate metal wirings and the first aluminum wirings and the contacts 32 for connecting between the first aluminum wirings and the second aluminum wirings. The output signal of the logic gate which is led out by the second aluminum wiring (second vertical wiring) 26 is wired on the chip using the horizontal wiring 18 and the second vertical wiring 26 (second vertical wiring), and the portion thereof which leads to the input of a logic gate is wired by only using the first vertical wiring which are located on the lines of the vertical wiring grid except for the portion thereof represented by diagonal lines in the standard cell 16 in FIG. 4, can be used for feed, thereby enabling a high density wiring. In the wiring rule of the present embodiment, it is a feature that the second vertical wirings can be used to provide a feed through wirings over the cell.

FIG. 5 shows the equivalent circuit of the wiring structure shown in FIG. 4. In FIG. 5, the numerals 33 and 34 indicate inverters, the numerals 35a to 35c indicate resistances caused by the gate metal wiring layers, the numerals 36a to 36c indicate capacities added to the input terminals of the gates, the numeral 37 indicates a NAND gate, the numeral 38 indicates a NOR gate, and the numeral 39 indicates a wiring constituted by the first aluminum wiring and the second aluminum wiring.

In this equivalent circuit, any resistance is not inserted into the output terminals of logic gates represented by the inverter 33, and the resistance 35 is inserted only into the input terminals of the gates. Furthermore, the length of the gate metal which gives rise to a resistant component is restricted to a value which is lower than the height of the horizontal channel, thereby reducing the resistance of the gate metal wiring to a great extent. For example, when the height of the cell is approximately 50 .mu.m, the height of the horizontal wiring channel is approximately 150 .mu. m, the sheet resistance of the gate metal is 40 .OMEGA./.quadrature., and the width of the gate metal wiring is 3 .mu.m, the resistance becomes 2000 .OMEGA.(=.OMEGA./.quadrature..times.150 .mu.m/3.mu.m) at a maximum value. If it is presumed that the input capacitance 36 of the gate is approximately 0.1 pF, the delay time of a signal caused by the resistant component becomes 0.20 ns, being negligible relative to the delay time of a gate which is almost 2 to 5 ns.

The above-described embodiment is concerned with CMOS devices, but it is, of course, possible to apply the present invention to a NE/D (N-channel Enhancement Depletion MOS) devices.