MOSFET Device

The present invention relates to a MOSFET device, and more specifically to an arrangement or structure suitable for protection of a power MOSFET against overcurrent or overheating.

FIGS. 35-38 show a conventional example of a vertical MOSFET device disclosed in IEEE Power Electronics Specialists Conference Record, 1985, pp 229.

FIG. 37 is a block diagram of the entire circuit of this device. A vertical power MOSFET is integrated with a protective circuit comprising CMOS and bipolar IC into a so-called power IC of a single chip. The device of FIG. 37 includes a thermal limit circuit 89 for detecting excessive temperature and a current limit circuit 88 for detecting excessive current. If an excessive condition is detected by the limit circuit 88 or 89, a signal is sent to a section of CMOS logic, and the power MOSFET 81 labeled as POWER TMOS is turned off to protect the device.

The current limit is shown in FIG. 35. The current limit has a single cell MOSFET 82 and a current sensing resistor 83. The MOSFET 82 consists of a single cell whereas the main MOSFET 81 consists of several thousand cells (3000 cells in this example) which are all connected in parallel. Therefore, the current through the main MOSFET 81 is 3000 times as large as the current through the single cell MOSFET 82.

A main current flowing through a load 84 is monitored by a current mirror circuit composed of the single cell MOSFET 82 and the current sensing resistor 83.

When the voltage drop across the current sensing resistor 83 is increased by an increase of the current flowing therethrough, either an upper rail comparator 85 or a lower rail comparator 86 produces an overcurrent detection signal. This signal is sent to a gate driving circuit, and causes the interruption of current. In this way, the current limit circuit prevents damage of the device due to overcurrent.

However, this MOSFET device is complicated in circuit configuration, and requires a wide variety of devices such a CMOS logic. Therefore, the size of a power IC chip is increased, the fabricating process is complicated, and the cost is high. Furthermore, this conventional device has not only the overcurrent protection but also other protective functions against excessive temperature and overvoltage, so that cost-utility is low in cases where only overcurrent protection is required.

FIG. 38 shows the thermal protection circuit of this conventional device. This circuit is arranged to detect a change of a base-emitter voltage of a bipolar transistor due to temperature change, and perform the protective function in accordance with the result of comparison with a reference voltage. However, in order to perform such a delicate analog control accurately, this circuit has a complicated and extensive configuration.

FIG. 36 is a cross section showing a basic structure of this conventional device. This structure requires a complicated and time-consuming fabrication process including two steps of epitaxial growths, and a step for forming a buried layer.

It is an object of the present invention to provide a MOSFET device having a protective function which is simple in arrangement, easy to fabricate, and low in cost.

It is another object of the present invention to provide a MOSFET device which can protect a power MOSFET in an effective manner well adapted to the area of safety operation (ASO) of the power MOSFET, with a very simple arrangement.

It is still another object of the present invention to provide a MOSFET IC structure which makes it possible to simplify a protective circuit of a power MOSFET without undesired influences.

According to one aspect of the present invention, a MOSFET device comprises a main MOSFET component having source, drain and gate electrodes, and a protective circuit. The protective circuit comprises first means for monitoring an operating condition of the main MOSFET component, such as a drain current, a drain-source voltage, or a temperature, and second means for turning off the main MOSFET component by decreasing a gate-source voltage if the operating condition exceeds a predetermined dangerous level.

Preferably, the protective circuit comprises a monitor MOSFET component, a monitor resistor, a first branch, and a protective transistor. The monitor MOSFET component has a gate electrode, a source electrode and a drain electrode which is connected with said drain electrode of the main MOSFET component. The monitor resistor is connected between the source electrodes of the main and monitor MOSFET components. The first branch connects the gate electrode of the main MOSFET component with the gate electrode of the monitor MOSFET component. The protective transistor has a first electrode directly connected with the gate electrode of the main MOSFET component, a second electrode and a control electrode connected with a node between said monitor resistor and said source electrode of said monitor MOSFET component.

The second electrode of the monitor MOSFET component is connected with the source electrode of the main MOSFET component, or a gate terminal of the MOSFET device, or some other point which enables the protective transistor to decrease a voltage applied to the gate electrode of the main MOSFET component when a voltage across the monitor resistor is increased.

FIG. 1 is a circuit diagram sowing a MOSFET device of a first embodiment of the present invention.

FIG. 2A is a cross section showing structures of MOSFETs shown in FIG. 1.

FIG. 2B is a cross section showing a structure of a resistor shown in FIG. 1.

FIGS. 3 and 4 are cross sections showing two alternative structrures which can be employed as a protective transistor of FIG. 1.

FIGS. 5A and 5B are, respectively, plan view and cross section showing the device of the first embodiment in the form of an IC.

FIG. 6 is a circuit diagram showing a MOSFET device of a second embodiment of the present invention.

FIG. 7 is a circuit diagram showing a MOSFET device of a third embodiment.

FIG. 8 is a cross section showing a structure of the device of FIG. 7.

FIG. 9 is a cross section showing an alternative form of an n channel MOSFET T.sub.2 shown in FIG. 7.

FIG. 10 is a circuit diagram showing a MOSFET device of a fourth embodiment.

FIGS. 11 and 12 are cross sections showing two alternative structures of a p channel MOSFET T.sub.3 used in the fourth embodiment.

FIG. 13 is a circuit diagram showing a MOSFET device of a fifth embodiment.

FIGS. 14A and 14B are cross section and schematic plan view showing structures of MOSFETs M.sub.1 and M.sub.2 shown in FIG. 13.

FIGS. 15 and 16 are cross sections showing, respectively, structures of a resistor, and a bipolar transistor T.sub.4 of the fifth embodiment.

FIG. 17 is a cross section showing a modification of the fifth embodiment.

FIG. 18 is a cross section showing another structure of the bipolar transistor T.sub.4.

FIGS. 19A and 19B are cross section and plan view showing still another structure of the bipolar transistor T.sub.4.

FIG. 20 is a circuit diagram showing a MOSFET device of a sixth embodiment.

FIG. 21 is a cross section of the device of the sixth embodiment.

FIGS. 22 and 23 are cross section and circuit diagram showing an example in which the structure of the present invention is not used.

FIGS. 24A and 24B are, respectively, circuit diagram and graph showing arrangement and function of a MOSFET device of a seventh embodiment.

FIG. 25A is a graph showing ASO (Area of Safety Operation) of a power transistor.

FIG. 25B is a graph showing a function of the device of FIG. 24A in relation to ASO.

FIG. 25C is a graph showing functions of devices shown in FIGS. 26A, 27A, and 28A.

FIG. 25D is a graph showing a function of a device shown in FIG. 29A.

FIG. 25E is a graph showing a function of a device of FIG. 30A.

FIG. 25F is a graph showing a function of a device of FIG. 31A.

FIGS. 26A and 26B show an eighth embodiment.

FIGS. 27A and 27B show a ninth embodiment.

FIGS. 28A and 28B show a tenth embodiment.

FIGS. 29A and 29B show an eleventh embodiment.

FIGS. 30A and 30B show a twelfth embodiment.

FIGS. 31A and 31B show a thirteenth embodiment.

FIGS. 32A and 32B are plan view and cross section showing a structure employed in each of the embodiments shown in FIGS. 24A-31B.

FIG. 33 is a circuit diagram showing a device of a fourteenth embodiment.

FIG. 34 is a circuit diagram showing a variation of the fourteenth embodiment.

FIG. 35 is a schematic view showing an overcurrent protective circuit of a conventional device

FIG. 36 is a cross section showing a basic structure of the conventional device.

FIG. 37 is a block diagram showing the conventional device.

FIG. 38 is a diagram showing a thermal protective circuit of the conventional device.

FIG. 39 is a circuit diagram showing a conventional power MOSFET device having a thermal protection.

A FIRST EMBODIMENT of the present invention is shown in FIGS. 1-5. A MOSFET device 101 of the first embodiment is provided with overcurrent protection.

As shown in FIG. 1, the MOSFET device 101 includes a main MOSFET component M.sub.1 and a current mirror (or monitor) MOSFET component M.sub.2. In this embodiment, the main MOSFET component M.sub.1 is made up of several thousand cells which are all connected in parallel, while the current mirror MOSFET component M.sub.2 is made up of a single cell which is substantially identical to the cells of the main MOSFET component M.sub.1. A single MOS transistor is formed in each cell. Thus, the main MOSFET component M.sub.1 is a collection of several thousand MOS transistors, all connected in parallel. It is possible to allot two or more cells to the current mirror MOSFET M.sub.2. In any case, the number of the cell or cells of the current mirror MOSFET component M.sub.2 is much smaller than the number of the cells of the main MOSFET component M.sub.1.

The MOSFET device 101 further includes a current sensing (monitor) resistor Rs, an input resistor Ri, and a protective transistor T.sub.1 for controlling the gate voltage of the main MOSFET M.sub.1. In the first embodiment, the transistor T.sub.1 is a metal gate FET(MESFET) or a junction FET(JFET).

The MOSFET device 101 has a gate terminal G, a drain terminal D and a source terminal S. In the first embodiment, a load R.sub.L is connected between the drain terminal D and a supply voltage V.sub.B, and the source terminal S is grounded. Drain electrodes of the main and current mirror MOSFETs M.sub.1 and M.sub.2 are connected together and connected to the drainterminal D of the device 101. Gate electrodes of the main and current mirror MOSFETs M.sub.1 and M.sub.2 of the first embodiment are connected together and connected to a first branch point, which is connected with the gate terminal G through the input resistor Ri. The current sensing resistor Rs is connected between source electrodes of the main and current mirror MOSFETs M.sub.1 and M.sub.2. A drain electrode of the field effect transistor T.sub.1 is connected with the first branch point. A source electrode of the transistor T.sub.1 is connected with the source electrode of the main MOSFET M.sub.1. A gate electrode of the transistor T.sub.1 is connected with a second branch point lying between the current sensing resistor Rs and the source electrode of the current mirror MOSFET M.sub.2. The source electrode of the main MOSFET M.sub.1 is connected to the source terminal S of the device 100.

FIG. 2A shows the structures of the main and current mirror MOSFETs M.sub.1 and M.sub.2. Each of MOSFETs M.sub.1 and M.sub.2 is a vertical MOSFET in which a current flows upwardly from a bottom to a top of a semiconductor chip. As shown in FIG. 2A, a semiconductor substrate has an n.sup.+ lower substrate layer 1 in which the drain electrode common to M and M.sub.2 is produced, and an n-type upper substrate layer 2 formed on the lower layer 1. Each cell which is a constituent of the main and current mirror MOSFETs M.sub.1 and M.sub.2 includes a p-type body region 3 formed in the n-type upper layer 2, at least one n.sup.+ -type source region 4 formed in the body region 3, and a p.sup.+ -type body contact region 5 formed in the body region 3. A gate insulating layer 9 of SiO.sub.2 is formed on the top surface of the semiconductor substrate, and a polysilicon layer 7 serving as a gate electrode is formed on the gate insulating layer 9. The polysilicon layer 7 is covered with an upper insulating layer 6, and separated from a metal interconnection layer 8.

The cells are connected in parallel. Therefore, a load current I.sub.L flowing into the drain terminal of the device 101 is divided into a main current I flowing through the main MOSFET M.sub.1 and a monitor current i flowing through the current mirror MOSFET M.sub.2. The ratio of the monitor current i to the main current I is equal to the ratio of the number of the o cell or cells of the current mirror MOSFET M.sub.2 to the number of the cells of the main MOSFET M.sub.1 .

FIG. 2B shows the structure of the input resistor Ri or the current sensing resistor Rs of the first embodiment. In this example, each of the input resistor Ri and the current sensing resistor Rs is a polysilicon resistor. In this embodiment, the input and current sensing resistors Ri and Rs are formed on the semiconductor substrate in which the MOSFETs M.sub.1 and M.sub.2 are formed. A field oxide layer 10 of SiO.sub.2 is formed on the top surface of the semiconductor substrate, and a polysilicon layer 7 serving as the input or curent sensing resistor Ri or Rs is formed on the field oxide layer 10. In this embodiment, the input and current sensing resistors Ri and Rs are formed simultaneously with the polysilicon gate electrodes of the main and current mirror MOSFETs M.sub.1 and M.sub.2 by a single fabrication step. Accordingly, the fabrication process of the device can be simplified.

FIGS. 3 and 4 show, respectively, the structures of MESFET and JFET which can be used as the protective transistor T of the first embodiment. In either case, the protective transistor T.sub.1 is in the form of a polysilicon film formed on an insulating layer. When the structure of FIG. 3 or 4 is employed, the protective transistor T.sub.1 can be easily integrated with the remaining components of the device into a single IC, and a superior electrical isolation can be obtained without complicating the fabrication process.

The MESFET of FIG. 3 includes source and drain regions 20 and 22 of an n.sup.+ type and an n.sup.- -type channel region 21 which are all polysilicon regions formed in a polysilicon layer deposited on a field SiO.sub.2 layer 10 corresponding to the field oxide layer 10 shown in FIG. 2. A Schottky junction 23 is formed between the n.sup.- channel region 21 and a metal gate electrode G. In the example of FIG. 3, a normally-off type (enhancement mode) transistor can be obtained by choosing the impurity concentration of the channel region 21 so that the channel 21 is entirely depleted at a built-in voltage of the Schottky diode 23. The normally-off transistor is advantageous because the driving current can be reduced during the normal operation during which the overcurrent protection is inoperative.

The structure of FIG. 3 can be fabricated simultaneously with the structures of FIGS. 2A and 2B without increasing the number of the fabrication steps. The polysilicon layer of FIG. 3 can be formed by the step of forming the polysilicon layers 7 shown in FIGS. 2A and 2B. The n.sup.+ regions can be formed simultaneously by a single diffusion step. The metal gate electrode G of FIG. 3 can be formed simultaneously with the metal interconnection layer 8.

The JFET of FIG. 4 has a first polysilicon layer in which there are formed an n.sup.+ source region 30, an n.sup.- channel region 31 and an n.sup.+ drain region 32, and a second polysilicon layer forming a p.sup.+ -type gate region 33.

The JFET of FIG. 4 can be made into a normally-off type by choosing the impurity concentration and thickness of the channel region 31 so that the channel region 31 is completely depleted at a built-in voltage of a pn junction between the gate region 33 and the channel region 31.

Although the structure of FIG. 4 is somewhat complicated because of addition of the second polysilicon layer, it has the following advantage. When the pn junction of the gate is forward biased by application of a gate voltage, holes are injected from the gate region 33 into the channel region 31, so that conductivity modulation takes place in the channel region 31, decreasing the resistance of the channel region 31 of the polysilicon which originally has a high registivity. Therefore, it is possible to reduce the on resistance of the JFET, or to reduce the size of the JFET while holding the on resistance equal to that of the MESFET of FIG. 3.

As shown in FIGS. 5A and 5B, the MOSFET device 101 of the first embodiment is in the form of an integrated circuit. In this example, the main and current mirror MOSFETs M.sub.1 and M.sub.2 having the structure shown in FIG. 2A, the input and current sessing resistors Ri and Rs each having the structure shown in FIG. 2B, and the MESFET shown in FIG. 3 are formed in and on the same n-type semiconductor substrate.

As shown in the plan view of FIG. 5A, the cells which are uniform in structure size are regularly arranged. In this example, only one belongs to the current mirror MOSFET M.sub.2 and the others are connected in parallel to form the main MOSFET M.sub.1.

In the IC of the first embodiment, it is possible to employ the JFET instead of the MESFET by replacing the MESFET in the structure of FIGS. 5A and 5B by the JFET of FIG. 4.

The MOSFET device 101 of the first embodiment is operated as follows:

When a voltage above a threshold voltage of the main and current mirror MOSFETs M.sub.1 and M.sub.2 is applied to the gate terminal G of the device 101 shown in FIG. 1, then the MOSFETs M.sub.1 and M.sub.2 are turned on, and the current I.sub.L flows through the load R.sub.L. In this case, the ratio of the main current I flowing through the main MOSFET M.sub.1 to the monitor current i flowing through the current mirror MOSFET M.sub.2 is equal to the ratio of the number n.sub.1 of the cells of the main MOSFET M.sub.1 to the number n.sub.2 of the cells of the current mirror MOSFET M.sub.2. That is, n.sub.1 :n.sub.2 =I:i.

Because I.sub.L =I+i, the load current I.sub.L is given by; ##EQU1## Therefore, it is possible to know the load current I.sub.L by sensing the monitor current i from the terminal voltage across the current sensing resistor Rs.

In case of accident such as short circuit of the load, an increase of the monitor current i causes an increase of the voltage across the current sensing resistor Rs. When the voltage across the current sensing resistor Rs exceeds a threshold voltage Vth of the protective transistor T.sub.1, the transistor T.sub.1 turns on, and limits the load current I.sub.L by decreasing the gate voltage of the main and current mirror MOSFETs M.sub.1 and M.sub.2.

From the above-mentioned relationship, the resistance of the current sensing resistor Rs required to limit the load current to a limit value I.sub.lim is given by; ##EQU2##

The value of Vth is given by Vth=Vbi-Vp where Vbi is a built-in voltage of the MESFET or JFET and Vp is a pichoff voltage which is the voltage at which the channel is completely depleted.

The pinchoff voltage Vp is given by;

where t is the thickness of the channel 21 or 31, N is the impurity concentration of the channel, q is the electronic charge, and .epsilon..sub.s is the dielectric constant of silicon. Therefore, it is possible to control the threshold voltage Vth by controlling the impurity concentration N and thickness t of the channel.

The built-in voltage Vbi of each of the MESFET and JFET is only 1 V or less. Therefore, it is possible to obtain the normally-off type FET whose threshold voltage Vth=0.about.1 V. By lowering the threshold voltage Vth, it is made possible to decrease the value of the current sensing resistor Rs, so that the accuracy of the current mirror operation can be improved.

Thus, in the present invention, the number of required components is small, and the fabrication process is simplified.

A SECOND EMBODIMENT of the present invention is shown in FIG. 6. A device 102 of the second embodiment is a MOSFET device including all the circuit components of the first embodiment device 101. However, the MOSFET device 102 of the second embodiment is different from the first embodiment device 101 in the addition of a second input resistor Ri.sub.2 interposed between the gate electrode of the main MOSFET M.sub.1 and the gate electrode of the current mirror MOSFET M.sub.2. By separating the gate electrodes of the MOSFETs M.sub.1 and M.sub.2, the second input resistor Ri.sub.2 allows the MOSFETs M.sub.1 and M.sub.2 to operate separately, during turn-on of the protective transistor T.sub.1. With this second input resistor Ri.sub.2, the MOSFET device 102 of the second embodiment is arranged so that the main MOSFET M.sub.1 is completely cut off when an overcurrent is detected.

When the current sensing resistor Rs of FIG. 6 detects an overcurrent, the protective transistor T.sub.1 consisting of the MESFET or JFET turns on. In this case, a gate voltage V.sub.G1 of the main MOSFET M.sub.1 whose gate is connected with the drain of the protective transistor T.sub.1 is immediately reduced to zero volt, so that the main MOSFET M.sub.1 cuts off the current path.

On the other hand, a gate voltage V.sub.G2 of the current mirror MOSFET M.sub.2 remains almost unchanged because of interposition of the second input resistor Ri.sub.2 whose value is so chosen that Ri.sub.2 is much greater than the resistance value of the first input resistor Ri.sub.1 corresponding to the input resistor of the first embodiment (i.e. Ri.sub.2 >>Ri.sub.1). Therefore, the current mirror MOSFET M.sub.2 remains on, and holds the terminal voltage across the current sensing resistor Rs above the threshold voltage of the transistor T.sub.1. As a result, the protective transistor T.sub.1 continues to be on, and accordingly the main MOSFET M.sub.1 continues to be off.

In the first embodiment device 101 arranged to limit the current to the limit value I.sub.lim on the occurrent of overcurrent, the power MOSFET consumes electric power of V.sub.DS .times.I.sub.lim. Because the drain-source voltage V.sub.DS normally becomes excessively high for the limit current value I.sub.lim which is higher than a design current, and the limit current I.sub.lim is greater than the normal working current, this power consumption given by the product of V.sub.DS and I.sub.lim becomes considerably higher than the power consumption during normal operation, and causes such an increase in the temperature of the device that a radiating plate or other cooling means is required in some cases. In contrast, the device 102 of the second embodiment can provide not only overcurrent protection but also protection against overheating due to overcurrent by completely cutting off the main MOSFET M.sub.1 when once the current exceeds the limit value I.sub.lim. Therefore, the second embodiment can eliminate, or reduce the size of, the radiating plate.

It is possible to form the MOSFET device 102 of the second embodiment into an integrated circuit in the same manner as the device 101 of the first embodiment by using the structures shown in FIGS. 2A-5B.

A THIRD EMBODIMENT of the present invention is shown in FIGS. 7 and 8. A MOSFET device 103 of the third embodiment is almost the same as the first embodiment device 101. In the third embodiment, however, an n channel MOSFET is used as a protective transistor T.sub.2 corresponding to the transistor T.sub.1 of the first embodiment. In the third embodiment, this n channel MOSFET T.sub.2, current sensing resistor Rs and input resistor Ri are all made of polysilicon.

The circuit of FIG. 7 is different from the circuit of FIG. 1 only in that the n channel MOSFET T.sub.2 is substituted for the transistor T.sub.1.

Although the device 103 of the third embodiment may be in the form of a conventional circuit consisting of discrete devices, it is easy to built all the components of the devices 103 into a single chip by employing the structure shown in FIG. 8.

The main and current mirror MOSFETs M.sub.1 and M.sub.2 are of the vertical type, and have a common drain electrode 40 connected directly to an n.sup.+ lower layer 41 of a semiconductor substrate. A p body region 43 of each cell is formed in an n upper layer 42 of the substrate. A polysilicon gate electrode 47 is formed above the body region 43, and insulated from the semiconductor surface by a gate SiO.sub.2 layer 48. At least one n.sup.+ source region 45 is formed in the body region 43. A p.sup.+ body contact region 44 is formed in the body region 43. The gate electrode 47 is covered with a PSG layer 46.

The current sensing resistor Rs and input resistor Ri are polysilicon resistors formed simultaneously with the polysilicon gate electrodes 47. The n channel MOSFET T.sub.2 of this example is a polysilicon TFT formed on a field SiO.sub.2 film 53. The polysilicon film of T.sub.2 can be also formed simultaneously with the gate electrodes 47. A gate SiO.sub.2 layer 49 is formed on an n.sup.- polysilicon channel region 54 of T.sub.2, and an Al gate electrode G is formed on the gate SiO.sub.2 layer 49. On both sides of the channel region 54, there are formed n.sup.+ polysilicon source and drain regions 50 and 51. A p.sup.+ guard ring region 52 is formed in the upper layer 42 under the field SiO.sub.2 layer 53.

The protecive transistor T.sub.2 of the third embodiment is formed into a so-called accumulation type MOSFET structure having a doping configuration of n.sup.+ -n.sup.- -n.sup.+ in order to decrease the threshold voltage as much as possible.

Each of the resistors Rs and Ri and the transistor T.sub.2 has a so-called SOI structure, so that a superior electrical isolation can be obtained, and the entire structure can be simplified.

FIG. 9 shows another example of the structure of the n channel MOSFET T.sub.2. The example of FIG. 9 is also a polysilicon TFT. In the example of FIG. 9, a gate SiO.sub.2 layer 58 is an insulating layer formed on the top surface of the semiconductor substrate simultaneously with the gate insulating layers of the vertical MOSFETs M.sub.1 and M.sub.2. A p.sup.+ gate diffusion region 55 is formed in the n upper layer 42 of the substrate under the gate insulating layer 58. The polysilicon layer of T.sub.2 includes an n.sup.- channel region 56, and n.sup.+ -type source and drain regions 57 and 59.

In the device 103 of the third embodiment, an increase of the terminal voltage Vs of the current sensing resistor Rs caused by an increase of the monitor current i due to short circuit causes a decrease of the on resistance of the n channel MOSFET T.sub.2, and a consequent decrease of the gate volta V.sub.G of the main and current mirror MOSFETs M.sub.1 and M.sub.2.

A FOURTH EMBODIMENT of the present invention is shown in FIGS. 10 and 11. A MOSFET device 104 of the fourth embodiment is arranged to achieve the current limit for overcurrent protection with a p channel MOSFET T.sub.3.

As shown in FIG. 10, the p channel MOSFET T.sub.3 is connected in series with the gates of the main and current mirror MOSFET M.sub.1 and M.sub.2. The gate of the p channel MOSFET T.sub.3 is connected to a branch point between the current mirror MOSFET M.sub.2 and the current sensing resistor Rs. Another resistor Ro is interposed between the source terminal S and a branch point between the p channel MOSFET T.sub.3 and the gates of the main and current mirror MOSFET M.sub.1 and M.sub.2.

In the device 104 of FIG. 10, an increase of the terminal voltage Vm of the current sensing resistor Rs due to overcurrent causes an increase of the on resistance of the p channel MOSFET T.sub.3, which, in turn, causes a decrease of the gate voltage V.sub.G of the main and current mirror MOSFET M.sub.1 and M.sub.2 to limit the overcurrent.

The main and current mirror MOSFETs M.sub.1 and M.sub.2, and the resistors Rs and Ro of the fourth embodiment are constructed in the same manner as shown in FIG. 8. THe p channel MOSFET T.sub.3 is constructed as shown in FIGS. 11 or 12. Except that the conductivity type is opposite in each region of the polysilicon layer, the structure of FIG. 11 is similar to the structure of T.sub.2 shown in FIGS. 8, and the structure of FIG. 12 is similar to the structure of FIG. 9. In the example of FIG. 11, the polysilicon layer has a p.sup.- -type channel region 61 and p.sup.+ -type source and drain regions 60 and 62, and a gate SiO.sub.2 layer 63 is formed on the polysilicon layer. In the example of FIG. 12, the polysilicon layer includes a p.sup.- -type channel region 65, and p.sup.+ -type source and drain regions 64 and 66, and a p.sup.+ -type diffusion gate region 68 is formed in the n upper layer 42 under a gate SiO.sub.2 layer 67.

Each of the preceding embodiments is advantageous in that the fabricating process is simple and easy, and the number of required circuit components is small, so that the components can be easily integrated into a single chip of a small size.

A FIFTH EMBODIMENT of the present invention is shown in FIGS. 13-15. A MOSFET device 105 of the fifth embodiment is similar to the second embodiment device 102 shown in FIG. 6 in that the input resistor Ri is interposed between the gates of the main an current mirror MOSFETs M.sub.1 and M.sub.2. However, the fifth embodiment device 105 differs from the second embodiment device 102 in that the protective transistor for limiting the gate voltage V.sub.G1 of the main MOSFET M.sub.1 is a bipolar transistor T.sub.4.

The structures of the main and current mirror MOSFETs M.sub.1 and M.sub.2 shown in FIG. 14A are similar to those of the preceding embodiments. The main and current mirror MOSFETs M.sub.1 and M.sub.2 are separated from each other by an isolation region as shown in FIGS. 14A and 14B. FIG. 14B shows only the polysilicon layer 7 used as the gate electrodes of the main and current mirror MOSFETs M.sub.1 and M.sub.2. In the example of FIG. 14B, the current mirror MOSFET M.sub.2 includes more than one cell. In each of M.sub.1 and M.sub.2, the cells are regularly arranged.

FIG. 15 shows a polysilicon resistor used as the input and current sensing resistors Ri and Rs. A polysilicon layer 7 shown in FIG. 15 is formed on the field oxide layer 10 simultaneously with the polysilicon layer 7 shown in FIGS. 14A and 14B. Doping to the polysilicon layer 7 of FIG. 15 can be performed by the steps for forming the p body regions 3 and p.sup.+ body contact regions 5 of M.sub.1 and M.sub.2, or by the step for forming the n.sup.+ source regions 4.

FIG. 16 shows the bipolar transistor T.sub.4. A p-type first base region 120 is formed in the n-type upper substrate layer 2 of the semiconductor substrate, simultaneously with the p body regions 3 of main and current mirror MOSFETs M.sub.1 and M.sub.2. The bipolar transistor T.sub.4 further includes a p.sup.+ second base region 121 and an n.sup.+ emitter region 122. The impurity concentration of the second base region 121 is higher than that of the first base region 120. The second base region 121 is formed in the first base region 120 by the step for forming the p.sup.+ body regions of M.sub.1 and M.sub.2. The emitter region 122 is formed in the second base region 121 by the step for forming the n.sup.+ source regions 4 of M.sub.1 and M.sub.2.

The second base region 121 and the emitter region 122 are formed by the technique of Diffusion Self Alignment (DSA) using the same mask, in order to reduce a base width of the bipolar transistor T.sub.4 formed in the lateral direction at or near the semiconductor substrate surface. A part of the second base region 121 is cut by forming an n-type collector region 123 after the second base region 121 has been formed. Therefore, it is possible to obtain a high h.sub.FE by lowering the impurity concentration of the base and reducing the base width of the lateral transistor T.sub.4.

The fifth embodiment can simplify the fabrication process of the MOSFET device by eliminating the necessity of a CMOS logic and a complicated bipolar transistor structure, and facilitate the reduction of the chip size in the same as in the preceding embodiments.

The bipolar transistor T.sub.4 of the fifth embodiment is operated as follows:

The main and current mirror MOSFETs M.sub.1 and M.sub.2 are both turned on, and the load current I.sub.L is caused to flow through the load R.sub.L by application to the gate terminal G of the device 105, of a voltage V.sub.G above the threshold voltage Vth of the MOSFETs M.sub.1 and M.sub.2. During normal operation, the bipolar transistor T.sub.4 remains off, so that V.sub.G =V.sub.G1 =V.sub.G2, and n.sub.1 :n.sub.2 =I:i. Therefore, the load current I.sub.L which is equal to the sum of I and i is given by; ##EQU3## Therefore, the voltage Vs developed between both ends of the current sensing resistor Rs (Vs=Rs.times.i) is proportional to the load current I.sub.L.

This device is so designed that, during normal operation, the voltage Vs across the resistor Rs remains lower than a threshold value V.sub.BE (.apprxeq.0.6 V) Of the base-emitter voltage of the bipolar transistor T.sub.4. Therefore, the bipolar transistor T.sub.4 is held off, and ensures the above-mentioned current mirror operation by maintaining the relationship V.sub.G =V.sub.G1 =V.sub.G2.

When the load current I.sub.L is increased by a short circuit of the load or some other accident, the monitor current i increases in proportion to the load current I.sub.L. If the voltage Vs across the current sensing resistor Rs is increased by the increase of the monitor current i beyond the base-emitter voltage V.sub.BE =0.6 V of the bipolr transistor T.sub.4, then the transistor T.sub.4 is turned on, and the gate voltage V.sub.G1 of the main MOSFET M.sub.1 is decreased. Thus, the gate voltage V.sub.G1 becomes lower than V.sub.G2 (V.sub.G =V.sub.G2 >V.sub.G1).

In order to limit the load current I.sub.L to a limit value I.sub.lim, the value of the current sensing resistor Rs is set as; ##EQU4## Therefore, the bipolar transistor T.sub.4 can limit the load current I.sub.L to the value I.sub.lim by turning on at the current value I.sub.lim.

When the gate voltage V.sub.G1 of M.sub.1 is lower than the gate voltage V.sub.G2 of M.sub.2, the principle of current mirror does not hold any more because of inequality between V.sub.G1 and V.sub.G2. In the main MOSET M.sub.1, a decrease of the gate voltage V.sub.G1 causes a steep increase of the on resistance Ron of th main MOSFET M.sub.1. Therefore, the drain-source voltage V.sub.DS increases notwithstanding the decrease of the main current I (.apprxeq.I.sub.L) through M.sub.1. The drain-source volta is given by; ##EQU5## On the other hand, the gate voltage V.sub.G2 of the current mirror MOSFET M.sub.2 remains equal to V.sub.G. Therefore, the monitor current i through M.sub.2 increases because of an increase of V.sub.D. Thus, the monitor current i through M.sub.2 increases whereas the main current I decreases. Therefore, the voltage Vs across the current sensing resistor Rs is further increased. This increase of Vs strengthens the on state of the bipolar transistor T.sub.4, and further decreases the gate voltage VG.sub.1 of M.sub.1 in the manner of positive feedback. Finally, the gate voltage V.sub.G1 of M.sub.1 becomes lower than the threshold voltage Vth, and the main MOSFET M is cut off, so that no or little current flows through M.sub.1. In this way, the bipolar transistor T.sub.4 protects the main MOSFET M.sub.1 if an overcurrent once exceeds the limit value I.sub.lim. The arrangement of the fifth embodiment can prevent an excessive increase of the junction temperature and avoid the possibility of thermal runaway by reducing the current through the main MOSFET M.sub.1 to almost zero in the same manner as in the second embodiment.

The polysilicon film resistor shown in FIG. 15 is stable against temperature increase, and superior in electrical isolation from M.sub.1 and M.sub.2.

The bipolar transistor T.sub.4 of the fifth embodiment can serve in a stable manner as a comparator for detecting an overcurrent because it is formed by the DSA technique which makes it possible to reduce the base width to a very small value.

FIG. 17 shows a modification of the fifth embodiment device. The modification of FIG. 17 is different from the structure of FIG. 16 only in that a pinch region 125 under the collector region 123 is used as the current sensing resistor Rs. The structure of FIG. 17 utilizes a portion of the p-type first base region 120 having a high resistivity as a pinch resistor, so that the chip size can be further reduced.

The bipolar transistor T.sub.4 of the fifth embodiment may be in the form of a three layer npn polysilicon transistor shown in FIG. 18 or in the form of a single layer polysilicon transistor shown in FIGS. 19A and 19B, instead of the structure of FIG. 16.

Polysilicon has many traps in grain boundaries. In a typical example, therefore, the diffusion length of electrons which are minority carriers is from

several thousand angstroms to one micrometer. It is possible to use the polysilicon safely when the base width is made as small as the level of such a diffusion length. Even though a transistor structure has h.sub.FE smaller than one, the structure is usable if the output impedance of T.sub.4 is sufficiently low as compared with the input resistor Ri.

The structure of FIG. 18 has a first polysilicon layer in which an n-type collector region 131 is formed, a second polysilicon layer in which a p.sup.+ base region 132 is formed, and a third polysilicon layer in which an n.sup.+ emitter region 133 is formed. The first layer is formed on the insulating layer formed on the top surface of the semiconductor substrate. The second layer is formed on the first layer, and the third layer is on the second layer. There is further provided a PSG layer 130. In this example, the thickness of each of the collector region 131 and the emitter region 133 approximately equals 1 micrometer, and the thickness of the base region 132 approximately equals 5000 .ANG. (angstrom).

In order to prevent interlayer diffusion of impurities among the three polysilicon layers, it is advisable to form these polysilicon layers by deposition such as LPCVD after the formation of the vertical MOSFETs M.sub.1 and M.sub.2.

The three layer structure of FIG. 18 is somewhat disadvantageous in that the number of fabrication steps is slightly increased. However, this structure is superior in performance because there is formed no parasitic bipolar transistor at all.

The bipolar transistor of FIGS. 19A and 19B is formed in a single polysilicon layer, so that the

fabrication process is simplified as compared with the structure of FIG. 18.

The structure of FIGS. 19A and 19B has an n.sup.+ emitter region 134, a p.sup.+ base region 135, an n collector region 36 and an n.sup.+ collector region 137, which are all formed in a polysilicon layer 139 formed on the insulating layer on the semiconductor substrate.

In this example, the base width is reduced by DSA technique. Diffusion of the base region 135 and diffusion of the emitter region 134 are performed successively by using the same diffusion mask of a thick SiO.sub.2 layer or the like. The base width is controlled to a small value by a difference between both diffusions. In FIG. 19B, the DSA mask is denoted by a numeral 138. A numeral 40 denotes a lead region of the base region 135. A base electrode is provided in this lead region 140.

The device of FIGS. 19A and 19B is a lateral type, so that this device requires a larger size than the example of FIG. 18 in order to obtain the same driving ability. However, the structure of FIGS. 19A and 19B is easy to fabricate, and completely free from parasitic bipolar transistor because of its SOI structure.

A SIXTH EMBODIMENT of the present invention is shown in FIGS. 20 and 21. The sixth embodiment is identical to the fifth embodiment in that the bipolar transistor T.sub.4 is employed as the protective transistor for controlling the gate voltage of the main MOSFET M.sub.1. In the sixth embodiment, however, the gates of the main and current mirror MOSFETs M.sub.1 and M.sub.2 are connected together as in the first embodiment.

As shown in FIG. 21, the bipolar transistor T.sub.4 having the same structure as shown in FIG. 16 is integrated with the main and current mirror MOSFETs M.sub.1 and M.sub.2. The bipolar transistor T.sub.4 of FIG. 21 is formed in the same manner as the structure of FIG. 16.

The p-type first base region 120 is formed in the n upper substrate layer 2 simultaneously with the p body regions 3 of M.sub.1 and M.sub.2 by the same process. The p.sup.+ second base region 121 is formed in the first base region 120, simultaneously with the p.sup.+ body contact regions 5 of M.sub.1 and M.sub.2 by the same process. The n.sup.+ emitter region 122 is formed simultaneously with the n.sup.+ source regions 4 of M.sub.1 and M.sub.2.

In order to reduce the base width of the lateral type bipolar transistor T.sub.4, the second base region 121 and the emitter region 122 are formed by diffusion (Diffusion Self Alignment) using the same mask. A part of the second base region 121 is cut by forming the collector region 123 after formation of the second base region 121. By this process, it is possible to obtain a high h.sub.FE by reducing the base width and lowering the impurity concentration of the base of the lateral bipolar transistor T.sub.4.

In the structure of FIG. 21, there is formed a parasitic bipolar transistor T.sub.1 * in the vertical direction, as shown in FIG. 21. However, the base width of this parasitic transistor T.sub.1 * is considerably larger than that of the lateral transistor T.sub.4. Furthermore, it is possible to reduce h.sub.FE of the parasitic transistor T.sub.1 * to a negligible value because the impurity concentration of the second base region 121 is high. Therefore, the structure of T.sub.4 shown in FIGS. 16 and 21 can prevent undesired influences of the parasitic bipolar transistor.

For comparison with the structure of T.sub.4 shown in FIG. 21, FIG. 22 shows a lateral bipolar transistor structure having only a single base region. The bipolar transistor T.sub.4 ' of FIG. 22 has a p-type single base region 112 formed in the n upper substrate layer 2 of the semiconductor substrate, and n.sup.+ -type collector and emitter regions 111 and 114, formed in the base region 112. There is further formed a p.sup.+ base contact region 113. In this structure of FIG. 22, it is not possible to sufficiently reduce h.sub.FE of a parasitic bipolar transistor T.sub.2 * formed vertically as shown in FIG. 22. Therefore, as shown in an equivalent circuit of FIG. 23, the parasitic bipolar transistor T.sub.2 * is connected between the drain and source of the main MOSFET M.sub.1.

In case of overcurrent, this parasitic transistor T.sub.2 * is turned on together with the intended transistor T.sub.4 ' because both transistors share the base. Therefore, the current readily destroys the device by concentrating in the parasitic transistor T.sub.2 * instead of flowing through the main and current mirror MOSFETs M.sub.1 and M.sub.2.

In contrast, the bipolar transistor structure T.sub.4 shown in FIGS. 16 and 21 is free from such a problem of parasitic transistor. In this lateral bipolar transistor T.sub.4, the base width is made short, and the part of the second base region 121 which is lowered in concentration by the collector region 123 is used as a substatial base. Furthermore, this lateral bipolar transistor T.sub.4 employs the two layer base structure consisting of the second base region 121 of a higher impurity concentration, and the first base region 120 which is lower in impurity concentration but deeper from the semiconductor substrate surface. Therefore, it is possible to remarkably reduce h.sub.FE of the parasitic bipolar transistor.

In the sixth embodiment, it is possible to employ the modification of FIG. 17, and the variations of FIGS. 18, 19A and 19B in the same manner as in the fifth embodiment.

A SEVENTH EMBODIMENT of the present invention is shown in FIG. 24A and 24B.

To facilitate understanding of the seventh embodiment, reference is first made to ASO (Area of Safety Operation) of a power transistor shown in FIG. 25A.

In the graph of FIG. 25A, the drain current I.sub.D is expressed along the vertical axis, and the drain-source voltage V.sub.DS is expressed along the horizontal axis. In FIG. 25A, the safe operating area of the transistor is bounded by a horizontal solid line "a" along which the current I.sub.D is constant, a curved solid line "b" along which the power I.sub.D .times.V.sub.DS is constant and a vertical solid line "c" along which the voltage V.sub.DS is constant.

The line a is a boundary defined by a maximum current value. An area above the line a is an excessive current area. The line b is a boundary defined by a maximum value of the power consumption in the chip. The power is excessive in an area beyond the line b. In the area beyond the line b, the power dissipation is excessive, so that the device is overheated. Thus, the line b is not only the boundary of the excessive power area, but also the boundary of the excessive temperature area. The line c which is defined by a maximum voltage value is a boundary between the safe operating area and an overvoltage area.

In this way, the safe operating area of a power transistor is determined by three conditions of current, power and voltage. In order to obtain a transistor having maximum capabilities near the limit of the safe operating area, it is desirable to make the protective function as close to the characteristic of FIG. 25A as possible.

The seventh embodiment device shown in FIGS. 24A has the main MOSFET M.sub.1 for driving a load, and the monitor MOSFET M.sub.2 for current mirror, as in the preceding embodiments. The number of cells of M.sub.1 is much greater than the number of cells of M.sub.2. The current is divided between M.sub.1 and M.sub.2 according to the ratio N of the number of cells of M.sub.1 to that of M.sub.2 as in the preceding embodiments.

The device further includes a first resistor R.sub.1 for sensing a drain voltage V.sub.DS, and a second resistor R.sub.2 connected between the source of the main MOSFET M.sub.1 and a branch point at which the first resistor R.sub.1 and the source of the current mirror MOSFET M.sub.2 are connected together. The first resistor R.sub.1 is connected between the drain and source of M.sub.2. A bipolar transistor Tr.sub.1 is connected between the gate and source of the main MOSFET M.sub.1. The second resistor R.sub.2 is connected between the base and emitter of Tr.sub.1 so that the voltage across the resistor R.sub.2 is applied between the base and emitter of Tr.sub.1 . The gates of the main and current mirror MOSFETs M.sub.1 and M.sub.2 are connected together.

The seventh embodiment device is operated as follows:

A drain current I.sub.1 of M.sub.2 is 1/N of the drain current I.sub.D of M.sub.1. Under the condition that R.sub.1 is much greater than R.sub.2 (R.sub.1 >>R.sub.2), a current I.sub.2 through the resistor R.sub.1 is proportional to the drain-source voltage V.sub.DS of the main MOSFET M.sub.1, and given by I.sub.2 =V.sub.DS /R.sub.1.

On the other hand, the current flowing through the second resistor R.sub.2 is equal to the sum (I.sub.1 +I.sub.2) of I.sub.1 and I.sub.2. The voltage V.sub.1 across R.sub.2 is given by; ##EQU6##

By this voltage V.sub.1, the base-emitter junction of Tr.sub.1 is forward biased. If the voltage V.sub.1 rises and exceeds a predetermined voltage V.sub.F (.perspectiveto.0.6 V), the transistor Tr.sub.1 turns on, so that a gate-source voltage V.sub.GS becomes approximately equal to V.sub.F (V.sub.GS .perspectiveto.V.sub.F), and the MOSFETs M.sub.1 and M.sub.2 are turned off.

FIG. 24B shows the condition that V.sub.1 .gtoreq.V.sub.F. In an area above a solid line of operating characteristic shown in FIG. 24B, V.sub.1 >V.sub.F, so that Tr is on and M.sub.1 is off.

The operating characteristic line shown in FIG. 24B is given by; ##EQU7##

In the equation (2), R.sub.1, R.sub.2, N and V.sub.F are constant. Therefore, by using A for -N/R.sub.1 and B for N/R.sub.2, i.e., ##EQU8## the equation (2) is rewritten as;

where A is a negative constant, and B is a positive constant.

FIG. 25B shows the relation between the operating characteristic line of the seventh embodiment and ASO. In FIG. 25B, ASO is shown by a solid line, and the operating characteristic is shown by a broken line.

In order to use the protective means of the seventh embodiment as a protection against excessive power, it is necessary to set the operating characteristic line below ASO. This requirement is expressed by a maximum value of the product I.sub.D .times.V.sub.DS on the operating characteristic line, and a maximum permissible power dissipation P.sub.D of the power MOSFET as follows:

In the seventh embodiment device, it is possible to set the operating characteristic line freely within a range satisfying the condition (4), by choosing the values of R.sub.1 and R.sub.2 appropriately.

By using A and B, the maximum value of I.sub.D .times.V.sub.DS on the operating characteristic line is expressed as -B.sup.2 /4A. Therefore, the expression (4) is rewritten as;

It is easy to accurately control the predetermined voltage V.sub.F of the bipolar transistor Tr.sub.1. Therefore, the seventh embodiment device can operate very accurately in spite of its relatively simple construction. The seventh embodiment can provide a low-cost MOSFET device having an overpower protection without requiring a complicated and large-sized IC structure.

AN EIGHTH EMBODIMENT of the present invention is shown in FIGS. 26A and 26B. In the eighth embodiment, an overcurrent protection is added to the overpower protection of the seventh embodiment.

In the MOSFET device of FIG. 26A, an overcurrent protective section is composed of a third MOSFET M.sub.3, a third resistor R.sub.3 and a second bipolar transistor Tr.sub.2. Like the MOSFET M.sub.2, the third MOSFET M.sub.3 is a current mirror MOSFET of the main MOSFET M.sub.1. A current I.sub.3 flowing through the third MOSFET M.sub.3 is proportional to I.sub.D flowing through M.sub.1. In this embodiment, the number n.sub.3 of cells of M.sub.3 is equal to the number n of cells of M.sub.2. However, it is optional to employ the structure in which n.sub.3 is not equal to n.sub.2.

The drain electrodes of M.sub.1, M.sub.2 and M.sub.3 are connected together to the drain terminal D of the device. The gate electrodes of M.sub.1, M.sub.2 and M.sub.3 are connected together to the gate terminal G. As in the seventh embodiment, the first resistor R.sub.1 is connected between the drain terminal and the source electrode of the M.sub.2. The second resistor R.sub.2 is connected between the source electrode of M.sub.2 and the source terminal S of the device.

The third resistor R.sub.3 is connected between the source electrode of M.sub.3 and the source terminal S of the device. Each of the first and second bipolar transistors Tr.sub.1 and Tr.sub.2 is connected between the gate and source of the main MOSFET M.sub.1. The third resistor R.sub.3 is connected between the base and emitter of the second bipolar transistor Tr.sub.2 so that the voltage across the third resistor R.sub.3 is applied between the base and emitter of Tr.sub.2. The second resistor T.sub.2 is connected between the base and emitter of Tr.sub.1 as in the seventh embodiment.

The eighth embodiment device is operated as follows:

When the current I.sub.3 flows through the third resistor R.sub.3, and the voltage V.sub.2 across the third resistor R.sub.3 exceeds V.sub.F, then the second bipolar transistor Tr.sub.2 is turned on, so that all of the three MOSFETs M.sub.1, M.sub.2 and M.sub.3 are turned off.

The operating area of the eighth embodiment is shown by a solid line in FIG. 26B. In the eighth embodiment, as shown in FIG. 26B, if

then the protective function is performed independent of V.sub.DS.

The characteristic of the eighth embodiment is shown by a broken line in FIG. 25C. The eighth embodiment can provide a protection with respect to the overcurrent line a, in addition to the protection with respect to the overpower line b.

A NINTH EMBODIMENT of the present invention is shown in FIGS. 27A and 27B. The device of the ninth embodiment combines an overcurrent protection with an overpower protection, as in the eighth embodiment.

The circuit of FIG. 27A is different from the circuit of 24A of the seventh embodiment only in the addition of a MOSFET M.sub.4. The MOSFET M.sub.4 is connected between the drain electrode of the main MOSFET M.sub.1 and the first resistor R.sub.1. The gate and drain of M.sub.4 are connected together.

In the device of FIG. 27A, the current I.sub.2 does not flow until the voltage applied between the drain and source of the MOSFET M.sub.4 becomes equal to or greater than a threshold voltage V.sub.th4 of M.sub.4. The current I.sub.2 is given by;

Therefore, the operating area shown by a solid line in FIG. 27B is obtained. The ninth embodiment can provide the protective function shown by the broken line in FIG. 25C like the eighth embodiment of FIG. 26A.

A TENTH EMBODIMENT of the present invention is shown in FIGS. 28A and 28B. The device of the tenth embodiment also combines the overcurrent protection and the protection against excessive power.

The circuit of FIG. 28A is the same as the circuit of FIG. 27A except that a zener diode ZD.sub.1 is used in place of the MOSFET M.sub.4. A cathod of the zener diode ZD.sub.1 is connected with the drain electrode of the main MOSFET M.sub.1. An anode of ZD.sub.1 is connected with one end of R.sub.1.

The operation of the tenth embodiment is similar to that of the ninth embodiment shown in FIGS. 27A and 27B. The operating characteristic of the tenth embodiment is shown by a solid line in FIG. 28B. In FIG. 28B, a horizontal V.sub.DS axis intercept of the solid line is greater than that of the broken line by a zener voltage V.sub.Z1 of the zener diode ZD.sub.1. The tenth embodiment can provide the protective function shown by the broken line in FIG. 25C.

AN ELEVENTH EMBODIMENT of the present invention is shown in FIGS. 29A and 29B. In this embodiment, a resistor R.sub.4 and a zener diode ZD.sub.2 are added to the circuit of FIG. 24A.

As shown in FIG. 29A, the resistor R.sub.1 is connected between the drain terminal D and a first branch point, and the zener diode ZD.sub.2 is connected between the first branch point and the source terminal S. The resistor R.sub.4 is connected between the first branch point and a second branch point lying between the source of M.sub.2 and the resistor R.sub.2.

In FIG. 29B, V.sub.Z2 is a zener voltage of ZD.sub.2. In the eleventh embodiment device, the current I.sub.2 is fixed at I.sub.2 =V.sub.Z2 /R.sub.4 in the range in which; ##EQU9## Therefore, the operating area shown by a solid line in FIG. 29B is obtained.

The relation between the characteristic of the eleventh embodiment and ASO is shown in FIG. 25D. The protective arrangement of the eleventh embodiment functions as a protection against excessive power like the protection shown in FIG. 25B. In the seventh embodiment, however, it is possible to adjust the protective function more precisely in agreement with the maximum permissible power dissipation curve b.

A TWELFTH EMBODIMENT of the present invention is shown in FIGS. 30A and 30B. The device of the twelfth embodiment combines the feature of the tenth embodiment shown in 28A and the feature of the eleventh embodiment shown in FIG. 29A. In FIG. 30B, a solid line shows the operating area obtained by the twelfth embodiment. The relation of the characteristic of this embodiment with respect to ASO is shown in FIG. 25E. The twelfth embodiment can provide overcurrent protection and overpower protection which are precisely conformed to the ASO boundaries.

A THIRTEENTH EMBODIMENT of the present invention is shown in FIGS. 31A and 31B. The device of this embodiment has an overvoltage protection in addition to the overcurrent protection and the overpower protection.

In the circuit shown in FIG. 31A, a third zener diode ZD.sub.3 is added to the circuit of FIG. 30A. The third zener diode ZD.sub.3 is connected between the source and drain of the main MOSFET M.sub.1.

In this embodiment, a zener voltage of the third zener diode ZD.sub.3 is set at a value equal to or lower than a breakdown voltage BD.sub.DS of the main MOSFET M.sub.1. Therefore, the main MOSFET M.sub.1 is protected from damage due to breakdown even if a voltage above the breakdown voltage is applied between the drain and source of M.sub.1.

The operating characteristic of the thirteenth embodiment is shown by a solid line in FIG. 31B, and the relation with ASO is shown in FIG. 25F.

The thirteenth embodiment can provide the protection effective against all of the three factors of ASO, i.e. excessive current power and voltage.

Because the third zener diode ZD.sub.3 directly clamps the drain-source voltage V.sub.DS of the main MOSFET M.sub.1, the third zener diode ZD.sub.3 must have a very large capacity as compared with the zener diodes ZD.sub.1 and ZD.sub.2. A method disclosed in Japanese patent provisional publication No. 59-98557 is helpful for forming the third zener diode ZD.sub.3 of such a large capacity between the source and drain of the MOSFET M.sub.1.

A main portion of the device of each of the seventh to thirteenth embodiments is shown in FIGS. 32A and 32B. The main and current mirror MOSFETs M.sub.1 and M.sub.2, the bipolar transistor Tr.sub.1, and the resistors R.sub.1 and R.sub.2 are formed in and on the same semiconductor substrate. The MOSFETs M.sub.1 and M.sub.2 are constructed in the same manner as shown in FIGS. 5A and 5B. Each of the resistors R.sub.1 and R.sub.2 is a polysilicon film resistor formed above and insulated from the substrate in the same manner as shown in FIGS. 2B or 15. It is possible to form the resistors R.sub.3 and R.sub.4 in the same manner. The bipolar transistor Tr.sub.1 of this example is constructed in the same manner as shown in FIGS. 16 or 21. It is possible to form the bipolar transistor Tr.sub.2 in the same manner.

In each of the embodiments shown in FIGS. 24A-31B, a protection against overheating is achieved with a very simple protective arrangement without requiring any means for temperature detection. Furthermore, this protective arrangement is easy to fabricate and suitable for integration with a main power MOSFET and for size reduction of an IC chip.

A FOURTEENTH EMBODIMENT of the present invention is shown in FIG. 33. In this embodiment, the bipolar transistor structure shown in FIG. 21 is used for a thermal protection.

FIG. 39 shows a conventional example of a thermal protective circuit (as disclosed in Denso Gijutsu Kai Kaiho vol. 30, no. 4, pages 17-23).

A power MOSFET device 200 shown by a broken line in FIG. 39 is in the form of a single chip. In this example, a p channel power MOS 201 is employed.

A switch 202 is connected with the device 200 for turning on and off the power MOS 201. In addition to the power MOS 201, the device 200 includes first and second control MOSFETs 203 and 204, a temperature sensing diode string 205 consisting of a plurality of diodes connected in series, a zener diode 206, resistors R.sub.1 and R.sub.2 and other components.

When the switch 202 is switched on, a low level signal is applied to he gate of the power MOS 201, and the power MOS 201 is turned on. In this case, the first control MOSFET 203 is turned on simultaneously with the power MOS 201 because the gates of both transistors are connected together. If we neglect the on resistance of the first control MOSFET 203, we can consider that a current flowing through the diode string 205 is determined by the resistance R.sub.1. At the thus-determined current value, each diode of the diode string 205 has a forward voltage V.sub.F1, and a voltage between both ends of the diode string 205 amounts to nV.sub.F1 where n is the number of the diodes of the diode string 205. Therefore, a gate source voltage of the second control MOSFET 204 is expressed as V.sub.Z -n.sub.V.sub.F1 where V.sub.Z is a zener voltage of the zener diode 206.

When the temperature is normal, the voltage V.sub.F1 is so high that the gate source voltage of the MOSFET 204 is lower than a threshold voltage V.sub.th of the MOSFET 204. That is, V.sub.th >(V.sub.Z -nV.sub.F1). Therefore, the second control MOSFET 204 remains off.

In the temperature sensing diode string 205, the forward voltage V.sub.F1 decreases with increase in temperature. Therefore, if the temperature of the chip increases abnormally because of an excessive increase in the voltage or current which the power MOS 201 handles, or by some other reason, then the gate source voltage V.sub.Z -nV.sub.F1 of the second control MOSFET 204 increases, and y exceeds the threshold voltage V.sub.th. For example, the gate source voltage V.sub.Z -nV.sub.F1 becomes higher than V.sub.th when the temperature reaches 150.degree. C. As a result, the second control MOSFET 204 is turned on, and causes the power MOS 201 to turn off by applying a high level signal to the gate of the power MOS 201. Thus, the protective device of this example protects the device against overheating.

The first control MOSFET 203 is turned off simultaneously with the powr MOS 201. Therefore, the current through the diode string 205 is decreased by being limited by the resistance R.sub.1 +R.sub.2. With this decrease of the current, the forward voltage of the diode string 205 is decreased to a lower value V.sub.F2, and the gate source voltage of the second control MOSFET 204 is increased from (V.sub.Z -nV.sub.F1) to (V.sub.Z -nV.sub.F2). Therefore, the on state of the second MOSFET 204 becomes more stable.

After a while, the chip temperature decreases, and accordingly, the forward voltage V.sub.F2 of the diode string 205 increases. When the chip temperature decreases to a sufficient low value (, for example, 110.degree. C.) at which the gate source voltage (V.sub.Z -nV.sub.F2) becomes lower than V.sub.th, then the second control MOSFET 204 turns off, so that the power MOS 201 is turned on again.

The first control MOSFET 203 is used for obtaining the characteristic of hysteresis. The first control MOSFET 203 adds the effect of temperature hysteresis by changing the current value through the diode string 205.

This conventional device employs MOSFETs as transistors for controlling the power MOS 201 in accordance with temperature. However, the threshold voltage V.sub.th of a MOSFET is difficult to control, and the dispersion of values of V.sub.th in fabrication is as wide as .+-.0.5 V. Therefore, it is difficult to accurately control the actuating temperature of the thermal protective circuit.

Another conventional example is disclosed in Electronics, June 28, 1984, pages 134-136. This example employs a comparator to improve the accuracy of temperature detection. However, the structure of this conventional device is so complicated and large-sized that the fabrication is not easy, and the cost and chip size are increased.

The fourteenth embodiment solves these problems by using the bipolar transistor structure shown in FIG. 21.

FIG. 33 shows an equivalent circuit of the fourteenth embodiment device 201. In this device, a bipolar transistor 208 is employed in place of the second control MOSFET 204 of FIG. 39. The diode 207 shown in FIG. 39 is removed, and a curent limiting resistor R.sub.3 is connected with the base of the bipolar transistor 208 because the threshold voltage of the bipolar transistor is low. In other respects, the device 201 is substantially the same as the conventional device of FIG. 39.

The device 201 is operated in the same manner as the conventional device 200 except that the function of the second control MOSFET 204 is performed by the bipolar transistor 208.

Unlike the conventional device 200, the fourteenth embodiment device 201 can improve the accuracy of the temperature value because it is easy to accurately control the threshold voltage of the bipolar transistor as compared with the MOSFETs, and the dispersion of the threshold voltage of the bipolar transistor is as small as several mV.

The bipolar transistor 208 has the structure shown in FIG. 21, so that the problem of a parasitic transistor can be solved as mentioned before. It is optional to employ either of the bipolar transistor structures shown in FIGS. 18 and 19A as the transistor 208 instead of the structure of FIG. 21.

FIG. 34 shows a variation of the fourteenth embodiment. In this example, an n channel MOS is used as the power MOS 201 instead of a p channel MOS.

Because the polarity of the power MOS is opposite to that of the device 201 shown in FIG. 33, a device 202 of FIG. 34 employs a bipolar transistor 209 of an opposite polarity in place of the bipolar transistor 208, and a MOSFET 210 of an opposite polarity in place of the MOSFET 203, and the circuit is arranged upside down. However, the device 202 is operated in an analogous manner, and has the same advantages. Because an n channel MOS is employed as the power MOS 201, it is possible to further reduce the chip size as compared with the p channel MOS device 201 of FIG. 33.