Complementary Current Mirror for Correcting Input Offset Voltage of Diamond Follower, Especially as Input Stage for Wide-Band Amplifier

A commonly used circuit structure is a "diamond follower". The diamond follower can be used as a differential input stage of a wide-band amplifier. FIG. 1 shows the basic diamond follower circuit. To use the diamond follower as a differential input stage, the collectors of transistors 6 and 8 are connected to complementary inputs of a push-pull output stage. When the diamond follower is used as in a differential input stage, terminal 2 of FIG. 1 is used as the +V.sub.IN terminal and terminal 3 is used as the -V.sub.IN terminal. It is well known that it is very desirable that a differential amplifier have a zero "input offset voltage". That is, when the amplifier output voltage is zero, the voltage difference between the differential input terminals also is zero. However, obtaining a zero input offset voltage for the diamond follower is difficult, because the base-to-emitter voltages (V.sub.BE 's) all need to be equal if the input offset voltage V.sub.OS is to be zero. The transistor V.sub.BE 's are determined by the equation V.sub.BE =V.sub.TH ln(I.sub.C /I.sub.S), where V.sub.TH =(kT/q), and k is Boltzman's constant, T is the junction temperature in degrees Kelvin, q is the electron charge, I.sub.C is collector current, and I.sub.S is saturation current. In a typical integrated circuit process, the NPN transistors such as 6 and 7 are fabricated using different critical processing steps from those used to construct the PNP transistors 5 and 8. In some cases the NPN transistors may be "vertical" devices while the PNP transistors may be "lateral" or "vertical" PNP devices. The "saturation current" of a transistor is a strong function of various processing parameters, including the doping levels on both sides of the emitter-base junction. The emitter-base junctions of the NPN transistors 6 and 7 are formed during entirely different process steps than the process steps forming the emitter-base junction of the PNP transistors 5 and 8. The saturation currents of the NPN transistors 6 and 7 are strongly dependent on the diffusion parameters of the N++ emitter diffusion, and the saturation currents of the PNP transistors 5 and 8 are unrelated to the N++ emitter diffusions. The contact potentials are inherently different for NPN transistors and PNP transistors because the contact potentials are a strong function of the saturation currents. This inherent difference in the contact potentials for NPN and PNP transistors results in inherent, large, somewhat uncontrollable variations in the input offset voltage of the diamond follower circuit of FIG. 1 when it is used as a differential input stage of an amplifier.

A known solution to the problem is to add diode-connected NPN transistors or PNP transistors in series with transistors 5, 6, 7, and 8 so that each NPN transistor emitter-base junction is always connected in series with a corresponding PNP transistor emitter-base junction. These solutions increase the amount of integrated circuit chip area required to implement an amplifier, and have a detrimental effect on circuit performance by adding noise and capacitance that usually results in poor frequency response for the amplifier.

There is a presently unmet need for a simple technique for reducing the input offset voltage of a diamond follower.

There is a presently unmet need for a simple technique for reducing the input offset voltage of an amplifier using a diamond follower as a differential input stage.

A wide variety of current mirror circuits are known. None of them have ever been utilized to compensate for input offset errors in a diamond follower stage used as a differential input stage of an amplifier.

Accordingly, it is an object of the invention to provide a complementary current mirror circuit.

It is another object of the invention to provide a simple, inexpensive technique for reducing the offset voltage in a diamond follower circuit.

It is another object of the invention to provide a simple, inexpensive technique for reducing the input offset voltage of an amplifier using a diamond follower circuit as a differential input stage.

Briefly described, and in accordance with one embodiment thereof, the invention provides a complementary current mirror circuit. In the described embodiment of the invention, a pair of complementary current mirrors are used as current sources for a diamond follower circuit stage. In one described embodiment, the complementary current mirror circuits adjust currents through a PNP transistor and an NPN transistor on one side of the diamond follower circuit in such a manner as to force the V.sub.BE voltages of those two transistors to equal the V.sub.BE voltages of an NPN transistor and a PNP transistor, respectively, on the other side of the diamond follower circuit, thereby providing zero input offset voltage. In another embodiment of the invention, a diamond follower is used as a differential input stage for a wide band amplifier. Bipolar and CMOS implementations of this embodiment are disclosed.

FIG. 1 is a schematic circuit diagram of a diamond follower circuit.

FIG. 2 is a schematic diagram illustrating a bias circuit including a pair of complementary current mirror circuits.

FIG. 3 is a simplified schematic circuit diagram of a wide-band amplifier utilizing the circuit of FIG. 2 as a bias circuit and utilizing a modified diamond follower circuit as a differential input stage.

FIG. 4 is a schematic diagram of a wide-band amplifier similar to that of FIG. 3 implemented using complementary field effect transistors.

Referring to FIG. 1, the basic diamond follower structure is shown. It includes a constant current source 10 through which a current I.sub.1 flows. Current source 10 is connected between +V.sub.S and conductor 23, which is connected to the base of NPN transistor 6 and the emitter of PNP transistor 5. The collector of transistor 6 is connected to +V.sub.S (although when the diamond follower circuit is used as a differential input stage of an amplifier, the collector of transistor 6 is connected to one input of a gain and output stage of the amplifier, and the collector of transistor 8 is connected to another input of the gain and output stage, as shown in FIG. 3). The collector of transistor 5 is connected to -V.sub.S, and its base is connected to conductor 2. Conductor 2 is also connected to the base of NPN transistor 7, the collector of which is connected to +V.sub.S. The emitter of transistor 7 is connected by conductor 24 to constant current source 12, through which a current I.sub.2 flows to -V.sub.S. Conductor 24 also is connected to the base of PNP transistor 8, the collector of which is connected to -V.sub.S. The emitter of transistor 6 and the emitter of transistor 8 are both connected to conductor 3. In FIG. 1, the emitter areas of transistors 6 and 8 are k times those of transistors 5 and 7.

It can be readily seen that the voltage between conductors 23 and 24 is equal to (1) V.sub.BE5 +V.sub.BE7 and (2) V.sub.BE6 +V.sub.BE8. It also can be readily seen that the offset voltage V.sub.OS is equal to V.sub.IN minus V.sub.OUT and that this is equal to either (1) V.sub.BE6 -V.sub.BE5 or (2) V.sub.BE7 -V.sub.BE8. Thus, the input offset voltages will be zero only if the V.sub.BE voltages of NPN transistors 6 and 7 is equal to that of the PNP transistors 5 and 8. As mentioned above, this often is not the case for monolithic integrated circuit implementations of the circuit.

In FIG. 2, the circuit is shown including a bias current source 21 producing a constant current I.sub.B which functions as a control current for a complementary current mirror circuit 10 and another complementary current mirror circuit 12 which, in accordance, with the present invention, can be used to implement current sources 10 and 12 in the diamond follower circuit of FIG. 1. Complementary current mirror circuit 10 includes a NPN transistor 16 having its collector and base connected to +V.sub.S and its emitter connected to conductor 17 and to bias current circuit 21. Conductor 17 also is connected to the base of PNP transistor 15, which has its emitter connected to +V.sub.S and its collector connected to conductor 23. The current I.sub.1 flows through transistor 15, as indicated by arrow 10A. Complementary current mirror circuit 12 includes diode-connected PNP transistor 25, which has its collector and base connected to -V.sub.S and its emitter connected by conductor 22 to bias current source 21 and to the base of NPN transistor 20. The emitter of transistor 20 is connected to -V.sub.S and its collector is connected to conductor 24. The current I.sub.2 flows through transistor 20, as indicated by arrow 12A.

In accordance with the present invention, the bias circuit of FIG. 2 provides currents I.sub.1 and I.sub.2 with amplitudes that vary as a function of the saturation currents I.sub.S for the NPN transistors and PNP transistors in such a manner that the value of I.sub.1 flowing through PNP transistor 5 causes its V.sub.BE voltage to be equal to that of NPN transistor 6 even though their contact potentials and normalized saturation currents are different. The circuit of FIG. 2 also causes I.sub.2 to have a value that causes the V.sub.BE voltage of NPN transistor 7 to be equal to the V.sub.BE voltage of PNP transistor 8, even though their contact potentials and normalized saturation currents are different as a result of processing parameter variations.

The following analysis, including equations (1) through (12) for the circuit of FIG. 1 establishes the requirements for I.sub.1 and I.sub.2 if the V.sub.BE voltages of the PNP transistors and the NPN transistors in FIG. 1 are to be equal despite differences in their saturation currents or contact potentials.

The input offset voltage V.sub.OS for the circuit of FIG. 1 is given by equation

Thus, it can be seen that V.sub.OS is given by each of the two following equations

When V.sub.OS is set equal to 0, equation (1.1) leads to equation ##EQU1## and equation (1.2) leads to equation ##EQU2##

The saturation current I.sub.S (NPN) for NPN transistors and the saturation current I.sub.S (PNP) for PNP transistors are related by the ratio m, which can vary from batch to batch and wafer to wafer in the manufacture of integrated circuits. However, m is usually very uniform across a particular integrated circuit. The following equation relates the saturation currents in the circuit of FIG. 1: ##EQU3##

Equation (2) leads to equation ##EQU4##

Equation (3) leads to equation ##EQU5##

From equation (5), it can be seen that ##EQU6## and from equation (6), it can be seen that ##EQU7##

Since the emitter area of transistors 6 and 8 is k times that of transistors 7 and 5, it can be seen that from equation (7)

and from equation (8), it can be seen that ##EQU8## Where k is defined to be I.sub.S8 divided by I.sub.S5 equations (9) and (10) lead to equations (11) and (12), respectively ##EQU9##

Thus, it is seen that for zero offset voltage the diamond follower circuit of FIG. 1 requires current sources 10 and 12 to supply currents I.sub.1 and I.sub.2 given by equations (11) and (12), respectively, where m is the ratio of saturation currents of NPN transistors and PNP transistors, and k is the ratio between the emitter area of transistors 6 or 8 to that of transistor 7 or 5, respectively.

Equations (13)-(20) show a similar analysis for the current source circuit of FIG. 2. The current I.sub.1 flowing through PNP transistor 15 is given by the equation ##EQU10## where I.sub.S 15 is a saturation current of transistor 15 and V.sub.BE 16 is the magnitude of the base-to-emitter voltage of NPN transistor 16. Similarly, the equation for the current I.sub.2 flowing through NPN transistor 20 is given by equation ##EQU11## where V.sub.TH is equal to kT divided by q.

The equation for V.sub.BE16 as a function of I.sub.B is given by equation ##EQU12## and the voltage V.sub.BE25 is given by equation ##EQU13##

Substituting equation (15) into equation (13) gives equation ##EQU14## and substituting equation (16) into equation (14) gives equation ##EQU15##

Substituting m for the ratio I.sub.S16 /I.sub.S15 in equation (17) leads to equation ##EQU16##

Similarly, substituting m for the ratio I.sub.S20 /I.sub.S25 leads to equation

The above relationships between I.sub.1, I.sub.2, I.sub.B and m are exactly what is required by the diamond follower circuit of FIG. 1 in order to produce the input offset voltage V.sub.OS equal to zero, as explained above. Also, the current I.sub.0 is exactly k multiplied by I.sub.B.

The following describes a feature of scaling that can be accomplished with the complementary current mirror circuit of FIG. 2. If it is assumed that the emitter areas of transistors 15 and 20 are scaled by a factor x relative to transistors 16 and 25, respectively, i.e., if I.sub.S15 =xI.sub.S25 and I.sub.S20 =xI.sub.S16, then the analysis of this scaling effect can be understood from the following equations: ##EQU17##

From equation (21), it can be seen that the output currents I.sub.1 and I.sub.2 are given by the following equations: ##EQU18##

Substituting equation (4), which defines m=(I.sub.S (NPN))/(I.sub.S (PNP)), leads to the equations ##EQU19##

If we compare equations (23) and (24) with equations (19) and (20), respectively, it is apparent that the only difference is that the bias current I.sub.B is scaled by the factor x. This means that the bias current source can be kept at a low level, thus minimizing the power dissipation of the complementary current mirror.

The diamond follower circuit often is used as a line driver. FIG. 3 shows another common use of a diamond follower. In FIG. 3, the diamond follower circuit of FIG. 1 is biased by the complementary current mirror circuit of FIG. 2 to provide I.sub.1 and I.sub.2, with bias control circuitry 21 supplying the bias current I.sub.B to the complementary current mirror control transistors 16 and 25. The collector 6A of transistor 6 is connected by a resistor 33, which may be 1200 ohms, to +V.sub.S and also is connected directly to the base of a PNP pullup transistor contained in output stage 32. The collector 8A of transistor 8 is connected by a resistor 34, which may be 1200 ohms, to -V.sub.S and also is connected to the base of an NPN pulldown transistor in output stage 32. Details of the bias circuit 21 and the operation of the PNP current mirror circuit connecting output stage 32 to +V.sub.S and the NPN current mirror circuit connecting output stage 32 to -V.sub.S are described in detail in commonly assigned co-pending application "WIDE-BAND AMPLIFIER WITH CURRENT MIRROR FEEDBACK TO BIAS CIRCUIT", Ser. No. 223,796, filed on July 25, 1988, by Anthony D. Wang and R. M. Stitt II, and incorporated herein by reference. Of course, the diamond follower circuit with the complementary current sources as shown in FIG. 3 can be used in conjunction with conventional techniques for limiting the current in the output transistors, rather than the current mirror feedback structure shown in FIG. 3.

Thus, the output of the bias control circuitry I.sub.B causes the NPN/PNP current mirrors 10 and 11 to provide the appropriate bias currents to force the +V.sub.IN and -V.sub.IN conductors to the same potential. Also, the current I.sub.0 in transistors 6 and 8 is controllably scaled to I.sub.B. Often, current scaling can easily be accomplished, where advantageous, by controlling the area ratios of transistors 16 and 15 and of transistors 25 and 20.

The circuit shown in FIG. 3 can be modified, if desired, to include a diode-connected NPN or PNP transistor or other voltage source, rather than a short circuit between the base of transistor 16 and V.sub.S. The emitter of the diode-connected transistor can be connected to the base of transistor 16 and the base and collector can be connected to +V.sub.S. Similarly, a diode-connected NPN or PNP transistor can replace the short circuit between the base of transistor 25 and -V.sub.S. In this case, the emitter of the diode-connected PNP transistor is connected to the base of transistor 25 and the collector and base thereof are connected to -V.sub.S. Such diode-connected transistors minimize base width modulation of transistors 16 and 25 to cause them to more closely match the operating conditions of the transistors 7 and 5, respectively, neither of which operates with zero collector-to-base bias voltage. Any voltage drop between the collector and base of transistors 16 and 25, such as results from adding the above-mentioned diode-connected transistors, increases the current which transistors 16 and 25 can carry before they go into saturation due to internal resistive voltage drops. Also, degeneration resistors can be connected in series with the emitters of transistors 15, 16, 5, 6, 7, 8, 20, and 25 to temper the exponential variation of bias currents from the complementary NPN/PNP current mirrors when the saturation currents of the NPN transistors and the PNP transistors differ from each other. Use of the degeneration resistors does not reduce the input offset voltage quite as effectively as the circuit shown in FIG. 3, but reduces bias current variation in transistors 5 and 7, which is desirable because the frequency responses of transistors 5 and 7 are somewhat dependent on their emitter currents, and a sufficient bias current difference will cause distortion in the frequency of response of the amplifier.

The above-described circuit technique, using a complementary current mirror to generate the current necessary to match V.sub.BE voltages of dissimilar transistors or the like, allows the designer of wide-band voltage buffers and transimpedance amplifiers to come one step closer to the ideal of zero offset voltage without requiring tighter control of integrated circuit manufacturing processes to equalize PNP and NPN saturation currents. The above circuit techniques decrease the processing complexity, since no attention need be paid to trying to target I.sub.S (NPN) and I.sub.S (PNP) to be equal or nearly equal. The described circuit techniques also increase manufacturing yields since the input offset voltage will no longer be subject to the variation that could eliminate entire wafers within a processed lot or even eliminate a number of wafer lots.

It should be noted that the present invention is not limited to just use of a diamond follower stage. There are likely to be many situations wherein it would be desirable to achieve control of "mixed device" terminal currents and voltages. Nor is it necessary that the transistors be bipolar. The concepts explained above will work if the NPN transistors and PNP transistors are replaced with N channel MOSFETS and P channel MOSFETS, respectively, as shown in the schematic diagram of FIG. 4, which shows a MOSFET implementation of the circuit of FIG. 3. The "body" electrodes of the MOSFETs should be connected to their source electrodes to avoid body-to-source voltage difference from increasing the MOS threshold voltages. This could be accomplished if dielectrically isolated (DI) substrates are used. In FIG. 4, the currents I.sub.B and I.sub.1 are given by the equations

Equation (26) leads to ##EQU20## Equation (27) leads to ##EQU21## Since ##EQU22## this leads to ##EQU23## where .mu..sub.n and .mu..sub.p are the n channel and p channel mobilities, respectively, W/L is the channel width-to-length ratio of the MOSFET under consideration, V.sub.TN and V.sub.TP are the p channel and n channel MOSFET threshold voltages, respectively, and C.sub.OX is the normalized gate capacitance of the MOSFET under consideration. Equation (30) gives a value of I.sub.1 that is related to the "parametric" difference between the P channel and N channel threshold voltages, and may be useful for compensating characteristics other than V.sub.OS for various CMOS circuits other than diamond followers for variations in one or both of these threshold voltages.

The offset voltage of the diamond follower circuit can be adjusted in ways other than using complementary mirror circuits in the manner described above. For example, I.sub.1 and I.sub.2 can be varied by trimming conventional current sources. I.sub.1 and I.sub.2 could be produced by any of a variety of controlled current source circuits that uses a complementary current mirror to generate a control signal. Alternately, feedback from the output of an amplifier might be used to adjust the bias currents fed into bias input terminals 23 and 24.

By way of definition, a base, emitter, and collector of a transistor can be regarded as its control electrode, first current carrying electrode, and second current carrying electrode, respectively. The gate, source, and drain of a MOSFET can be regarded as its control electrode, first current carrying electrode, and second current carrying electrode, respectively.

While the invention has been described with reference to a particular embodiment thereof, those skilled in the art will be able to make various modifications to the described embodiment without departing from the true spirit and scope of the invention.