Multimode Expanded Memory Space Addressing System Using Independently Generated DMA Channel Selection and DMA Page Address Signals

1. A computer comprising: a central processing unit; a computer address modification system receiving memory address signals, DMA channel selection signals and memory address signals and selectively outputting translated memory address signals and DMA page address signals in response thereto: a CPU address bus coupled to the central processing unit, to the computer address modification system and through a first gate to a system address bus; a main memory; A DMA controller that is operates during a DMA cycle to provide a plurality of direct memory access address signals; an interrupt controller; a system address bus providing addresses to the main memory; a DMA address bus coupled to receive address signals from the DMA controller, the DMA address bus being coupled through a second gate to the system which address bus and to an output for a plurality of address signals from the computer address modification system which correspond to a most significant plurality of the address signals from the DMA controller; a local I/O bus coupled to communicate information with I/O devices including the DMA controller and the interrupt controller and with the computer address modification system; a system data bus coupled to the main memory; a CPU data bus coupled to communicate data with the central processing unit and with the compute address modification system; a third gate coupling the CPU data bus to the system data bus; a fourth gate coupling the system data bus to the local I/O bus; a latch coupled to receive and store data from the local I/O bus including address signals which correspond to said most significant plurality of the address signals from the DMA controller; a DMA extension bus coupled to transfer the address signlas stored by the latch which correspond to said most significant plurality of the address signals from the DMA controller to the computer address modification system; a fifth gate coupling the DMA extension bus to corresponding signals on the CPU address bus; a translated address bus receiving translated address signals from the computer address modification system and coupling the translated address signals to the main memory; a sixth gate coupling signals from the translated address bus which correspond to said most significant plurality of the address signals form the DMA controller to corresponding signals of the DMA address bus; and a seventh gate coupling the translated address bus to the system address bus.

2. A computer system comprising: a central processing unit having address and data terminals; a data store storing information including instructions that are executable by the central processing unit, the data store being addressable in response to first, second and third groups of encoded address signals; a DMA controller circuit providing address signals comprising the first and second groups during a direct memory access operation; a DMA address latch coupled to receive and store the second group of address signals and a portion of the first group of address signals; a DMA address bus coupled to receive the first and second groups of address signals provided by the DMA controller circuit and communicate the first and second groups of address signals to the data store; an input/output controller generating the third group of address signals during a direct memory access operation; a DMA extension bus coupled to receive the second group of address signals from the DMA address latch during a direct memory access operation; A CPU address bus coupled to receive the first, second and third groups of address signals from the central processing unit during a central processing unit operation and to receive the third group of address signals form the input/output controller during a direct memory access operation; a first writeable register storing a map enable signals indicating whether or not translation of address signals appearing on a CPU address bus is enabled; a second writeable register storing a page enable signal indicating whether or not paging of DMA addresses during a direct memory access operation is enabled; a first gate that operates during a direct memory access operation when the page enable signal indicates that paging of DMA addresses during a direct memory access operation is not enabled to couple the second group of address signals from the DMA extension bus to the CPU address bus; a translated address bus communicating the second and third groups of addresses to the data store; a second gate that operates during a direct memory access operation when the page enable signal indicates that paging of DMA addresses during a direct memory access operation is not enabled to couple the second group of signals from the translated address bus to the DMA address bus; a computer address modification system receiving first, second and third groups of addresses at address input terminals from a CPU address bus, receiving data at data input terminals, receiving the second group of address signals from the DMA extension bus during a direct memory access operation, and receiving direct memory access channel identification information at DMA channel identification input terminals, the computer address modification system including a mapping store storing a plurality of translation addresses and a page store storing a plurality of direct memory access page addresses, the computer address modification system selectively transferring an address received from the CPU bus or a translated address to the translation address bus in accordance with a state of the map enable signal with translation being inhibited during a direct memory access operation when the page enable signal enables paging; and a data bus circuit providing communication of data information among the central processing unit data terminals, the data store and the address modification system data input terminals.

3. A computer system according to claim 2 further comprising an interrupt controller generating an interrupt request upon an occurrence of an interrupt and placing an interrupt vector type upon the data bus circuit upon acknowledgement of an interrupt request by the central processing unit, the computer address modification system including an interrupt detection circuit inhibiting translation of received address signals while an interrupt response routine is being processed.