Scanning Pulse Generating Circuit

1. Field of the Invention:

The present invention relates to a scanning pulse generating circuit composed mainly of MOS transistors and suitable for use in, for example, solid-state imaging devices.

2. Description of the Related Art:

FIG. 1A shows a known scanning pulse generating circuit which drives pixels of a solid-state imaging device. This circuit has a plurality of basic circuits each composed of a two-stage inverter comprising a first-stage inverter composed of MOS transistors Q.sub.12 and Q.sub.13 and a second-stage inverter composed of MOS transistors Q.sub.15 and Q.sub.16, and a pair of signal transmitting MOS transistors Q.sub.11 and Q.sub.14. The basic circuits 11.sub.-1, 11.sub.-2, 11.sub.-3, . . . are connected in a cascade manner and output terminals 12.sub.-1, 12.sub.-2, 12.sub.-3, . . . are led from the connections between adjacent stages of the cascade.

In operation, a start pulse ST (see FIG. 1B) is input to the signal transmitting transistor Q.sub.11. At the same time, clock pulses .phi..sub.11 and .phi..sub.12 are input to the signal transmitting transistors Q.sub.11 and Q.sub.14. The start pulse ST is delayed by a time corresponding to the period of the clock pulse .phi..sub.12 so that output pulses V.sub.01, V.sub.02, V.sub.03, . . . are derived from the output terminals 12.sub.-1, 12.sub.-2, 12.sub.-3, . . . of the basic circuits 11.sub.-1, 11.sub.-2, 11.sub.-3, . . . of the respective stages, as shown in FIG. 1B.

Each of the MOS transistors used in the scanning pulse generating circuit of FIG. 1A is of the N-channel type. A symbol V.sub.DD repesents positive D.C. source voltage, while V.sub.SS represents grounding voltage. Symbols V.sub.11, V.sub.12 and V.sub.13 appearing in FIG. 1B represent the input voltage waveform of the first-stage inverter circuit, output voltage waveform of the first-stage inverter circuit and the input voltage waveform of the second-stage inverter circuit.

This known scanning pulse generating circuit is advantageous in that the operational margin of the scanning pulse generating circuit is high and in that the wiring interconnecting the circuit elements is suitable for attaining a higher density of the circuit arrangement. Unfortunately, however, this known scanning pulse generating circuit suffers from the following disadvantages.

(1) The voltage of the "H" level of the output signal from the basic circuit of each stage is affected by a fluctuation in the threshold voltage of the load transistor Q.sub.16 incorporated in the second-stage inverter of the basic circuit of the same stage, so that the basic circuits of different stages provide different levels of output signal.

(2) The voltage of the "H" level of the output signal is considerably lowered from the level of the D.C. source voltage V.sub.DD.

(3) Either one of the two stages of inverter is operative to conduct the inverting operation in all the basic circuits so that electric current is continuously supplied to all basic circuits, whereby the power consumption is increased. This poses a serious problem particularly when a multiplicity of stages of basic circuit, e.g., several hundreds of stages, are employed as in the case of the scanning circuit for a solid-state imaging device.

Using Complementary MOS transistors (referred to as CMOS hereinafter), a scanning pulse generating circuit is obtainable which is capable of operating at high speed with reduced power consumption and which can produce an "H" output level which is substantially the same as the source voltage, i.e., without a substantial drop in the voltage supplied from the source.

However, production of a scanning pulse generating circuit using CMOS transistors arranged in the form of an integrated circuit inconveniently requires a specific production process for forming CMOS transistors and the production process is inevitably complicated. Preferably, the scanning pulse generating circuit is constituted solely by N-channel MOS transistors or P-channel MOS transistros depending on whether the outputs to be obtained are of positive or negative voltage.

Accordingly, an object of the present invention is to provide a scanning pulse generating circuit which can provide output voltage at a constant level without substantial voltage drop, thereby to overcome the above-described problems of the prior art.

Another object of the present invention is to provide a scanning pulse generating circuit in which the basic circuit of each stage can easily be made up of a reduced number of elements and in which the power consumption is appreciably decreased.

To these ends, according to an aspect of the present invention, there is provided a scanning pulse generating circuit comprising: (a) a plurality of first basic circuits each including: a first MOS transistor with the gate terminal thereof serving as an input terminal; a second MOS transistor connected in series to the first MOS transistor with one of the main electrodes thereof being grounded while the gate terminal thereof being capable of receiving a first synchronizing pulse; a third MOS transistor having the gate terminal thereof connected to the point of juncture between the first and second MOS transistors while one of the main electrodes thereof being connected to a power supply; a fourth MOS transistor connected in series to the third MOS transistor with one of the main electrodes thereof being grounded while the gate terminal thereof being capable of receiving a second synchronizing pulse; and a first capacitive element connected between the point of juncture between the first and second MOS transistors and the point of juncture between the third and fourth MOS transistors, the point of juncture between the third and fourth MOS transistors constituting an output terminal; and (b) a plurality of second basic circuits each including: fifth, sixth, seventh and eighth MOS transistors corresponding to the first, second, third and fourth MOS transistors of the first basic circuit, respectively; and a second capacitive element corresponding to the first capacitive element; the fifth, sixth, seventh and eighth MOS transistors and the second capacitive element being connected in the same manner as the corresponding elements in the first basic circuit, the output terminal of the first basic circuit being connected to the gate terminal of the fifth MOS transistor, the gate terminals of the sixth and eighth MOS transistors being capable of receiving third and fourth synchronizing pulses, respectively; the first and second basic circuits being connected alternatingly in a multiplicity of stages so that scanning pulses are derived from the output terminals of the basic circuits of the successive stages.

According to another aspect of the present invention, there is provided a scanning pulse generating circuit comprising: (a) a plurality of first basic circuit each including: a first MOS transistor having an input terminal constituted by one of the main electrodes thereof while the gate terminal thereof being capable of receiving a first synchronizing pulse; a second MOS transistor with the gate terminal thereof connected to the other of the main electrodes of the first MOS transistor and with one of the main electrodes thereof connected to a power supply; a third MOS transistor connected in series to the second MOS transistor with one of the main electrodes thereof being grounded while the gate terminal thereof is capable of receiving a second synchronizing pulse; and a first capacitive element connected between the gate terminal of the second MOS transistor and the point of juncture between the second and third MOS transistors, the point of juncture between the second and third MOS transistors serving as an output terminal; and (b) a plurality of second basic circuits each including: fourth, fifth and sixth MOS transistors corresponding to the first, second and third MOS transistors of the first basic circuit, respectively; and a second capacitive element corresponding to the first capacitive element of the first basic circuit; the fourth, fifth and sixth MOS transistors and the second capacitive element being connected in the same manner as the corresponding elements of the first basic circuit, the output terminal of the first basic circuit being connected to one of the main electrodes of the fourth MOS transistor, the gate terminals of the fourth and sixth MOS transistors being capable of receiving third and fourth synchronizing pulses, respectively; the first and second basic circuits being connected alternatingly in a multiplicity of stages so that scanning pulses are successively output from the output terminals of the basic circuits of the successive stages.

Thus, in the scanning pulse generating circuit according to the present invention, voltage drop is completely eliminated by virtue of the bootstrap effect which is realized by the capacitance of the capacitive element determined to be suitably greater than the parasitic capacitance. This arrangement ensures that all the basic circuits can produce "H" outputs of substantially equallevels. In addition, power consumption is remarkably reduced because only one basic circuit conducts the inverting operation at any moment. It is also to be pointed out that the pitch of arrangement of the basic circuits, i.e., the distance between adjacent basic circuits, can be reduced owing to the reduced number of elements of the basic circuit.

FIG. 1A is a circuit diagram showing the construction of a conventional scanning pulse generating circuit;

FIG. 1B is a chart showing signal waveforms and voltage waveforms, illustrative of the operation of the scanning pulse generating circuit of FIG. 1A;

FIG. 2A is a circuit diagram showing the construction of a bootstrap type inverter incorporated in the scanning pulse generating circuit according to the present invention;

FIG. 2B is a voltage waveform chart illustrative of the operation of the bootstrap type inverter shown in FIG. 2A;

FIG. 3A is a circuit diagram showing the construction of a first embodiment of the scanning pulse generating circuit in accordance with the present invention;

FIG. 3B is a chart showing signal waveforms and voltage waveforms illustrative of the operation of the embodiment shown in FIG. 3A;

FIG. 4 is a diagram showing the construction of a second embodiment of the present invention;

FIG. 5A is a circuit diagram showing the construction of a third embodiment of the scanning pulse generating circuit in accordance with the present invention; and

FIG. 5B is a chart showing signal waveforms and voltage waveforms illustrative of the operation of the embodiment shown in FIG. 5A.

Before commencing the description of embodiments, a description will be made of the principle of a bootstrap type inverter employed in the scanning pulse generating circuit according to the present invention. Referring to FIG. 2A, which is a circuit diagram illustrating the bootstrap type inverter comprising N-channel MOS transistors, the gate terminal of a driver transistor Q.sub.1 serves as an input terminal 1, while the source terminal of this transistor is connected to a grounding terminal. A load transistor Q.sub.2 connected in series to the driver transistor Q.sub.1 has a drain terminal which is supplied with a source voltage V.sub.DD. An output terminal 2 is led from the juncture between both transistors Q.sub.1 and Q.sub.2. A third transistor Q.sub.3 is connected between the gate terminal and the drain terminal of the load transistor Q.sub.2. A feedback capacitor C.sub.1 is connected between the gate terminal and the source terminal of the load transistor Q.sub.2.

The third transistor Q.sub.3 cooperates with the feedback capacitor C.sub.1 so as to boost the voltage at the point 3 of juncture between the feedback capacitor C.sub.1 and the load transistor Q.sub.2, i.e., the voltage V.sub.0 at the gate terminal of the load transistor Q.sub.2. Parasitic capacitance at the juncture point 3 with respect to the ground potential is represented by C.sub.2.

The capacitance of the feedback capacitor C.sub.1 is so determined that the parasitic capacitance C.sub.2 and the capacitance of the feedback capacitor C.sub.1 normally meet the condition of C.sub.1 /(C.sub.1 +C.sub.2)>about 0.6. The parasitic capacitance at the output terminal 2 is represented by C.sub.L.

The operation of the bootstrap type inverter will be described with reference to FIG. 2B which shows waveforms of voltages at the input terminal 1, output terminal 2 and the juncture point 3. At a moment t.sub.1, the input voltage V.sub.in at the input terminal 1 takes the "H" level. In this state, the voltage V.sub.0 at the juncture point 3 is determined by the following formula (1) and is lower than the source voltage V.sub.DD.

In this formula (1), a symbol V.sub.T represents the threshold voltage of the MOS transistor, while .DELTA.V.sub.T is given by the following equation. ##EQU1## where, K is a value given by: ##EQU2## wherein, .phi..sub.F : Fermi potential of the transistor substrate or P-type well

N.sub.A : acceptor density of substrate

.epsilon..sub.0 : dielectric constant of vacuum

K.sub.s : specific dielectric constant of substrate

C.sub.ox : electrostatic capacitance of gate oxide film

Meanwhile, the voltage V.sub.out (t.sub.1) at the output terminal 2 is at the "L" level which is almost equal to zero as determined by the following formula (2).

Symbols g.sub.m (Q.sub.1) and g.sub.m (Q.sub.2) represent conductance values of the transistors Q.sub.1 and Q.sub.2.

When the input voltage V.sub.in is lowered to the "L" level, the driver transistor Q.sub.1 cuts off so that the output terminal voltage V.sub.OUT starts to rise because of the operation of the load transistor Q.sub.2 which is always conductive. Simultaneously, the voltage V.sub.0 at the juncture point 3 also rises due to the capacitive couping of the feedback capacitor C.sub.1 to satisfy the condition of V.sub.0 >V.sub.DD thereby switching off the enhancement type transistor Q.sub.3, so that the voltage V.sub.0 continues to rise until the voltage increment .DELTA.V.sub.0 reaches a value which is given by the following formula (3).

where, V.sub.out (t.sub.2) represents the voltage of the "H" level output obtained at a moment t.sub.2.

If the capacitance of the feedback capacitor C.sub.1 is determined to be suitably greater than the parasitic capacitance C.sub.2, the condition expressed by the following formula (4) is satisfied.

When the condition of formula (4) is met, the load MOS transistor Q.sub.2 operates in unsaturated condition so that it directly transmits the drain voltage V.sub.DD to the source terminal, so that the output terminal voltage V.sub.OUT (t.sub.2) derived from the source terminal becomes equal to the source voltage V.sub.DD.

A description will be given hereinunder as to shift-register type scanning pulse generating circuits embodying the present invention and incorporating the operation principle of the bootstrap type inverter described hereinabove.

Referring to FIG. 3A showing the circuit of a first embodiment, the basic circuit 21.sub.-1 of a first stage has four MOS transistors Q.sub.D1, Q.sub.L1, Q.sub.B1 and Q.sub.R1 and a capacitor C.sub.F. The MOS transistors Q.sub.D1, Q.sub.L1 and Q.sub.B1 perform operations equivalent to the operation performed by the MOS transistors Q.sub.1, Q.sub.2 and Q.sub.3 of the bootstrap inverter shown in FIG. 2A. First and second MOS transistors Q.sub.D1 and Q.sub.L1, which are connected in series, constitute an inverter circuit in which the second transistor Q.sub.L1 serves as the load transistor while the first transistor Q.sub.D1 functions as the driver transistor. This inverter circuit is connected between the power supply V.sub.DD and the earth terminal.

The capacitor C.sub.F is composed of a MOS diode and corresponds to the feedback capacitor C.sub.1 in the bootstrap inverter shown in FIG. 2A. This capacitor C.sub.F is connected between the juncture point between the MOS transistors Q.sub.D1 and Q.sub.L1 and the gate terminal of the MOS trtansistor Q.sub.L1. A symbol C.sub.S represents the parasitic capacitance corresponding to C.sub.2 of the bootstrap inverter shown in FIG. 2A. A fourth MOS transistor Q.sub.R1 is used as a resetting transistor and is connected between the earth terminal and the source terminal of the third MOS transistor Q.sub.B1 which functions as a biasing transistor. The source terminal of the third MOS transistor Q.sub.B1 is connected to the gate terminal of the load transistor Q.sub.L1.

The gate terminal of the third MOS transistor Q.sub.B1 receives the start pulse ST, while the gate terminals of the driver transistor Q.sub.D1 and the fourth MOS transistor Q.sub.R1 receive, respectively, synchronizing pulses .phi..sub.2 and .phi..sub.4.

An output terminal 22.sub.-1 is led from the point of juncture between the MOS transistors Q.sub.D1 and Q.sub.L1 which constitute the inverter circuit.

A basic circuit 21.sub.-2 of the second stage has a construction identical to that of the basic circuit 21.sub.-1 of the first stage, except that it receives different synchronizing pulses. Namely, the basic circuit 21.sub.-2 of the second stage has MOS transistors Q.sub.L2, Q.sub.D2, Q.sub.B2 and Q.sub.R2, which correspond to the MOS transistors Q.sub.L1, Q.sub.D1, Q.sub.B1 and Q.sub.R1, and a feedback capacitor C.sub.F and a parasitic capacitance C.sub.S. The output terminal 22.sub.-1 of the basic circuit of the first stage is connected to the gate terminal of the MOS transistor Q.sub.B2 so that the output from the basic circuit 21.sub.-1 of the first stage is input to the basic circuit 21.sub.-2 of the second stage. The gate terminals of the driver transistors Q.sub.D2 and the fourth MOS transistor Q.sub.R2 receive synchronizing pulses .phi..sub.1 and .phi..sub.3, respectively. The basic circuits 21.sub.-1 and 21.sub.-2 of the first and second stages having the described constructions are connected alternately in a cascade-like manner so as to constitute a scanning pulse circuit.

The operation of this scanning pulse generating circuit will be described with reference to FIG. 3B which illustrates waveforms of pulses applied to various portions of the circuit shown in FIG. 3A and the waveforms of voltages obtained at the respective juncture points and output terminals. The description will be made on the assumption that all the MOS transistors are of the N-channel type.

At a moment t.sub.1, the start pulse ST applied to the gate terminal of the third MOS transistor Q.sub.B1 of the first stage basic circuit 21.sub.-1 is changed to "H" level, so that the voltage V.sub.1 at the source terminal of the transistor Q.sub.B1 rises to V.sub.A as a result of supply of the drain current. The conductance values g.sub.m (Q.sub.L1) and g.sub.m (Q.sub.D1) of the MOS type transistors Q.sub.L1 and Q.sub.D1 are determined beforehand so as to meet the following condition.

where, V.sub.T represents the threshold voltage of the MOS transistor.

Under the condition described, the voltage V.sub.01 obtained at the output terminal of the inverter circuit composed of the transistors Q.sub.L1 and Q.sub.D1 remain at a level V.sub.C which is lower than the threshold voltage V.sub.T, even when the gate terminal of the load transistor Q.sub.L1 receives a voltage V.sub.A higher than the threshold voltage V.sub.T while the gate terminal of the driver transistor Q.sub.D1 receives the synchronizing pulse .phi..sub.2 of the voltage level "H" higher than the threshold voltage V.sub.T.

At a moment t.sub.2, the level of the synchronizing pulse .phi..sub.2 is changed to "L" so that the driver transistor Q.sub.D1 is turned off with the result that the voltage V.sub.01 at the output terminal is raised due to the supply of the drain current from the load transistor Q.sub.L1. Partly because of the rise of the output terminal voltage V.sub.01 and partly because of the operation of the feedback capacitor C.sub.F, the voltage V.sub.1 at the gate terminal of the load transistor Q.sub.L1 is incremented by .DELTA.V.sub.1 which is given by the following formula (6). ##EQU3## where, V.sub.01 represents the voltage obtained at the output terminal when the voltage V.sub.1 (.tbd.V.sub.B) after the increment of the voltage is applied to the gate terminal of the load transistor Q.sub.L1.

It is possible to obtain the condition V.sub.01 (V.sub.1 =V.sub.B)= V.sub.DD, by making the capacitance of the feedback capacitor C.sub.F to be suitably greater than the parasitic capacitance C.sub.S connected to the gate terminal of the load transistor Q.sub.L1. The manner in which the voltage at the gate terminal of the load transistor Q.sub.L1 rises is the same as that in the bootstrap inverter explained before in connection with FIGS. 2A and 2B.

The voltage V.sub.01 derived from the output terminal of the first stage is held at the "H" level for the period between the moment t.sub.2 and a moment t.sub.3 so that the biasing MOS transistor Q.sub.B2 of the second-stage basic circuit 21.sub.-2 receiving this output voltage V.sub.01 is held on. As a result, the source terminal voltage V.sub.2 of the transistor Q.sub.B2 is raised and set at the voltage V.sub.A and this voltage V.sub.A is maintained even after the moment t.sub.3.

At the moment T.sub.3, the driver transistor Q.sub.D1 of the first-stage basic circuit 21.sub.-1 is turned on because the synchronizing pulse .phi..sub.2 is switched to "H" level at this moment. As a result, the output terminal voltage V.sub.01 starts to fall. In consequence, the drain terminal voltage V.sub.1 of the MOS transistor Q.sub.R1 of the first-stage basic circuit 21.sub.1 tends to come down. Simultaneously with the start of the fall of the output terminal voltage V.sub.01 or, alternatively, after the elapse of a predetermined time from the moment of the start of the fall of the output terminal voltage, the synchronizing pulse .phi..sub.4 is switched to "H" level so that the MOS transistor Q.sub.R1 is turned on, whereby the voltage V.sub.1 is forcibly reduced to the level of the ground potential. This in turn causes the load transistor Q.sub.L1 to be turned off so that the output terminal voltage V.sub.01 is lowered to the ground potential.

At the moment t.sub.2, the output terminal voltage V.sub.01 of the first-stage basic circuit 21.sub.-1, now switched to "H" level, is input so that the second-stage basic circuit 21.sub.-2, in which the source terminal voltage V.sub.2 of the MOS type transistor Q.sub.B2 has been set at V.sub.A, operates in accordance with the timing of the synchronizing pulses .phi..sub.1 and .phi..sub.3 in the chart of FIG. 3B, in the same manner as the first-stage basic circuit 21.sub.-1. That is, the second-stage basic circuit 21.sub.-2 produces an output voltage V.sub.02 of the same level as the source voltage V.sub.DD at a moment t.sub.4 at which the synchronizing pulse .phi..sub.1 is switched to "L" level, as will be seen from FIG. 3B.

In this manner, output voltages V.sub.03, . . . are successively output from the output terminals 22.sub.-3 . . . of the basic circuits 21.sub.-3 . . . of the successive stages, in the period t.sub.p between the moment at which the synchronizing pulse .phi..sub.2 falls and the moment at which the synchronizing pulse .phi..sub.1 falls.

FIG. 4 shows the circuit arrangement used in a second embodiment of the present invention. In this Figure, the same reference numerals are used to denote the same parts or members as those used in the first embodiment shown in FIG. 3A. The circuit arrangement in the second embodiment is materially the same as that of the first embodiment except that the drain terminals of the third MOS transistors Q.sub.B1, Q.sub.B2 . . . of the basic circuits 21.sub.-1, 21.sub.-2 . . . of the successive stages are commonly connected to the gate terminals. Timings and waveforms of the operating pulses, as well as the voltage waveforms in various portions of the circuit, are identical to those in the first embodiment explained before in connection with FIG. 3B.

In this embodiment, the supply of the drain currents of the MOS transistors Q.sub.B1, Q.sub.B2, . . . is conducted via the juncture of the gate terminal rather than from the source voltages V.sub.DD, so that the high-speed operation characteristic is somewhat impaired, although the overall performance is materially equivalent to that of the first embodiment. Moreover, the second embodiment offers an advantage in that the wiring area for the elements can be appreciably reduced as compared with the first embodiment.

FIG. 5A shows the circuit arrangement in a third embodiment of the present invention. This third embodiment is intended for further reducing the number of elements constituting each basic circuit. A first-stage basic circuit 31.sub.-1 has three MOS transistors Q.sub.D1, Q.sub.L1, Q.sub.T1 and a capacitor C.sub.F. The MOS transistors Q.sub.D1, Q.sub.L1, Q.sub.T1 perform functions equivalent to those performed by the MOS transistors Q.sub.1, Q.sub.2, Q.sub.3 of the bootstrap inverter explained before in connection with FIG. 2A. The MOS transistors Q.sub.D1 and Q.sub.L1 which are connected in series to each other constitute an inverter circuit in which the transistor Q.sub.L1 serves as a load transistor while the transistor Q.sub.D1 functions as a driver transistor. This inverter circuit is connected between the power supply V.sub.DD and the grounding terminal. The capacitor C.sub.F also is constituted by a MOS diode and corresponds to the feedback capacitor C.sub.1 of the bootstrap inverter shown in FIG. 2A. The capacitor C.sub.F is connected between the gate terminal of the MOS transistor Q.sub.L1 and the point of juncture between the MOS transistors Q.sub.D1 and Q.sub.L1. A symbol C.sub.S represents a parasitic capacitance corresponding to the parasitic capacitance C.sub.2.

The source electrode of the MOS transistor Q.sub.T1 is connected to the gate terminal of the load transistor Q.sub.L1. The drain terminal of the transistor Q.sub.T1 receives the start pulse ST while the gate terminal of the same receives the transfer synchronizing pulse .phi..sub.3. On the other hand, the gate terminal of the driver transistor Q.sub.D1 receives the synchronizing pulse .phi..sub.2 and the point of juncture between the MOS transistors Q.sub.D1 and Q.sub.L1 constituting the inverter circuit constitutes an output terminal 32.sub.-1.

A second-stage basic circuit 31.sub.-2 has a construction which is substantially the same as the first-stage basic circuit 31.sub.-1 except that it receives different synchronizing pulses. Thus, the second-stage basic circuit 31.sub.-2 comprises MOS transistors Q.sub.D2, Q.sub.L2 and Q.sub.T2 corresponding to the MOS transistors Q.sub.D1, Q.sub.L1 and Q.sub.T1 of the first-stage basic circuit 31.sub.-1, a feedback capacitor C.sub.F and a parasitic capacitance C.sub.s. The output terminal 32.sub.-1 of the first-stage basic circuit 31.sub.-1 is connected to the drain terminal of the MOS transistor Q.sub.T2 so that the output from the first-stage basic circuit 31.sub.-1 is input to the second-stage basic circuit 31.sub.-2. The gate terminal of the driver transistor Q.sub.D2 and the gate terminal of the MOS transistor Q.sub.T2 receive synchronizing pulses .phi..sub.1 and .phi..sub.4, respectively. The first- and second-stage basic circuits 31.sub.-1 and 31.sub.-2 are alternately connected in a multiplicity of stages, thus constituting a scanning pulse generating circuit of the present invention. The operation of this scanning pulse generating circuit will be described with reference to FIG. 5B, which shows waveforms of pulses applied to various portions of the circuit and waveforms of voltages obtained at various portions of the circuit. The following description is based upon an assumption that all the MOS transistors employed in the scanning pulse generating circuit are of the N-channel type.

At a moment t.sub.1, the start pulse ST applied to the drain terminal of the MOS transistor Q.sub.T1 of the first-stage basic circuit 31.sub.-1 is switched to "H" level. At the same time, the synchronizing pulse (transfer pulse) .phi..sub.3 applied to the gate terminal of the MOS transistor Q.sub.T1 is switched to "H" level, whereby the MOS transistor Q.sub.T1 is turned on. In consequence, the voltage V.sub.1 at the node 41 to which the source terminal of the MOS transistor Q.sub.T1 is connected is raised to V.sub.A. The source terminal voltage V.sub.1 in this state is given by the following formula (7).

where, V(H) represents the voltage of the "H" level of the start pulse ST shown in FIG. 5B. A symbol V.sub.T represents the threshold voltage of the MOS transistor Q.sub.T1. Amount .DELTA.V.sub.T of dropping of the voltage due to substrate effect is expressed by the following formula (8). ##EQU4## where, K is a value given by ##EQU5##

When a voltage V.sub.1 which is equal to V.sub.A is applied to the gate terminal of the load transistor Q.sub.L1, the transistor Q.sub.L1 is switched on. Meanwhile, the driver transistor Q.sub.D1 has already been turned on because its gate terminal receives the synchronizing pulse .phi..sub.2 the level of which has already been changed to "H", so that the output terminal voltage V.sub.01 of the first-stage basic circuit is held at the low level of V.sub.01 ("L")=V.sub.c (<V.sub.T). This voltage V.sub.C corresponds to the "L" level of the output voltage V.sub.OUT of the bootstrap inverter explained before in connection with FIGS. 2A and 2B, and can materially be determined by the following equation:

where, g.sub.m (Q.sub.D1) and g.sub.m (Q.sub.L1) represent the conductance values of the driver transistor Q.sub.D1 and the load transistor Q.sub.L1 which in cooperation constitute an inverter circuit.

At a moment T.sub.2, the level of the synchronizing pulse .phi..sub.2 is switched to "L" level so that the driver transistor Q.sub.D1 is turned off. In this state, the voltage V.sub.1 at the node 41 is held at the same level as the voltage V.sub.1 (t.sub.1) obtained at the moment T.sub.1 so that the load transistor Q.sub.L1 is held in on state, whereby the voltage V.sub.01 at the output terminal rises.

Then, the first stage basic circuit operates in accordance with the operation principle of the bootstrap inverter explained before in connection with FIGS. 2A and 2B. Namely, the voltage at the gate terminal of the load transistor Q.sub.L1 is raised as a result of the rise of the output terminal voltage V.sub.01 and the operation of the feedback capacitor C.sub.F, so that a voltage V.sub.1 (t.sub.2) as represented by the following formula (9) is obtained at the node 41. ##EQU6## where, V.sub.01 represents the output voltage which is obtained when the voltage V.sub.1 (=V.sub.B) at the node 41 after the rise is supplied to the gate terminal of the load transistor Q.sub.L1.

By selecting the capacitance of the feedback capacitor C.sub.f to be suitably greater than the parasitic capacitance C.sub.S connected to the gate terminal of the load transistor Q.sub.L1, it is possible to obtain the following conditions.

The output terminal voltage V.sub.01 of the first-stage basic circuit 31.sub.-1 is maintained at "H" level, i.e., at the same level as the source voltage V.sub.DD, over a period between the moment t.sub.2 and a moment t.sub.3 at which the synchronizing pulse .phi..sub.2 is switched to "H" level. At the moment t.sub.2, the synchronizing pulse .phi..sub.4 has been set at "H" level so that the MOS transistor Q.sub.T2 of the second-stage basic circuit 31.sub.-2 has been turned on. In consequence, the output voltage V.sub.01 (=V.sub.DD) of the first-stage basic circuit 31.sub.-1 is transmitted to the source terminal of the transistor Q.sub.T2, whereby the voltage at the node 42 is changed to V.sub.2 (t.sub.2). The value of this voltage V.sub.2 (t.sub.2) equals the voltage V.sub.1 (t.sub.1)=V.sub.A unless the threshold voltage V.sub.T of the MOS transistor Q.sub.T1 and the MOS transistor Q.sub.T2 is changed. This value of the voltage V.sub.2 (t.sub.2) is maintained even after the moment T.sub.3.

At the moment t.sub.3, the synchronizing pulse .phi..sub.2 is switched to "H" level so that the driver transistor Q.sub.D1 is turned on, with the result that the output terminal voltage V.sub.01 starts to fall to a level V.sub.01 (t.sub.3)=V.sub.C, so that the voltage V.sub.1 at the node 41 of the first-stage basic circuit 31.sub.-1 is lowered to the level V.sub.A. Subsequently, at a moment t.sub.4, the start pulse ST is switched to "H" level while the synchronizing pulse .phi..sub.3 is switched to "H" level, whereby the source terminal of the MOS transistor Q.sub.T1 is switched to "L" level with the result that both the voltage V.sub.1 (t.sub.4) at the node 41 and the output teminal voltage V.sub.01 (t.sub.4) are reduced to the grounding level.

The second-stage basic circuit 31.sub.-2 receives the output terminal voltage V.sub.01 of the first-stage basic circuit 31.sub.-1 which was set at "H" level at the moment t.sub.2. At the same time, the voltage V.sub.2 (t.sub.2) at the node 42 is set at V.sub.A. The second-stage basic circuit 31.sub.-2 therefore performs the same operation as the operation of the first-stage basic circuit 31.sub.-1 in accordance with the synchronizing pulses .phi..sub.1 and .phi..sub.4 the waveforms and timing of which are shown in FIG. 5B, so that an output voltage V.sub.02 (=V.sub.DD) of "H" level is obtained from the output terminal 32.sub.-2 thereof at the moment t.sub.5 at which synchronizing pulse .phi..sub.1 is switched to "L" level. Thereafter, the base circuits 31.sub.-3, . . . of the third and subsequent stages operate in the same manners as those described in accordance with the synchronizing pulses .phi..sub.1 to .phi..sub.4 shown in FIG. 5B, so that output voltages of "H" level which is equal to V.sub.DD are successively derived from the output terminals 32.sub.-2, . . . in a successively-shifted manner with a period T.sub.P which is equal to the length of time between the moment at which the synchronizing pulse .phi..sub.2 falls and the moment at which the synchronizing pulse .phi..sub.1 falls.

In the chart shown in FIG. 5B, the mesial magnitude time width .DELTA.t between the rise of the synchronizing pulse .phi..sub.3 and the fall of the synchronizing pulse .phi..sub.1, and the mesial magnitude time .DELTA.t between the rise of the synchronizing pulse .phi..sub.4 and the fall of the synchronizing pulse .phi..sub.2 are determined to meet the condition of .DELTA.t=0. This, however, is not essential and the substantially same effect can be obtained even under the condition of .DELTA.t=0.

In the embodiments described hereinbefore, the outputs from the output terminals of the basic circuits of the successive stages are used as the scanning pulses. The "L" level of the output voltages from the respective output terminals are determined by the "H" level of the synchronizing pulses .phi..sub.1 and .phi..sub.2 so that there is a risk that fluctuation may occur in the "L" level of every other output voltages due to difference in the "H" level between the synchronizing pulses .phi..sub.1 and .phi..sub.2. In order to obviate such a fluctuation, it is advisable to arrange such that only the outputs from the group of basic circuits driven by the synchronizing pulse .phi..sub.1 or the group of basic circuits driven by the other synchronizing pulse .phi..sub.2 are used as the scanning pulses.

As will be understood from the foregoing description, the present invention offers the following advantages.

(1) The "H" level of the outputs from the basic circuits of the respective stages of the scanning pulse generating circuit can be maintained substantially constant at the level of the source voltage V.sub.DD without being affected by variable factors or parameters such as the threshold voltage V.sub.T of the MOS transistor.

(2) The output voltage exhibits no drop at all with respect to the clock voltage and the power supply voltage, by virtue of the booster-type bootstrap effect produced by the bootstrap inverter, so that the scanning pulse generating circuit can be driven at a compareatively low driving voltage.

(3) Although the scanning pulse generating circuit of the invention is of inverter type or ratio type, the power consumption is almost constant regardless of the number of stages of the basic circuit, because only one stage conducts the inverting operation to consume the electrical power at any time during the operation of the scanning pulse generating circuit. This advantage becomes more appreciable as the number of stages of the scanning pulse generating circuit is increased.

(4) The number of elements to be employed in each basic circuit is as small as three to four, so that the wiring space can be saved. This in turn contributes to a reduction in the pitch or spacing between the basic circuits of adjacent stages, thus realizing a higher scale of integration of the circuit.

When the scanning pulse generating circuit of the present invention is applied to a solid-state imaging device, it is possible to eliminate any fixed pattern noise attributable to the operation of the scanning pulse generating circuit, by virtue of the advantage (1) explained above. In addition, the advantage (4) explained above makes it possible to design and construct solid-state imaging devices having higher scale of integration and employing a greater number of pixels. It is also possible to suppress generation of heat in the regions around the pixel arrays by virtue of the advantage (3) and, hence, to eliminate increase in the level of dark outputs from the pixel arrays.