Static Induction Transistor and Manufacturing Method of the Same

FIG. 1 shows a cross-sectional structure of a single cell of a conventional SIT photosensor;

FIG. 2A is a time chart showing a drive pulse for a SIT photosensor and gate potential;

FIG. 2B shows a circuit to explain the operation of the SIT photosensor;

FIG. 3 illustrates the static characteristics of the SIT;

FIG. 4 illustrates the region in the vicinicy of a source and a gate of the SIT;

FIG. 5 illustrates the dependency of pinch-off voltage V.sub.p and the voltage resistance BV.sub.GS between the gate and the source on the width of the gate;

FIG. 6 illustrates the plan pattern of a single cell of the SIT photosensor;

FIG. 7 illustrates the change in the structures of the gate and the source of the SIT;

FIG. 8 illustrates the reverse-directional characteristics between the gate and the source of the SIT;

FIG. 9A illustrates a cross-sectional view of the SIT according to a first embodiment of the present invention during the manufacturing process;

FIG. 9B illustrates in cross-section the structure of the completed SIT;

FIG. 10 illustrates a cross-sectional view of the SIT according to a second embodiment during the manufacturing process;

FIG. 11 illustrates a cross-sectional view according to a third embodiment;

FIGS. 12A and 12B respectively illustrate potential distribution when no impurities exist in the surface region of an epitaxial layer and when impurities do exist in the same;

FIGS. 13A to 13D illustrate the manufacturing process according to the third embodiment shown in FIG. 11;

FIGS. 14A to 14D illustrate the manufacturing process according to a fourth embodiment of the present invention;

FIGS. 15A and 15B illustrate in cross-section the structure used in the manufacturing process according to a fifth embodiment of the present invention;

FIG. 15C illustrates the relationship between the ion dose, the density at the surface of the epitaxial layer, and dark output;

FIGS. 15D and 15E each illustrate in cross-section the structure according to the fifth embodiment of the present invention;

FIGS. 16A to 16D illustrate the manufacturing process according to the sixth embodiment of the present invention;

FIG. 16E illustrates in cross-section the structure according to the sixth embodiment of the present invention;

FIG. 17 illustrates potential distribution in the structure shown in FIG. 16D;

FIG. 18 illustrates in cross-section the structure according to a seventh embodiment of the present invention; and

FIGS. 19A to 19C illustrate the manufacturing process according to the embodiment shown in FIG. 18.

An embodiment of the present invention will now be described.

FIG. 9A illustrates in cross section the structure of a semiconductor device according to a first embodiment of the present invention, the semiconductor device being in the process of manufacture. In this embodiment, the structure is so constituted as to realize a control of pinch-off voltage. Referring to the figure, reference numeral 101 represents an n.sup.+ substrate, reference numeral 102 represents n.sup.- epitaxial layer, and reference numeral 103 represents an isolating region. Reference numeral 104 represents a thick oxidized film, reference numeral 105 represents a thin oxidized film, and reference numeral 106 represents a p.sup.+ gate region. Reference numeral 107 represents a resist pattern in which a part of the inside of the p.sup.+ gate region 106 and a region 108 in which a source is to be disposed are exposed. Utilizing the resist pattern 107 as a mask, a p-type impurity such as boron or an n-type impurity such as arsenic or phosphorus is implanted at a depth close to the place at which the source diffusion layer will be disposed (in the vicinity of the saddle of the saddle-shaped potential of an SIT), the implanted impurity being an ion 109. As a result of this implantation, an ion-implanted layer 110 is formed. The type of impurity which is implanted is selected in accordance with the direction of the movement of pinch-off voltage. That is, in the case where pinch-off voltage is moved toward the normally-on type, an n-type impurity is implanted, while where the pinch-off voltage is moved toward the normally-off type, a p-type impurity is implanted. The acceleration energy is determined in such a manner that the range is coincident with the saddle point, and the dose is set in accordance with the level of movement of the pinch-off voltage. After ion has been implanted, an oxidized film is formed in a similar manner to that for the conventional process, and the aperture forming for the source region is conducted to allow the source region to be formed. As a result of this, an SIT is obtained in which a p-type or an n-type impurity layer 110 is, as shown in FIG. 9B, disposed immediately beneath the source region 111. In FIG. 9B, reference numeral 112 represents a gate electrode, reference numeral 113 represents a source electrode, and reference numeral 114 represents an oxidized film.

This approach in which the movement of the pinch-off voltage of SITs is realized by implanting ions into a saddle point immediately beneath the source is convenient because SITs having various pinch-off voltages can be manufactured using the same mask and in the same manufacturing process. Furthermore, as the dose of the p-type impurity is increased, it becomes difficult for the p-type layer immediately beneath the source to become depleted by means of drain voltage, as a result of which the SIT operation is transformed to a bipolar operation. That is, this invention can be applied to a case where it is intended that the pinch-off voltage of SITs is controlled, as well as to a case where it is intended that direct current amplification factor h.sub.FE is controlled. By changing the ion-implanting conditions while employing the a same mask, this invention can be applied not only to SITs but also to bipolar transistors.

FIG. 10 illustrates in cross section the structure employed in a manufacturing process according to a second embodiment of the present invention. This embodiment is characterized in that ion-implantation for the purpose of moving pinch-off voltage is conducted successively after the process of providing an aperture for forming the SIT source has been completed. Reference numeral 201 represents an n.sup.+ substrate, reference numeral 202 represents an n.sup.- epitaxial layer, and reference numeral 203 represents an isolating region. Reference numeral 204 represents a thick oxidized film, reference numeral 205 represents a thin oxidized film, and reference numeral 206 represents a p.sup.+ gate region. Reference numeral 207 represents an oxidized film, and reference numeral 208 represents a resist mask for conducting aperture provision for forming the source region 211. After etching the oxidized film 207 and thin oxidized film 205 by means of the resist mask 208, ion 209 is implanted with the resist mask 208 being retained for the purpose of forming an impurity ion-implanted layer 210 in the vicinity of the place at which the source will be formed. Such means for forming an impurity layer according to this embodiment has the advantage that one mask is used both for implanting the ion for the purpose of moving pinch-off voltage and for providing an aperture for forming the source.

FIG. 11 illustrates in cross section the structure according to a third embodiment. This embodiment is characterized in that in order to have the photoelectric charge which has been generated in the epitaxial layer 302 captured by the p.sup.+ gate region 306 without involving any loss, a low-density p-type diffusion layer 310 is formed over the surface of the n.sup.- epitaxial layer 302 in such a manner that the low-density p-type diffusion layer 310 is positioned in contact with the p.sup.+ gate region 306. Reference numeral 301 represents a n.sup.+ substrate, reference numeral 303 represents an isolating region, and reference numeral 304 represents a thick oxidized film. Reference numeral 305 represents a thin oxidized film, reference numeral 307 represents a gate electrode, and reference numeral 308 represents a source electrode. Reference numeral 309 represents an oxidized film, and reference numeral 311 represents a source region.

The surface density of the above p.sup.- diffusion layer 310 is set to a relatively low density in the range between 1.times.10.sup.14 to 1.times.10.sup.16 cm.sup.-3.

Potential distribution during a storage period in the cross sectional plane taken along the line A--A' is illustrated in FIGS. 12A and 12B which respectively show a case where a low-density p-type diffusion layer 301 is present in the surface region of n.sup.- epitaxial layer and a case where the same is not present. FIG. 12A illustrates the potential distribution in a case where no p-type diffusion layer 310 is present on the surface of the epitaxial layer, that is the potential distribution of the conventional structure shown in FIG. 1. A curve a shows the potential distribution in a case where the line A--A' crosses the p.sup.+ gate region 4. A curve e shows the potential distribution in a case where the line A--A' is positioned outward of the depletion layer 9 which extends from the p.sup.+ gate region 4. Curves b, c, and d show the potential distribution in the case where the line A--A' is positioned in the depletion layer 9 extending from the p.sup.+ gate region 4, the potential distribution shown by the curves b, c, and d being positioned away from the p.sup.+ gate region 4 in the alphabetical order of those curves. The region outward of the depletion layer 9 extending from the gate region 4 has no electric field. Therefore, the photo-generated holes 11 which have been generated in this region reach the end of the depletion layer 9 by way of diffusion, causing the photo-generated holes 11 to inevitably disappear in part. The probability that the photoelectric charge will vanish due to the recombination undertaken during diffusion is increased as the distance from the end of the depletion layer 9 is itself increased. Therefore, if a design in which the epitaxial region is widened is employed for the purpose of improving blue sensitivity, a problem arises in that the photoelectric charge is lost.

Meanwhile, as shown in FIG. 11, according to the present invention, in a case where a low-density p-type diffusion layer 310 is formed in the surface region of the epitaxial layer, the potential distribution becomes as shown in FIG. 12B. That is, since the p.sup.+ gate region 306 and the p-type diffusion layer 310 is electrically connected, an electric field accelerated with respect to the holes is formed toward the surface of the epitaxial layer regardless of the location of the line A--A'. The photo-generated holes are immediately captured in the p-type diffusion layer 310 by means of this accelerated electric field. Since the holes in the p-type diffusion layer 310 are of the majority carrier type, they have a long life. Therefore, the holes do not vanish even while they are being diffused from the p-type diffusion layer 310 to the p.sup.+ gate region 306, or while they drift and move through the electric field formed in the p-type diffusion layer 310.

The question as to whether the movement of the holes from the p-type diffusion layer 310 toward the p.sup.+ gate region 306 is carried out by means of diffusion or drift is determined in accordance with the density of the p-type diffusion layer 310. In a case where the density of the p-type diffusion layer is high, the p-type diffusion layer 310 is not depleted due to the reverse bias voltage between the p.sup.+ gate region 306 and the n.sup.+ substrate 301 and that between the p.sup.+ gate region 306 and the isolating region 303. Consequently movement by means of diffusion can be effected. On the other hand, in a case where the density of the p-type diffusion layer 310 is low, causing the p-type depletion layer 310 to be depleted due to the above reverse bias voltages, movement by means of drifting is performed. If the photo-generated holes are moved by drifting through the p-type diffusion layer 310, and are captured in the p.sup.+ gate region 306, no loss of photoelectric charge is involved.

In the embodiment shown in FIG. 11, the p-type diffusion layer 310 is formed in the surface region of the epitaxial layer. In such a structure, both the p.sup.+ gate region 306 and the p-type diffusion layer 310 are, in a reset mode, forwardly biased with respect to the grounded source 311. Therefore, all the holes captured in the p.sup.+ gate region 306 and p-type diffusion layer 310 are discharged to the source 311, and consequently no residual images is generated.

FIGS. 13A to 13D partially illustrate an SIT photosensor in a manufacturing process according to a third embodiment shown in FIG. 11, a structure being shown in which the p-type diffusion layer is provided in the surface region of the epitaxial layer outside the p.sup.+ gate region. In FIG. 13A, reference numeral 401 represents an n.sup.+ substrate, reference numeral 402 represents an n.sup.- epitaxial layer, and reference numeral 403 represents an isolating region. Reference numeral 404 represents a thin oxidized film, and reference numeral 405 represents an Si.sub.3 N.sub.4 film which covers the region where the SIT gate and the source will be formed. Reference numeral 406 represents a resist, and reference numeral 407 represents a .sup.11 B.sup.+ ion. By selectively oxidizing with the resist 406 which is removed after the .sup.11 B.sup.+ ion 407 has been implanted, a p-type diffusion layer 409 is, as shown in FIG. 13B, formed beneath the thick oxidized film 408. Then, as shown in FIG. 13C, a thin oxidized film 410 is formed again after the Si.sub.3 N.sub.4 film and the thin oxidized film 404 have been removed. Then large dose .sup.11 B.sup.+ ion 412 is implanted using the resist pattern 411 as a mask. Then, as shown in FIG. 13D, a p.sup.+ gate region 413 is formed by means of thermal diffusion after the resist pattern 411 has been removed. According to this manufacturing method, since high temperature treatment process of selective oxidization and the P.sup.+ gate diffusion are conducted for the purpose of forming a p-type diffusion layer 409, the p-type diffusion layer 409 can be diffused for a deep level.

If the density in the p-type diffusion layer 409 is high, a problem arises in that the blue sensitivity deteriorates due to the forming of a non-depleted region in the p-type diffusion layer 409 because of reverse bias between the p.sup.+ gate region 413 and the substrate 401 and that between the p.sup.+ gate region 413 and the isolating region 403.

In order to overcome this problem, the manufacturing process of a fourth embodiment, shown in FIGS. 14A to 14D, is one in which the p-type diffusion layer is formed only in the extreme surface region of the epitaxial layer. FIG. 14A illustrates the forming process of Si.sub.3 N.sub.4 pattern 505 before being selective-oxidized, wherein a state is shown in which only the Si.sub.3 N.sub.4 is removed from the isolating region 503. Reference numeral 501 represents an n.sup.+ substrate, reference numeral 502 represents an n.sup.- epitaxial layer, reference numeral 504 represents a thin oxidized film, and reference numeral 506 represents a resist. The selective oxidization is conducted in this state, and the Si.sub.3 N.sub.4 pattern 505 and the thin oxidized film 504 are removed. Then a thin oxidized film 507 is formed by way of re-oxidization. As shown in FIG. 14B, a resist mask 508 is then formed, and .sup.11 B.sup.+ ion 509 is implanted, a p.sup.+ gate region 510 then being formed by thermal diffusion. Then, as shown in FIG. 14C, the resist 511 is made to cover the location 512 where the source will be formed and parts of the p.sup.+ gate regions 510, and a low dose .sup.11 B.sup.+ ion 513 is implanted. By annealing in a furnace or lamp-annealing, a boron-implanted layer 514 is activated, and a shallow p-type layer 515 is, as shown in FIG. 14D, formed. A BF.sub.2.sup.+ ion may be used for the purpose of obtaining an ever shallower p-type layer. Thanks to the provision of such a shallow p-type layer 515, an SIT photosensor can be obtained in which the blue sensitivity is not substantially deteriorated, no capturing loss of photoelectric charge occurs, and, hence, no residual image is created.

FIGS. 15A and 15B illustrate in cross-section the structure of the manufacturing process of a fifth embodiment of the present invention. In this embodiment, by way of shortening a depleted layer which extends along the surface of the epitaxial layer disposed to the outside of the P.sup.+ gate region, a thermally-excited charge generated at the surface is lowered for the purpose of restricting the dark output. That is, by ion-implanting a .sup.31 p.sup.+ ion or .sup.75 As.sup.+ ion into the surface of the epitaxial layer disposed on the outside of the p.sup.+ gate region 604, the density at the surface of the epitaxial layer 602 is increased, and an n-type layer 606 is formed. FIG. 15C shows the results of an experiment on the relationship between the dose of the phosphor ion .sup.31 p.sup.+, the density at the surface of the epitaxial layer, and the dark output. That is, when the density at the surface of the epitaxial layer is increased by ion-planting on the outside of the gate region by making use of phosphor, the dose and density (1.times.10.sup.17 to 1.times.10.sup.18 cm.sup.-3) at the surface of the epitaxial layer at which the dark current reaches its lowest level is, as shown in FIG. 15C, obtained. In FIG. 15C, in a region A, since the width of the depletion layer which extends to the outside of the gate region is reduced due to the increase in the dose, the dark current is lowered, being generated at the boundary surface between the SiO.sub.2 oxidized film and the epitaxial layer. On the other hand, in a region B, when the dose is increased, the dark current is increased because of damage due to ion-implanting, or because of an increase in the reverse leak current due to p.sup.+ /n.sup.+ junction.

FIG. 15A illustrates a case which is similar to the third embodiment shown in FIGS. 13A to 13D, and in which an n-type impurity is ion-implanted before selectively-oxidizing regions other than the place 607 where the SIT gate and source will be formed. Similarly to the fourth embodiment shown in FIGS. 14A to 14D, FIG. 15B illustrates in cross-section a structure in a manufacturing process in which ion-implanting is conducted after the selective oxidization of the SIT and the gate diffusion have been completed. In FIGS. 15A and 15B, reference numeral 601 represents a n.sup.+ substrate, reference numeral 603 represents an isolating region, reference numeral 605 represents a thick oxidized film, and reference numeral 608 represents a thin oxidized film. Similarly to the embodiment shown in FIGS. 13A to 13D, and that shown in FIGS. 14A to 14D, the structure shown in FIG. 15B is more suitable for forming a shallow n-type layer.

FIGS. 15D and 15E respectively show SITs manufactured by the method shown in the corresponding FIGS. 15A and 15B. In FIGS. 15D and 15E, reference numeral 609 represents a gate electrode, reference numeral 610 represents a source region, reference numeral 611 represents a source electrode, and reference numeral 612 represents an oxidized film.

FIGS. 16A to 16D illustrate in cross-section the manufacturing process for SITs according to a sixth embodiment of the present invention in which the third and fourth embodiments shown in FIG. 11, FIGS. 13A to 13D and FIG. 14A to 14D, and the fifth embodiment shown in FIGS. 15A to 15D are combined. In FIG. 16A, reference numeral 701 represents an n.sup.+ substrate, reference numeral 702 represents an n.sup.- epitaxial layer, and reference numeral 703 represents an isolating region. Reference numeral 704 represents a thin oxidized film, reference numeral 705 represents a Si.sub.3 N.sub.4 pattern in which an SIT field region 707 is bored for the purpose of using it as the wiring region. Reference numeral 706 represents a resist. Using the resist 706 and the Si.sub.3 N.sub.4 pattern 705 as a mask, a .sup.31 P.sup.+ ion 708 is ion-implanted, and selective-oxidization is conducted for the purpose of forming a field oxidized film 709. As shown in FIG. 16B, an n-type layer 710 is formed beneath the field oxidized film 709. Then the Si.sub.3 N.sub.4 pattern 705 and the thin oxidized film 704 are removed, and a thin oxidized film 712 is again formed due to thermal oxidization. Then .sup.11 B.sup.+ ion 714 is ion-implanted by means of a resist mask 711 at the location 713 where a p.sup.+ gate will be formed for the purpose of forming a p.sup.+ gate region 715 by way of thermal diffusion. Then, as shown in FIG. 16C, the resist mask 716 is made to cover the location 717 where the source will be formed and parts of the p.sup.+ gate region 715 before ion implanting .sup.11 B.sup.+ ion and .sup.75 As.sup.+ ion 718 and annealing. As a result of this, as shown in FIG. 16D, a double-layer structure comprising a shallow n-type layer 719 and a p-type layer 720 which is formed beneath the former is formed in the surface region of the epitaxial region outside of the p.sup.+ gate region 715.

The density of the n-type layer 719 is determined to be high enough to ensure that sufficient voltage resistance with respect to the p.sup.+ gate region 715 can be obtained (for example, 1.times.10.sup.17 to 1.times.10.sup.18 cm.sup.-3), and the depth of diffusion is set to be as shallow as possible. On the other hand, the density of the p-type layer 720 is set at a low level such as, 1.times.10.sup.14 to 1.times.10.sup.16 cm.sup.-3. The shallow n-type layer 719 is connected to the n-type layer 710, and is connected to the n.sup.+ substrate 701 through the isolating region 703. The extension of the depletion layer from the p.sup.+ gate region 715 toward the outer surface is limited by the presence of the shallow n-type layer 719 which causes the density of the surface of the epitaxial layer to become high. Therefore, generation of any thermally exciting charge in this region can be kept to a low level.

The potential distribution during a storage period at the position of a line BB' in FIG. 16D becomes as shown in FIG. 17 since a p-type layer 720 is present. That is, an electric field .epsilon. toward the p-type layer 720 is present in the epitaxial layer 702 on the outside of the p.sup.+ gate region 715. The photo-generated holes are collected without involving any loss by means of this electric field .epsilon. into the p.sup.+ gate region 715 through a hole-capturing portion 721 at which the potential with respect to the holes in the p-type layer 720 is at its lowest. The photo-generated hole moves along a route from an epitaxial bulk to the p.sup.+ gate region 715 via the p-type layer 720, or a route from the surface of the epitaxial layer to the p.sup.+ gate region 715 via the p-type layer 720. The photo-generated hole is captured in the p-type layer 720 disposed away from the surface, and is moved through the same, whereby the probability of recombination at the surface thus being extremely small.

FIG. 16E is a cross-sectional view of an SIT manufactured by the method shown in FIGS. 16A to 16D. In this figure, reference numeral 721 represents a gate electrode, reference numeral 722 represents a source region, reference numeral 723 represents a source electrode, and reference numeral 724 represents an oxidized film.

FIG. 18 illustrates in cross-section a structure according to a seventh embodiment of the present invention. This structure is so constituted that the generation of dark output between the p.sup.+ gate and source is kept at a low level. As shown in FIG. 8, when the width Wg of the gate is enlarged for the purpose of increasing voltage resistance between the p.sup.+ gate and source, the width t of the depletion layer between the p.sup.+ gate region and source is also increased. Therefore, the reverse leak current increases. In this embodiment, it is intended that the surface depletion is prevented, and the generation of the thermal exciting charge is thereby reduced by increasing the surface density between the p.sup.+ gate and source. That is, the structure is similar to the conventional structure shown in FIG. 1, except that an n-type layer or a p-type layer 811 is formed at a shallower position than the source 810 between the p.sup.+ gate region 804 and the source 810. In FIG. 18, reference numeral 801 represents an n.sup.+ substrate, reference numeral 802 represents an n.sup.- epitaxial layer, reference numeral 803 represents an isolating region, and reference numeral 805 represents a thick oxidized film. Reference numeral 806 represents a thin oxidized film, reference numeral 807 represents a gate electrode, reference numeral 808 represents a source electrode, and reference numeral 809 represents a CVD oxidized film.

FIGS. 19A to 19C illustrate the manufacturing process of the embodiment shown in FIG. 18. As shown in FIG. 19A, an n.sup.- epitaxial layer 902 is formed on an n.sup.+ substrate 901. A thick oxidized film 905 is formed in regions other than the place 904 where the source and gate will be formed, the thick oxidized film 905 being formed by way of masking of Si.sub.3 N.sub.4 and selective oxidization after forming an isolating region 903. After the Si.sub.3 N.sub.4 mask and the pad oxidized film have been removed, a thin oxidized film is formed by way of thermal oxidization, and .sup.11 B.sup.+ ion is ion-implanted by means of the resist mask at the place where the p.sup.+ gate region will be formed so that a p.sup.+ gate region 906 is formed by thermal diffusion. Then the thin oxidized film is removed, and the thin oxidized film (gate oxidized film) 907 is again formed by thermal oxidization. Next, a gate electrode 908 is formed in the p.sup.+ gate region 906 for the purpose of applying bias, the gate electrode 908 being made of a material such as polysilicone.

As shown in FIG. 19B, a resist mask 909 is then used for the purpose of ion-implanting in the surface region of the n.sup.- epitaxial layer on the inside of the p.sup.+ -gate region 906. In this embodiment, an n-type impurity 910 such as .sup.75 As.sup.+ is implanted. Then, as shown in FIG. 19C, the resist mask 909 is removed, a CVD SiO.sub.2 911 is applied for the purpose of insulating each layer, and a SiO.sub.2 911 in the location 912 where the source will be formed is removed by means of the resist mask. Then polysilicone 913 is accumulated, and .sup.31 P.sup.+ or .sup.75 As.sup.+ 914 is ion-implanted over the entire surface of the accumulated polysilicone 913. The phosphour or arsenic which has been implanted in the polysilicone 913 is activated by annealing at 900.degree. C. for 30 to 60 minutes, and is simultaneously diffused slightly into the location 912 where the source will be formed. In the thermal process for source diffusion, the depth of the n-type diffusion layer 915 of arsenic which has been implanted in the process shown in FIG. 19B is arranged not to exceed the depth of the source diffusion region 916. Then, by forming the pattern of the polisilicone 913, a structure like that shown in FIG. 18 is obtained. Next, the layer-insulating film is accumulated, a contact hole is formed, and Al wire is connected.

The structures according to the first, second, fifth and seventh embodiments shown in FIGS. 9B, 10, FIGS. 15A and 15B, and FIG. 18 can be applied not only to SIT photosensors, but also to the SIT alone, and to a case in which an improvement in the characteristics of SITICs is intended.

As described above with reference to the embodiments, pinch-off voltage can be controlled according to the present invention, by means of an impurity layer formed by ion-implanting at a location immediately beneath the source region. Therefore, the control of pinch-off voltage does not need any change in processing conditions, masks or so on.

Furthermore, by forming various impurity layers by changing the type of impurity, accelerating energy and dose, SITs having optional pinch-off voltages can be easily produced. Furthermore, by forming impurity layers in which the impurity dose is changed, a bipolar transistor can be obtained. As a result of this, SITs and bipolar transistors can be formed using the same mask. Furthermore, control of h.sub.FE of bipolar transistors can be performed.

According to the present invention, since an impurity layer of the same type as that of the gate region is formed in the surface region of the epitaxial layer outside of the gate region, an electric field can be formed that substantially covers the entire surface of the epitaxial layer. Therefore, the photoelectric charge generated in the portion close to the surface of the epitaxial layer can be captured in the gate region without involving any loss. As a result of this, the generation of residual images can be effectively prevented.

According to the present invention, since each structure is arranged in such a manner that the density at the surface of the epitaxial layer outside of the gate region is increased by way of forming an impurity layer in the same, the extension of a depletion layer which projects over the gate region is prevented, whereby the thermally excited charge generated in this depletion layer can be reduced, and dark current is restricted too so as to improve the S-N ratio.

According to the present invention, since an impurity layer is formed in the surface region of the epitaxial layer between a gate and a source for the purpose of preventing extension of a depletion layer at the surface between the gate and the source, the amount of a thermally excited charge generated in this depletion layer can be reduced, and dark current is restricted too, allowing the S-N ratio to be improved.

While the invention has been particularly shown and described in reference to preferred embodiments thereof, it will be understood by those skilled in the art that changes in form and details may be made therein without departing from the spirit and scope of the invention.