US 4,888,677 AGrant
Three Reservoir Capacitor
Issue Date:1989-12-19
•4 Claims
•5 Drawing Sheets
Abstract
A charge pump circuit operates from a voltage provided on an input rail at a first potential relative to a reference potential rail and that provides second and third potentials relative to the reference potential rail on first and second output rails, respectively. The charge pump circuit includes first, second and third charge reservoir capacitors, an oscillator and control logic circuit for providing timing control signals, and a switch network responsive to the timing control signals for coupling the first, second and third capacitors in a plurality of configurations. The switch network also provides for the decoupling of the capacitors from between the input rail and the reference potential rail between transitions of these configurations.
Metadata
Assignee
- Teledyne Industries, Inc.
Inventors
- Michael A. Grimm
- Paul Hildebrant
Application Information
Application Number:US 3024296
Filing Date:1989-01-27
Priority Date:1989-01-27
Art Unit:212
Classifications
IPC:
H02M 725
Field of Search:
36330732059;60109;1101
Patent Drawings (5 sheets)
Description
Field of the Invention
The present invention generally relates to charge pump circuits used to generate a voltage potential difference greater than the otherwise available supply rail potential and, in particular, to a charge pump circuit appropriate for monolithic fabrication with RS-232 type transceiver circuits and capable of providing split voltage potentials suitable for powering the operation thereof.
Background of the Invention
Conventional computing equipment typically utilize RS-232 type transceiver circuits for the communication of data. Conventional RS-232 data transceivers operate from .+-.12 volt power supply rails and function to bidirectionally convert data between the standard digital logic signal (0-5 volts) representation and logically equivalent transmission voltage levels (.+-.12 volts). The ordinary digital logic levels exist only within the relatively small and electromagnetic interference (EMI) controlled area of the computer equipment enclosure. The relatively much greater RS-232 transmission voltage levels are used to transfer data through less EMI protected data cables that are often of substantial length. Such cables are therefore further subject to signal attenuation. The use of higher transmission voltage levels, however, allows a relatively large signal-to-noise ratio to be maintained even in the presence of significant signal attenuation.
In response to the continuing pressure to reduce the size, board level complexity and cost of computer equipment, a single integrated circuit embodying a pair of conventional RS-232 data transceivers and a charge pump circuit for generating the required .+-.12 volt power from a single 5 volt input power source has been developed. For example, the device disclosed in U.S. Pat. No. 4,636,930, Bingham, et al, issued Jan. 13, 1987 and entitled "Integrated Dual Charge Pump Power Supply and RS-232 Transmitter/Receiver", illustrates a workable approach to providing a single chip RS-232 transceiver. The circuit disclosed utilizes four discrete charge reservoir capacitors, linked by an integrated charge pump switch network, to provide the necessary .+-.12 volts required by co-integrated RS-232 transceiver circuits. Two reservoir capacitors are used alternatingly to accumulate and transfer charge. The remaining two reservoir capacitors are utilized to receive charge from the transfer reservoir capacitors and to support the current transfer requirements of the respective .+-.12 volt supply lines between charge transfers.
Although the Bingham, et al charge pump circuit provides an adequate solution and is suitable for monolithic integration, the circuit has two distinct disadvantages. The first disadvantage is that it requires four discrete charge reservoir capacitors of substantial size. Each charge reservoir capacitor is typically on the order of 100 microfarads. Capacitors of such size directly increase the amount of printed circuit board surface area and enclosure volume required to implement a complete RS-232 transceiver circuit.
The second and perhaps more significant disadvantage is that the monolithic fabrication of the Bingham, et al circuit requires several significant, if not critical, specialized process dependant integrated features to prevent incorrect operation of the circuit due to the occurrence of parasitic transistors. The operation of the switching network in effectively switching the charge reservoir capacitors between circuit nodes results in impulse currents of sufficient magnitude to initiate the operation of even weakly parasitic transistors. Consequently, the design of the Bingham, et al circuit requires several clamping structures to be implemented to block potential parasitic current paths. The implementation of current clamps require additional processing steps, with an increase in the complexity of fabrication, in order to insure ensure proper operation.
Summary of the Invention
A general purpose of the present invention is to realize a charge pump circuit optimally suited for fabrication with RS-232 transceiver circuits and the like on a monolithic substrate.
This is achieved in the present invention by the provision of a charge pump circuit operating from a voltage provided on an input rail at a first potential relative to a reference potential rail and that provides second and third potentials relative to the reference potential rail on first and second output rails, respectively. The charge pump circuit includes first, second and third charge reservoir capacitors, an oscillator and control logic circuit for providing timing control signals, and a switch network responsive to the timing control signals for coupling the first, second and third capacitors in a plurality of configurations. A first configuration occurs wherein the first capacitor is coupled between the input rail and the reference potential rail, the second capacitor is coupled between the first output rail and the reference potential rail, and the third capacitor is coupled between the reference potential rail and the second output rail. A second configuration is achieved wherein the first capacitor is coupled between the first output rail and the input rail, the second capacitor is coupled between the first output rail and the reference potential rail, and the third capacitor is coupled between the reference potential rail and the second output rail. A third configuration is achieved upon coupling of the first capacitor between the first output rail and the input rail. The second capacitor is coupled between the reference potential rail and the second output rail, and the third capacitor is coupled between the reference potential rail and the second output rail. In transitioning between these configurations, the switch network provides for the decoupling of the first capacitor from between the input rail and the reference potential rail prior to enabling the second configuration and from between the first output rail and the input rail prior to enabling the first configuration, and for the decoupling of the second capacitor from between the first output rail and the reference potential rail prior to enabling the third configuration and from between the reference potential rail and the second output rail prior to enabling the first configuration.
Thus, an advantage of the present invention is that it provides a charge pump circuit for generating two voltages of opposite polarity and symmetric potential relative to a reference potential with magnitudes approximately twice that of the single input voltage potential. This is achieved in the present invention while requiring only three charge reservoir capacitors.
Another advantage of the present invention is that it is compatible with epitaxial integrated circuit fabrication processes, thereby essentially eliminating the occurrence of on-chip parasitics that would interfere with the operation of the present invention.
A further advantage of the present invention is that it is capable of providing its output voltage potentials with adequately low output ripple and at sufficient continuous current draw levels as to fully support a full function RS-232 type transceiver circuit.
Brief Description of the Drawings
These and other attendant advantages and features of the present invention will become readily appreciated upon consideration of the following detailed description of the invention when considered in conjunction with the accompanying drawings, wherein like reference numerals designate like parts throughout the figures thereof, and wherein:
FIG. 1 is a simplified schematic diagram of an RS-232 type transceiver pair powered from a single voltage level input charge pump circuit;
FIG. 2 is a simplified schematic diagram of a three-charge reservoir capacitor charge pump circuit constructed in accordance with a preferred embodiment of the present invention;
FIG. 3 is a detailed schematic diagram of an oscillator and first stage timing control signal generation circuit for controlling the switch network of the present invention;
FIGS. 4a-b are simplified schematic diagrams of a second stage for generating timing control signals for controlling the switch network of the present invention;
FIG. 4c is a schematic diagram of the level shifting and timing control circuitry of a preferred embodiment of th present invention corresponding to the second stage circuit shown in FIG. 4a;
FIG. 5 illustrates the waveforms of the timing control signals utilized in a preferred embodiment of the present invention to control the switch network of a preferred embodiment of the present invention;
FIG. 6 is a detailed circuit schematic of the charge pump switch network utilized in a preferred embodiment of the present invention; and
FIG. 7 is a cross-sectional diagram of a portion of the circuit of the present invention illustrating the preferred epitaxial fabrication of the transistors thereof.
Detailed Description of the Invention
A simplified schematic diagram of an RS-232 type transceiver pair operating from the output voltages provided from a charge pump circuit that, in turn, operates from a single low voltage (typically 5 volt) input source, as generally indicated by the reference numeral 10, is shown in FIG. 1. The circuit 10 includes a charge pump subcircuit 12 operating from an input voltage rail 14 provided with an input voltage .sup.+ V.sub.I and a ground reference rail 16 at a reference voltage potential V.sub.G. The charge pump subcircuit 12 operates to provide two output voltages, .sup.+ V.sub.O and .sup.- V.sub.O, having a potential difference of approximately 4.sup.+V.sub.I (% 2.sup.+ V.sub.I ) centered about the reference potential V.sub.G. The positive output voltage .sup.+ V.sub.O is provided on the internal output rail 18 to both the transmitter 22 and receiver 24 subcircuits. The negative potential .sup.- V.sub.O similarly provided on a separate internal output rail 20 to the transmitter and receiver 22, 24.
The transmitter 22 receives an input logic signal Tx.sub.i on an externally connected input line 26. The function of the transmitter 22, conventionally, is to level shift the input TTL compatible logic level present on the input line 26 to a unipolar voltage potential Tx.sub.o that correspondingly varies between .+-.12 volt levels on the transmitter output line 28.
The receiver 24 performs a complementary function. An externally provided input signal, Rx.sub.o, that varies between .+-.12 volt levels is buffered to TTL compatible voltage levels and provided as Rx.sub.i on the receiver output line 32.
A simplified schematic diagram of the preferred charge pump subcircuit 12 of FIG. 1 is shown in FIG. 2. A network of switches 44, 52, 56, 58, 62, 70, 74, 76 are provided to variously interconnect charge reservoir capacitors C.sub.1 46, C.sub.2 64 and C.sub.3 78 to provide the output voltages .sup.+ V.sub.O and .sup.- V.sub.O on the output rails 18, 20. A control logic and oscillator block 40 provides the timing signals necessary to control the operation of the switch network. The block 40 produces a first control signal, denoted as "B+C", on control line 42 to control the operation of switches 44 and 52. Switch 44 in turn, controls coupling terminal 48 of capacitor 46 to the input voltage rail 14. Switch 52 controls the coupling of the second terminal 50 of the capacitor 46 to the .sup.+ V.sub.O output rail 18.
A second control signal, denoted as "A", is provided on control line 54 to switches 56 and 58. Switch 56 controls the coupling of the first terminal 48 of the capacitor 46 to the ground reference rail 16. Switch 58 controls the coupling of the second terminal 50 of the capacitor 46 to the input rail 14.
A third control signal, denoted as "C", is provided on a control line 60 to switches 62 and 70. Switch 62 controls the coupling of a first terminal 66 of the capacitor C.sub.2 64 to the .sup.- V.sub.O output rail 20. Switch 70 controls the coupling of a second terminal 68 of the capacitor C.sub.2 64 to the ground reference rail 16.
Finally, a fourth control signal, denoted as "A+B", is provided to the remaining switches 74, 76. Switch 74 controls the coupling of the first terminal 66 of the capacitor C.sub.2 64 to the ground reference rail 16. The switch 76 controls the coupling of the second terminal 68 of the capacitor C.sub.2 64 to the .sup.+ V.sub.O output rail 18.
The circuit schematic of the control logic and oscillator block 40 is shown in greater detail in FIGS. 3 and 4. Referring first to FIG. 3, the circuit schematic for the oscillator and initial timing control logic 40' is shown. A timing capacitor C.sub.T 80 is coupled between the output rail 18 and a node 82. Inverters 84 and 86, whose inputs are commonly connected at node 82, drive the respective gates of series connected P- and N- type transistors 88, 90 to switch the input to an inverter 92, coupled to the common connection point between the FETs 88, 90 that are, in turn, connected between the .sup.+ V.sub.O output rail potential and a buffered ground potential provided at a virtual ground reference rail 16'. The input and output of an inverter 94 are respectively coupled to the output and input of the inverter 92 to provide a latch function for the input of the inverter 92. The output of the inverter 92 is further coupled to the input of an inverter 96 whose output provides a timing control signal C' on control line 102. The signal is also fed back to the input of an inverter 104 whose output is coupled to the node 82. Another timing control signal, (A+B)', is provided on a control line 100 from the output of an inverter 98 whose input is the control line 102.
As should be readily apparent, the delay contributed by the inverters 84, 86, 92, 96 and 104, combined with the voltage slew imposed by the timing capacitor C.sub.T at the node 82, further combined with the complimentary switching operation of the FETs 88 and 90, results in the creation of a free running oscillator. The period of this oscillator may be directly controlled by the value selected for the timing capacitor C.sub.T 80, the unit logic delay of the inverters 84, 86, 92, 96 and 104 and selection of the independent input thresholds of the inverters 84 and 86. For the latter, the duty cycle is adjusted by adjusting the ratio of the slew current provided by inverter 104 at its output in the pull-up mode (output going high) as compared to the pull-down mode (output going low). In the preferred embodiments of the present invention, the oscillator frequency is approximately 27 kHz with a duty cycle of 66.67%.
Another factor affecting both the period and duty cycle of the oscillator is the voltage potential provided at the virtual ground reference rail 16'. The control logic and oscillator block 40 must be isolated from supply voltage transients in order to ensure continued steady operation. While the block 40 might be powered from the relatively stable input voltage potential .sup.+ V.sub.I, as generally shown in FIG. 2, the preferred embodiments of the present invention use P-type FETs in the block 40 in addition to N-type FETs. The channel of the P-type FETs are preferably coupled through the N.sup.+ type substrate of the preferred embodiments to the highest potential, i.e., .sup.+ V.sub.O, in order to minimize body effect. If the block 40 is powered by the positive output potential .sup.+ V.sub.O, rather than .sup.+ V.sub.I, an unnecessary power dissipation problem and a requirement for higher-voltage tolerant P-type FETs can be avoided. Consequently, the block 40 is preferably operated from the .sup.+ V.sub.O potential on the positive output rail 18 and a constant .sup.+ V.sub. O -5 V potential provided on the virtual ground reference rail 16', i.e., the same potential difference represented by .sup.+ V.sub.I.
The potential at the virtual ground reference rail 16' is controlled largely by the reverse biased threshold of a Zener diode 130 series connected between the positive output potential .sup.+ V.sub.O and through a resistor 132 to the ground reference voltage potential rail 16. The gate terminal of a P-type FET 134 is coupled to the common series connection between the Zener diode 130 and the resistor 132 to thereby establish a current path between the virtual ground node 16' and the ground voltage reference rail 16. A bypass capacitor 138 is coupled between the positive output potential .sup.+ V.sub.O rail 18 and virtual ground rail 16', while a second resistor 136 is coupled between the virtual ground rail 16' and the ground voltage reference rail 16. Thus, the threshold voltage of the Zener diode 130, less the gate threshold potential of the FET 134, effectively establishes a high-frequency bypassed ground reference potential for the control logic and oscillator block 40' that tracks the positive output potential .sup.+ V.sub.O. The control logic and oscillator block 40' is therefore effectively isolated from transients on the input and ground reference rails 14, 16 and particularly, the output voltage rail 18. In the preferred embodiments of the present invention, the Zener diode is provided with a threshold of approximately 6.3 V.sub.Z.
The input of a latch configured pair of inverters 106, 108 is also coupled through an inverter 105 to the node 82. The output of the latch 106, 108 is coupled as an input to an inverter 110 whose output is, in turn, connected to a first input of a NAND gate 112. The second input of the NAND gate 112 is connected to the control line 100.
The inputs of inverters 114 and 116 are commonly connected to the output of the NAND gate 112. The inverter 114 provides an A' control signal on the control line 122. The inverter 116 is coupled through a second inverter 117 to provide a (B+C)' control signal on the control line 120. A delay inducing capacitor C.sub.D is coupled at a point between the inverters 116, 117 and the output voltage rail 18.
As illustrated in FIGS. 4a-b, the timing control signals C', (A+B)', A' and (A+B)' are provided to buffers 140, 146, 152 and 158, respectively. In turn, the buffers 140, 146 level shift and provide complimentary timing control signals C and C on timing control lines 142, 144, and A+B and A+B on timing control lines 148, 150; these signals being provided relative to the negative output .sup.- V.sub.O 20. Similarly timing control signals A and A are provided by the buffers 152, 158 on timing control lines 154, 156 and timing control signals B+C and B+C are provided on the timing control lines 160, 162; these signals also being provided relative to the negative .sup.- V.sub.O 20. However, as shown in FIG. 4a, an enable signal provided from buffer 140 on control line 145 determines, at least in part, when the state of the A+B and A+B timing control signals can change in response to a change in the (A+B)' signal. The enable signal on control line 145 is provided when the timing control signal C' is provided active low. Until the buffer 146 receives the enable signal on control line 145, the state of the A+B and A+B timing control signals are prevented from changing in response to a rising edge in the (A+B)' signal.
Similarly, an enable signal is provided from the buffer 146 on control line 151 to determine, at least in part, when the state of the C and C may change in response to a change in the C' timing control signal. That is, once buffer 146 has been enabled, allowing the A+ B and A+B timing control signals to transition with A+B inactive, or low, the buffer 140 is enabled by provision of the enable signal on the enable control line 151 to permit the transition of the C and C timing control signals on control lines 142, 144 in response to a rising edge in the C' timing control signal.
As shown in FIG. 4b, an enable control signal, provided on the enable control line 157 from the buffer 152 following the A' timing control signal going active low, is used to enable the buffer 158. An enable control signal is provided by the buffer 158 to the buffer 152 in response to a transition by the (B+C)' timing control signal to its active low state.
FIG. 4c details the circuitry of the buffer pair 140, 146. The circuitry of the buffer pair 152, 158 is essentially identical. An initial, level shifting stage receives the timing control signals C' and (A+B)' at the gates of P-type FETs 101, 103 that are respectively coupled from the output potential .sup.+ V.sub.O rail 18 to the enable control lines 145, 151. A latch, formed by FETs 143 and 149 coupled from the respective enable control lines 145, 151 to the negative output rail .sup.- V.sub.O 20, complete the input stage. The outputs of the level shifting stage are the enable control lines 145, 151. The level shifter is designed such that if both inputs, (A+B)' and C', are low, both outputs will be high. When both inputs, (A+B)' and C', are high, the P-type FETs 101, 103 are off and the N-type FETs 143, 149 latch the previous state of the (A+B)' and C' timing control signals. For all other states of the inputs, (A+B)' and C', the level shifting stage merely repeats its inputs at its outputs.
The outputs, 145, 151, of the level shifting stage are respectively provided to series coupled inverter pairs 139, 141 and 147, 153. These inverters, in turn, provide the C, C, A+B and A+B timing control signals on the timing control lines 142, 144, 148, and 150.
Referring now to FIG. 5, the timing waveforms associated with the operation of the preferred embodiment of the present invention are shown. The waveform N.sup.82 illustrates the change of voltage potential at node 82 of FIG. 3. For an oscillator cycle period beginning at t.sub.0 and ending at t.sub.12, the N.sub.82 waveform rises, in the preferred embodiment of the present invention, for two thirds of the cycle before declining to the original voltage level during the balance of the cycle. The N.sub.82 waveform effectively reflects the ideal three-phase waveforms, shown as A.sub.I B.sub.I and C.sub.I that define the basic three-phase operation of the present invention. However, the ideal waveforms A.sub.I B.sub.I and C.sub.I not actually generated in the operation of the present invention. Rather, the intermediate timing control wave forms (A+B)', C', A' and (B+C)' are produced directly by the operation of the control logic and oscillator block 40' of FIG. 3 based on the N.sub.82 waveform. These intermediate timing control signals (A+B)', C', A' are then combined and used to produce the final timing and control signals C, A+B, B+C and A. Considering the single cycle between t.sub.0 and t.sub.12 as representative of all operational cycles of the present invention, the three operational phases are generally defined as occurring between t.sub.0 and t.sub.4 (Phase 1), t.sub.4 and t.sub.8 (Phase 2), and t.sub.8 and t.sub.12 (Phase 3). During the first phase of operations, for example at t.sub.2, timing control signals A+B and A are active on while timing control signals C and B+C are inactive, or off. Consequently, switches 44 and 52 of FIG. 2 are effectively open, switches 56 and 58 are closed, switches 62, 70 are open and switches 74, 76 are closed. In this Phase 1 circuit configuration, capacitor C.sub.1 46 is charged from the input voltage rail 14 while capacitor C.sub.2 64 and C.sub.3 78 support the .sup.+ V.sub.O and .sup.- V.sub.O output voltage potentials on the respective output rails 18, 20.
During Phase 2, for example at T.sub.6, timing control signal B+C is active while timing control signal A is inactive. Thus, terminal 48 of capacitor C.sub.1 46 has been decoupled by switch 56 from the ground reference rail 16 and coupled through switch 44 to the input rail 14. Similarly, terminal 50 of capacitor C.sub.1 46 has been decoupled from the input rail 14 by switch 58 and coupled to the positive output rail 18 by switch 52. Consequently, charge is transferred from capacitor C.sub.1 46 to capacitor C.sub.2 64 while boosting the voltage potential on the output rail 18 to approximately twice the input rail potential .sup.+ V.sub.I.
Finally, in the third phase of operation, for example at t.sub.10, the timing control signal C is active while the timing control signal A+B is inactive. Thus, the terminals 68, 66 of capacitor C.sub.2 64 are respectively decoupled by the action of the switches 74, 76 from between the positive output rail 18 and the ground reference rail 16 and coupled, by switches 70, 62, respectively, to the ground reference rail 16 and negative output potential rail 20. Consequently, charge stored by the capacitor C.sub.2 64 is transferred to capacitors C.sub.3 when the voltage potential across the capacitor C.sub.2 64 is applied across the capacitor C.sub.3. After a number of cycles of operation, the magnitude of voltage potential difference across C.sub.3 will stabilize at approximately twice that of the input rail potential .sup.+ V.sub.I. During this Phase 3, the capacitor C.sub.1 46 acts to support the positive output rail potential, .sup.+ V.sub.O on output rail 18.
In order to conserve the charge stored by the capacitors C.sub.1, C.sub.2 and C.sub.3 and to minimize output voltage and current spiking, the mutual transitions of the timing control signals C, A+B, B+C and A, are critical. At the conclusion of Phase 1, at about t.sub.4, terminals 48, 50 of capacitor C.sub.1 must be decoupled in response to timing control signal A from the ground reference and input voltage rails 16, 14, respectively. This decoupling must occur prior to being connected to the input voltage and positive output voltage rails 14, 18, respectively in response to the B+C timing control signal. As should be apparent, failure to do so would result in the direct shorting of capacitor C.sub.1 46. Therefore, timing control signals B+C and A must not have overlapping active states.
Similarly, the terminals 48, 50 of capacitor C.sub.1 46 must be decoupled from the input and positive output rails 14, 18 prior to being recoupled to the ground reference rail 16 and positive voltage input rail 14. This non-overlap condition is effectively controlled by the provision of the delay capacitor C.sub.D coupled to the input of inverter 117 and the enablement of buffer 158 in response to the provision of the A' timing control signal. The transition of the timing control signal B+C is delayed from t.sub.0 by approximately 0.5 microseconds in the preferred embodiment of the present invention. Since the buffer 152 of FIG. 4b is enabled only when the timing control signal (B+C)' is low, the timing control signal A is not provided on the control line 156 until approximately 0.6 microseconds after t.sub.0.
The timing control signals A+B and C must likewise have non-overlapping active high states in order to prevent shorting during the transitions between Phases 2 and 3 at t.sub.8 and between Phases 3 and 1, at t.sub.12. That is, the terminals 66, 68 of capacitor C.sub.2 64 must be decoupled by switches 74, 76 from the ground reference and positive output voltage rails 16, 18 prior to being coupled to the negative voltage output and ground reference rails 20, 16 by operation of the switches 62, 70. Due to the presence of the inverter 98, in the control logic and oscillator block 40' as shown in FIG. 3, the (A+B)' timing control signal transitions will closely lag those of the timing control signal C'. However, the rising edge of the timing control signal C is forced to trail the falling edge of the timing control signal A+B by use of the A+B timing control signal to enable the operation of buffer 140 to provide the C timing control signal on control line 144.
Finally, it is highly preferred, if not critical, for the active high states of the A+B and B+C timing control signals to overlap during the transition from phase 3 to phase 1. This condition is desired to insure that the positive output voltage potential rail 18 is supported at all times by a reservoir capacitor. This condition is effectively achieved in the present invention by selection of the timing delay capacitor's C.sub.D value such that transitions of the timing control signal (B+C)' follow those of the timing control signal (A+B)' by a margin of at least 0.2 micro seconds and, in the preferred embodiment of the present invention, by approximately 0.4 microseconds.
A detailed schematic diagram of the preferred charge reservoir capacitor switching network of the present invention is shown in FIG. 6. N-type FET 174 and P-type FET 176 act as simple switches to permit the coupling of the terminals 48, 50 of the charge reservoir capacitor C.sub.1 46 to the ground reference and positive input rails 16, 14 respectively, in response to the application of the A and A timing control signals to their FET gate electrodes via control lines 156, 154.
Similarly, P-type FETs 170 and 172 enable the coupling of the terminals 48, 50 of the capacitor C.sub.1 46 to the input voltage and positive output supply rails 14, 18 in response to the B+C timing control signal provided to their FET gates via control line 160.
The timing A+B control signal, provided via control line 148 to the gate of P-type FET 188 allows terminal 68 of the reservoir capacitor C.sub.2 64 to be coupled to the positive output supply rail 18. The terminal 68 is also alternately coupled through N-type FET 180 to the ground reference rail 16 in response to the C timing control signal as provided on control line 144. The C timing control signal also controls N-type FET 178 in coupling terminal 66 of the capacitor C.sub.2 to the negative output supply rail 20.
N-type FET 186, controlled by the A+B timing control signal, provides a current path from terminal 66 of capacitor C.sub.2 64 to the ground reference rail 16. Two additional FETs 182, 184, respectively controlled by the C and A+B timing control signals, are also serially coupled between terminal 66 and the ground reference rail 16. The source and drain of FETs 182, 184 are further coupled to the body of FET 186. Consequently, the body effect associated with FET 186 is substantially reduced, ensuring that FET 186 switches quickly in response to the A+B timing control signal.
Finally, one collector and the emitter of a diode connected multiple collector transistor 190 are respectively connected to the negative supply reference rail 20 and ground reference rail 16. The output potential .sup.+ V.sub.O is provided to a second collector of the transistor 190 to ensure operation as an unidirectional, fast acting current shunt. Thus, the transistor 190 operates to clamp positive voltage transients that may appear on the negative output supply rail 20 to voltages less than approximately +0.6 volts particularly during start-up operation.
In accordance with the preferred embodiments of the present invention, no further design enhancements need be provided to ensure proper operation of the present invention. This is made possible by the preferred use of an epitaxial fabrication process that inherently provides for a high degree of isolation between neighboring FET transistors.
For purposes of completeness, a cross-section 200 of two neighboring switch FET transistors of the present invention are shown in FIG. 7. As typical of conventional epitaxial fabrication processes, an N.sup.- epitaxial layer 204 is provided on the surface of an N.sup.+ type substrate 202. For example, a P-type FET transistor is formed by the provision of P.sup.+ source and drain regions 210 formed in the epitaxial layer 204 and a gate electrode 214. An N-type FET transistor is formed by the provision of N+source and drain regions 212 in a P-well 208 also formed in the epitaxial layer 204. The N-type FET is completed with the provision of its gate electrode 218. As is conventional, the gates 214, 218 of the P-type and N-type FET transistors are formed within the overlying oxide layer generally indicated as layer 220. The N- and P-type transistors are thus present within respective portions of the N-epitaxial layer 204 effectively isolated by the existence of a low impedance path through the N.sup.+ substrate to the .sup.+ V.sub.O potential.
Thus, a three phase charge pump circuit requiring no more than three charge reservoir capacitors and that is suitable for fabrication on a common monolithic substrate with RS-232 type transceiver circuits has been described.
From the forgoing disclosure of the preferred embodiments of the present invention, numerous modifications and variations should be readily apparent to those of skill-in-the-art to which the present invention pertains. Accordingly, it is therefore to be understood that, within the scope of the appended claims, the present invention may be practiced otherwise than as specifically described above.
Claims
We claim:
1. A charge pump circuit operating from an input rail provided at a first potential difference relative to a reference potential rail to provide second and third potential differences also relative to said reference potential rail on first and second output rails, said charge pump circuit comprising: (a) first, second and third capacitors; (b) oscillator means for providing a timing control signal; and (c) control means, responsive to said timing control signal, for coupling said first, second and third capacitors in a plurality of configurations including: (i) a first configuration wherein said first capacitor is coupled between said input rail and said reference potential rail, said second capacitor is coupled between said first output rail and said reference potential rail, and said third capacitor is coupled between said reference potential rail and said second output rail; (ii) a second configuration wherein said first capacitor is coupled between said first output rail and said input rail, said second capacitor is coupled between said first output rail and said reference potential rail, and said third capacitor is coupled between said reference potential rail and said second output rail; and (iii) a third configuration wherein said first capacitor is coupled between said first output rail and said input rail, said second capacitor is coupled between said reference potential rail and said second output rail, and said third capacitor is coupled between said reference potential rail and said second output rail; said control means providing for the decoupling of said first capacitor from between said input rail and said reference potential rail prior to enabling said second configuration and from between said second output rail and said input rail prior to enabling said first configuration and for the decoupling of said second capacitor from between said first output rail and said reference potential rail prior to enabling said third configuration and from between said reference potential rail and said second output rail prior to enabling said first configuration.
2. The charge pump circuit of claim 1 wherein said control means further provides for the coupling of said first capacitor between said first output rail and said input rail prior to enabling said second configuration and for the coupling of said second capacitor between said first output rail and said reference potential rail prior to enabling said first configuration.
3. A charge pump circuit for providing first and second output voltage potentials on first and second output supply rails, said charge pump circuit operating from an input voltage potential provided on an input supply rail and a ground potential provided on a ground rail, said charge pump circuit comprising: (a) an oscillator; (b) timing means, responsive to said oscillator, for providing a plurality of timing signals transiting between active and inactive signal states, said plurality of timing signals including first, second, third and fourth signals related as defining first, second and third timing phases and wherein the inactive state of said first signal substantially defines the duration of said first and second phases in time, the active state of said first signal substantially defines the duration of said third phase in time, the active state of said second signal is non-overlapping with the active state of said first signal, the active state of said third signal substantially defines the duration of said first phase in time and is overlapping with the active state of said second signal, and the active state of said fourth signal is non-overlapping with the active state of said third signal; (c) first, second and third reservoir capacitors, each having first and second terminals, the first and second terminals of said third reservoir capacitor being coupled to said ground rail and said second output rail, respectively; (d) first switching means, responsive to the active state of said third signal, for coupling said first and second terminals of said first reservoir capacitor to said input rail and said ground rail, respectively; (e) second switching means, responsive to the active state of said fourth signal, for coupling said first and second terminals of said first reservoir capacitor to said first output rail and said input rail, respectively; (f) third switching means, responsive to the active state of said second signal, for coupling said first and second terminals of said second reservoir capacitor between said first output rail and said ground rail; and (g) fourth switching means, responsive to the active state of said first signal, for coupling said first and second terminals of said second reservoir capacitor between said ground rail and said second output rail, respectively.
4. An integrated circuit including an on-chip charge pump circuit for providing first and second output voltage potentials on first and second output supply rails, said charge pump circuit operating from an input voltage potential provided on an input supply rail and a ground potential provided on a ground rail, wherein said charge pump circuit requires no more than three reservoir capacitors for operation, said integrated circuit comprising: (a) a monolithic substrate including an epitaxial layer forming a major surface thereof; (b) an oscillator circuit fabricated on said major surface of said monolithic substrate; (c) timing means, fabricated on said major surface of said monolithic substrate and responsive to said oscillator, for providing a plurality of timing signals transiting between active and inactive signal states, said plurality of timing signals including first, second, third and fourth signals related as defining first, second and third timing phases and wherein the inactive state of said first signal substantially defines the duration of said first and second phases in time, the active state of said first signal substantially defines the duration of said third phase in time, the active state of said second signal is non-overlapping with the active state of said first signal, the active state of said third signal substantially defines the duration of said first phase in time and is overlapping with the active state of said second signal, and the active state of said fourth signal is non-overlapping with the active state of said third signal; (d) first, second and third reservoir capacitor connection points provided on said major surface of said monolithic substrate, each having first and second terminals, the first and second terminals of said third reservoir capacitor connection point being coupled to said ground rail and said second output rail, respectively; (e) first switching means, fabricated on said major surface of said monolithic substrate and responsive to the active state of said third signal, for coupling said first and second terminals of said first reservoir capacitor connection point to said input rail and said ground rail, respectively; (f) second switching means, fabricated on said major surface of said monolithic substrate and responsive to the active state of said fourth signal, for coupling said first and second terminals of said first reservoir capacitor connection point to said first output rail and said input rail, respectively; (g) third switching means, fabricated on said major surface of said monolithic substrate and responsive to the active state of said second signal, for coupling said first and second terminals of said second reservoir capacitor connection point to said first output rail and said ground rail; and (h) fourth switching means, fabricated on said major surface of said monolithic substrate and responsive to the active state of said first signal, for coupling said first and second terminals of said second reservoir capacitor to said ground rail and said second output rail, respectively.