Circuit Protection Device

Several embodiments of the invention will now be described by way of example with reference to the accompanying drawings, in which:

FIG. 1 is a side view, partly in section, of a BNC

coaxial connector that incorporates a circuit protection

device according to the invention;

FIG. 2 is a side view, partly in section, of a flat

cable mass termination connector and wafers that

incorporate a circuit protection device according

to the invention;

FIG. 3 is an enlarged view of part of the connector

shown in FIG. 2;

FIG. 4 is a perspective view of a modification of the

wafers shown in FIG. 2;

FIG. 5 is a schematic view of a capacitor that incorporates

a circuit protection device according to

the invention; and

FIG. 6 is a diagram of a circuit used to determine

the energy to latch of the materials and devices

according to the invention.

FIG. 7 is a perspective view of a chip carrier

employing the device according to the invention;

FIG. 8 is a view, partly in section, of a modification

of the chip carrier of FIG. 7;

FIG. 9 is a section showing a further modification

of the carrier shown in FIG. 7;

Referring to FIG. 1 of the accompanying drawings, a connection arrangement for connecting two coaxial cables comprises a connector shell 1 and a male connector 2. The male connector 2 comprises a pin 3, the central and rear portion of which is hollow for receiving the central conductor of a coaxial cable to be connected (not shown). The pin has a fluxed solder ring 4 and a number of apertures (not shown) beneath the solder ring which communicate between the solder ring 4 and the hollow interior of the pin 3. The rear end 10 of the pin is firmly located in a connector housing 5 by means of an electrically insulating plastics spacer 6. The housing 5, which provides the electrical connection between the shields of the cables to be connected, has a termination portion 7 on which is mounted a solder impregnated braid 8 and solder ring 9.

The rear end 10 of the pin is provided on its outer surface with an electrode, e.g. a copper/indium electrode followed by a 10 micrometer thick layer 11 of a selenium-germanium-antimony glass described above that has been deposited thereon by a vapour deposition method, and the outer surface of the glass layer 11 has been provided with a further thin (about 5 micrometers thick) electrode, e.g. formed from indium/copper by vapour deposition. The copper electrode is electrically connected to the housing 5 by means of a bonded wire 12.

In order to connect a coaxial cable to the connector, the outer jacket, shield and dielectric are cut back by appropriate amounts and the cable inserted into the connector so that the exposed end of the internal conductor is located within the hollow interior of the pin 3, the dielectric abuts the rear end of the spacer 6 and the exposed shield is located within the solder impregnated braid 8. The connector is then briefly heated, for example by means of a hot-air gun, to fuse the solder rings 4 and 9 and to form solder connections between the pin 3 and central conductor and between the braid 8 and coax cable shield.

The connector will function exactly as a standard coaxial connector until the connected cable experiences a voltage transient whereupon the potential difference across the thickness of the glass layer 11 will cause the glass to become electrically conductive and form a closed circuit between the central conductor and the shield.

Referring to FIGS. 2 and 3, a mass termination connector such as that described in U.S. Pat. No. 3,993,394 (the disclosure of which is incorporated herein by reference) is schematically shown.

The connector comprises a connector housing 21 and a pair of connector wafers 22 and 23 that can be inserted into the housing. Each wafer 22,23 has a number of (usually 25 or 50) metallic electrical conductors 24 extending therethrough which terminate at one end either in the form of pins 25 or complementary "tuning fork" female contacts and at the other end in the form of contacts 26 for connection to a flat cable or to a number of small single conductor wires. The particular means used for connecting the conductors 24 to the wires or flat cable is not shown but usually comprises one or more solder devices for example as described in U.S. Pat. No. 3,852,517.

In each of the wafers 22 and 23 a stepped recess 27 is made that extends across the width of the entire wafer to expose each of the conductors. in one embodiment of this connector, a copper electrode is deposited onto the individual conductors 24 followed by a 10 micrometer thick layer 28 of the selenium-germanium-antimony glass described above, and a thin electrode 29 formed e.g. from copper or gold is deposited on top of the glass layer 28. An additional conductive layer 30 or "ground plane" of copper or gold is deposited on the wafer material in the stepped recess 27, the ground plane being electrically earthed for example to the metallic housing of the connector or to an earth pin. Each electrode 29 is connected to the ground plane by means of a wire 31 formed from e.g. gold or aluminium and bonded to the electrode 29 and ground plane 30 by conventional wire bonding techniques. ,

Alternatively, a single layer 28 of the glass and electrode 29 may be deposited across the entire width of the wafer in which case only a single wire 31 is necessary for connection to the ground plane, or the ground plane and wire can even be dispensed with if one of the conductors 24 is earthed.

In an alternative construction, the glass layer and electrodes are deposited onto the common ground plane 30, and the wires 31 connect the conductors 24, after any appropriate surface preparation if necessary, with the electrode of the glass layer.

FIG. 4 shows schematically a further modification of the wafer shown in FIGS. 2 and 3. In this form of wafer the glass layers 28 and electrodes 29 are deposited on the conductors 24 as described above and are electrically connected to a ground plane 30 by means of wires 31. In addition, however, a 100 nanofarad capacitor 40 is located in the recess 27 and is connected between the ground plane and an earth terminal or housing of the connector. In this form of device any transient current having a frequency spectrum above about 1 MHz is conducted directly to earth while any direct currents or alternating currents of frequencies significantly lower than about 1 MHz are blocked by the capacitor. This modification of the device has the advantage that it reduces or eliminates the possibility of the glass switching layers 28 being held in their low resistance state by the direct currents in the electrical system after the transient has been transmitted to earth.

FIG. 5 shows schematically a circuit protection device according to the invention that may be incorporated into any larger electrical component. The device comprises a capacitor 51 having a capacitance for example of 0.5 to 3 microfarads (although larger or smaller capacitances e.g. 0.1 to 1 microfarads may be desired in many circumstances) which is provided with terminals 52 and 53. A 10 micrometer thick layer 54 of the selenium-germanium-antimony glass switching material described above is deposited on the terminal 52 for example by a vapour deposition method and then a thin copper electrode 55 is deposited on the glass layer 54 by evaporation. Additional metal layers may be provided on top of the electrode 55 in order to improve the formation of solder joints if desired. As described above copending European Patent Application No. 86302326.3, the glass layer will become conductive when the circuit is exposed to a transient having a high frequency spectrum, e.g. above 1 MHz, to allow the transient to be passed to earth, but the capacitor will exhibit a high impedence to lower frequency signals and therefore prevent such signals latching the glass layer 54 in its low resistance state.

FIG. 7 shows the use of a threshold circuit protection device according to the present invention on a chip carrier 71 containing a chip 72. The conductive I/0 pads of chip 72 are wire bonded by wires 73 to conductive pads 74 in the chip carrier. The threshold circuit protection device 75 comprises a glass layer which contacts the conductive pads 74 of the chip carrier and an electrode layer in contact with the glass which can be grounded to earth through an appropriate earthpad in the chip carrier or any other appropriate point in the chip package. The threshold circuit protection device 75 covers a portion of the pad 74 of chip carrier 71 leaving a portion of each pad 74 available for wire bonding of the chip 72 and wires 73. The threshold circuit protection device 75 can be formed in situ on chip carrier 71 by first depositing the glass layer, for example by vapour deposition, on the appropriate areas of the conductive pads 74 of the chip carrier and then depositing the electrode layer on top of the glass, which in turn can be connected to earth through a separate wire bond to an earth pad or chip package frame. Alternatively the glass layer can be omitted from an appropriate pad on the chip carrier thereby permitting the electrode layer to be deposited on the glass and on and in contact with that pad which will serve as an earthing pad. The circuit protection device in the chip carrier allows all of the in/out circuits to be in contact with the glass layer which glass is in turn in contact with a ground plane. Thus any overvoltage which enters the package through any lead or I/0 pad can immediately pass through the glass layer to the ground plane. As mentioned above, any appropriate elements such as the capacitor of FIGS. 4 or 5 may also be built into the combination of the circuit protection device and the chip carrier. The circuit protection device 75 can be connected to pads 74 by conductive adhesive or other appropriate means.

FIG. 8 shows a further modification of FIG. 7, here to frame 120 used to support the circuit protection device is multilayered. A pattern of electrodes 121,122 is produced on both top an bottom faces of the frame to match electrodes 123 of the chip carrier 124. The two electrodes 121,122 on opposite faces are interconnected by a conducting channel or via 125. A circuit protection device 126 is built up on the top electrode pattern 121 of the frame 120 and when completed the frame can be fitted into the chip carrier as shown in FIG. 10. As shown in FIG. 9, it is also possible to incorporate within the frame material the elements of a capacitor 127 within the structure of the via 125. This system of assembly provides for a more robust package since the circuit protection device is separated from the electrode tracks of the chip carrier by the conducting vias.

The following Examples illustrate the invention:

Samples of a number of chalcogenide glass compositions were prepared by mixing the components, which were of at least 99.99% purity, and melting the mixture in a silica ampoule under a vacuum or under reduced argon pressure. During melting, which was carried out at tempertures of up to 1000.degree. C. and for periods of up to 48 hours depending on the composition, the ampoule was rocked and rotated in order to ensure that a homogeneous melt was obtained.

A 10 micrometer thick film of the glass so prepared was deposited onto a lower indium plated copper electrode by vapour deposition at a pressure of 10.sup.-3 to 10.sup.-4 Pa using either a resistance heated, or an electron beam heated, source. Deposition rates of 0.1 to 0.5 micrometers per minute were employed. An upper electrode of 1mm.sup.2 area was deposited by evaporating an indium layer followed by a copper layer in argon at a pressure of 10 Pa and at a deposition rate of 0.1 to 1 micrometers per minute.

The glasses had the compositions shown in Table I.

The electrical properties of devices made from the glass compositions are shown in Table II.

The energy to latch of the device, and hence of the glass material, was measured by means of a circuit as shown in FIG. 6. Single shot pulses generated by means of a pulser 1 were passed to the switching element 2 connected in series with a current limiting resistor 3 having a resistance R.sub.2 of from 40 to 100 ohms and the voltage across the switching element was observed by means of oscilloscope 4. The voltage generated by the pulser 1 was gradually increased (about 5 to 10 pulses being passed for each voltage level from the pulser) until the switching element latched in its low resistance state (determined by subsequently measuring its resistance.

The energy to latch the device, E.sub.L was determined by the equation: ##EQU2## where J is the energy available from the pulser; V is the peak voltage from the pulser when

latching occurred;

R.sub.l is the internal output impedance of the

pulser (5 ohms); and

R.sub.2 is the resistance of the current limiting resistor.

This equation gives very good agreement with values obtained by integrating the current and voltage curves of the pulses.