US 4,887,045 AGrant
Sum/Differential Signal Processing Circuit
Issue Date:1989-12-12
•3 Claims
•1 Drawing Sheets
Abstract
A sum/differential signal processing circuit for use in a sound reproduction system, such as a Dolby surround processing system, includes a pair of operational amplifiers, a resistor connected between the inverting input terminals of the operational amplifiers, two resistors connected between the output terminals of the operational amplifiers, a signal output terminal connected to a junction between the two resistors for producing the sum of output signals from the output terminals of the operational amplifiers. A make switch is connected across one of the two resistors, which is selectively rendered ON and OFF. When the make switch is ON, the sum of output signals of the operational amplifiers is derived from the signal output terminal while when the make switch is OFF, the difference between the output signals thereof is derived therefrom. Even when a monaural signal is applied to each of the two signal input terminals, the signal is not cancelled by the circuit thus arranged.
Metadata
Assignee
- Pioneer Electronic Corporation
Inventor
- Kazuaki Nakayama
Application Information
Application Number:US 3305260
Filing Date:1989-03-30
Priority Date:1988-09-07
Art Unit:252
Classifications
IPC:
H03F 345
Field of Search:
33038169;84;124 R;2951;17;18;28
Patent Drawings (1 sheets)
Description
Background of the Invention
The present invention relates to a sum/differential signal processing circuit for use in a surround processor such as a Dolby surround processing system.
Surround processors, such as Dolby surround processing systems, are generally required to produce signals representing the sum of and the difference between left and right stereophonic signals. Therefore, sound reproduction systems, such as these surround processors, include a sum/differential signal processing circuit for producing left and right signals. When a monaural signal is reproduced from an AM broadcasting program or a monaural VTR, the monaural signal would be cancelled if it passed through a difference detector. Thus, it is necessary to switch between differential and sum signal processing modes dependent on an input signal applied.
It would be conceivable to provide a sum/differential signal switching circuit as shown in FIG. 2, in which operational amplifiers IC.sub.1 and IC.sub.2 generate signals V1=A-B and V2=A+B independently of each other. Either one of these signals is selected by a transfer switch SW' so that an output voltage V0 may be either V0=V1 or V0=V2.
The transfer switch SW' is one of the two-contact switching type. Where the transfer switch SW' is constructed of bipolar transistors, as shown in FIG. 3, a control voltage signal is applied directly to the base of one transistor TR.sub.2 and via an inverter to the base of the other transistor TR.sub.1 for allowing input signals applied to the emitters of the transistors TR.sub.1 and TR.sub.2 to be selectively picked up as an output signal from the collectors thereof. Therefore, the transfer switch requires two transistors, and the inverter is further required to invert the control voltage signal. The transfer switch of FIG. 3 is thus complex in arrangement.
Summary of the Invention
It is therefore an object of the present invention to provide a sum/differential signal processing circuit which can switch between a sum signal and a differential signal simply by employing a single bipolar transistor as a make switch.
According to the present invention, there is provided a sum/differential signal processing circuit for receiving first and second input signals and producing a sum signal and a differential signal upon processing the first and second input signals, the circuit comprising:
first and second operational amplifiers, each having an inverting input terminal, a noninverting input terminal and an output terminal;
first and second signal input terminals, the first and second input signals being applied to the first and second signal input terminals, respectively;
an attenuator having one end connected to the first and second signal input terminals and another end connected to the noninverting input terminals of the first and second operational amplifiers for attenuating the first and second input signals when applying to the noninverting input terminals thereof, wherein the first and second operational amplifiers output first and second output signals in response to the attenuated first and second input signals, respectively;
a first resistor connected between the inverting input terminals;
second and third resistors connected in series to each other at a junction, the series-connected resistors being connected across the output terminals of the first and second operational amplifiers;
fourth resistor connected between the output terminal of the first operational amplifier and the inverting input terminal thereof;
fifth resistor connected between the output terminal of the second operational amplifier and the inverting input terminal thereof;
a signal output terminal connected to the junction;
a switch connected across the second resistor, the switch being selectively rendered ON and OFF, the second resistor being short-circuited when the switch is ON; and
wherein the sum signal is indicative of a sum of the first and second outputs and the differential signal is indicative of a difference between the first and second outputs, the sum signal appears on the signal output terminal when the switch is OFF and the differential signal appears thereon when the switch is ON, and wherein resistances of the first, second, third, fourth and fifth resistors are selected so that the sum signal and the differential signal are provided on the signal output terminal.
The sum/differential signal processing circuit thus arranged is preferably employed in a sound reproduction system, such as a Dolby surround processing system. Even when a monaural signal is applied to each of the first and second signal input terminals, the signal is not cancelled.
The above and other objects, features and advantages of the present invention will become more apparent from the following description when taken in conjunction with the accompanying drawings in which a preferred embodiment of the present invention is shown by way of illustrative example.
Brief Description of the Drawings
In the drawings:
FIG. 1 is a circuit diagram of a sum/differential signal processing circuit according to an embodiment of the present invention;
FIG. 2 is a circuit diagram of a sum/differential signal processing circuit on which the present invention is based; and
FIG. 3 is a circuit diagram of a switch for selecting one of a sum signal and a differential signal produced in the sum/differential signal processing circuit shown in FIG. 2.
Detailed Description of the Preferred Embodiments
FIG. 1 shows a sum-differential signal processing circuit according to the present invention.
The sum/differential signal processing circuit includes a pair of operational amplifiers IC.sub.1 and IC.sub.2 having respective noninverting input terminals for receiving signals A and B, respectively, through respective resistors R.sub.1 and R.sub.3. The noninverting input terminals are connected to ground through respective resistors R.sub.2 and R.sub.4 which serve as an attenuator. The operational amplifiers IC.sub.1 and IC.sub.2 have respective output terminals connected to an output terminal OUT of the sum/differential signal processing circuit via respective resistors R.sub.8 and R.sub.9.
Output signals from the operational amplifiers IC.sub.1 and IC.sub.2 are fed back to the respective inverting input terminals via associated resistors R.sub.6 and R.sub.7 for forming negative feedback loops. A resistor R.sub.5 is connected between the inverting input terminals of the operational amplifiers IC.sub.1 and IC.sub.2.
A make switch SW which may be made up of a bipolar transistor is connected between the output terminal of the operational amplifier IC.sub.1 and the output terminal OUT.
Setting that
signal voltages V.sub.1 and V.sub.2 at the output terminals of the operational amplifiers IC.sub.1 and IC.sub.2 are expessed as follows:
The voltage signal V.sub.0 at the output terminal OUT is given as follows:
For the sake of brevity, it is assumed here that .beta.=1and R.sub.6 =R.sub.7. By substituting equations (1) and (2) for equation (3), equation (3) is expressed as follows: ##EQU1## Equation (4) can be rearranged as follows: ##EQU2##
By determining R.sub.1 through R.sub.6 so that .alpha.(1+R.sub.6 /R.sub.5)=.beta..multidot.R.sub.6 /R.sub.5 in equation (1) and using a constant K, the voltage V.sub.1 can be rewritten as:
Assuming that R.sub.3 =0, i.e., .beta.=1, then
Hence K=.alpha./(1-.alpha.).
By determining R.sub.8 and R.sub.9 so that ##EQU3## in equation (4)', and using a constant K', the voltages V0 is givn by:
Equation (4)" is simplified as follows:
Therefore,
If R.sub.8 is a real number, the following equation can be obtained by dividing both sides of the above equation by R.sub.8. ##EQU4##
Assuming that .alpha.=1/2, for example,
Thus, by determining so that R.sub.1 =R.sub.2, R.sub.3 =0, R.sub.5 =R.sub.6 =R.sub.7, R.sub.9 =(5/4).multidot.R.sub.8, the signal voltages of (A-B) and (A+B) are selectively available from the output terminal OUT dependent on whether the make switch SW is turned on or off.
Where the values of the resistors are determined as described above, since ##EQU5##
Because R.sub.5 =R.sub.6 and from equation (5),
With the present invention, simply by selecting the values of the resistors in the sum/differential signal processing circuit, and employing a simple make switch which may be composed of a bipolar transistor, sum and differential signals can selectively be produced from the output terminal of the circuit.
Although a certain preferred embodiment has been shown and described, it should be understood that many changes and modifications may be made therein without departing from the scope of the appended claims.
Claims
What is claimed is:
1. A sum/differential signal processing circuit for receiving first and second input signals and producing a sum signal and a differential signal upon processing said first and second input signals, said circuit comprising: first and second operational amplifiers, each having an inverting input terminal, a noninverting input terminal and an output terminal; first and second signal input terminals, said first and second input signals being applied to said first and second signal input terminals, respectively; an attenuator having one end connected to said first and secnd signal input terminals and another end connected to said noninverting input terminals of said first and second operational amplifiers for attenuating said first and second input signals when applying to said noninverting input terminals thereof, wherein said first and second operational amplifiers output first and second output signals in response to said attenuated first and second input signals, respectively; a first resistor connected between said inverting input terminals; second and third resistors connected in series to each other at a junction, said series-connected resistors being connected across said output terinals of said first and second operational amplifiers; fourth resistor connected between said output terminal of said first operational amplifier and said inverting input terminal thereof; fifth resistor connected between said output terminal of said second operational amplifier and said inverting input terminal thereof; a signal output terminal connected to said junction; a switch connected across said second resistor; said switch being selectively rendered ON and OFF, said second resistor being short-circuited when said switch is ON; and wherein said sum signal is indicative of a sum of said first and second outputs and said differential signal is indicative of a difference between said first and second outputs, said sum signal appears on said signal output terminal when said switch is OFF and said differential signal appears thereon when said switch is ON, and wherein resistances of said first, second, third, fourth and fifth resistors are selected so that said sum signal and said differential signal are provided on said signal output terminal.
2. A sum/differential signal processing circuit according to claim 1, wherein said attenuator comprises a first attenuator connected between said first signal input terminal and said noninverting input terminal of said first operational amplifier for attenuating said first input signal, and a second attenuator connected between said second signal input terminal and said non-inverting input terminal of said second operational amplifier for attenuating said second input signal.
3. A sum/differential signal processing circuit according to claim 2, wherein said first attenuator comprises a sixth resistor and a seventh resistor, said sixth resistor having a first terminal connected to said first input terminal and a second terminal connected to said noninverting input terminal of said first operational amplifier, said seventh resistor having a third terminal connected to said second terminal and a fourth terminal connected to ground, said second attenuator comprises an eighth resistor and ninth resistor, said eighth resistor having fifth terminal connected to said second input terminal and a sixth terminal connected to said noninverting input terminal of said second operational amplifier, said ninth resistor having seventh terminal connected to said sixth terminal and eighth terminal connected to ground.
Patent Citations (1)
| Patent | Date | Inventor | Cited By |
|---|---|---|---|
| US3992590 | 1976-11-01 | Takahashi et al. |