Reset Pulse Generating Device

1. Field of the Invention

This invention relates to reset pulse generating devices, and more particularly to a device for producing a reset pulse by which the output of a digital system is returned to an initial state.

2. Description of the Prior Art

In the past, control of a digital system has been accomplished by clock pulses from either a built-in, or an external clock pulse oscillation circuit. Therefore, it generally follows that when, for some cause, for example, when a drop in the battery voltage for the oscillation circuit stops the production of the clock pulses, the interior condition of the digital system is latched, and its output terminal continues holding the state that existed just before the termination of oscillation.

This raises a serious problem, for example, when the same battery used as the electrical power source of the digital system also serves as an electrical power source to drive a large current load.

Suppose, for example, an apparatus such as a camera equipped with the motor driven winder is controlled by the logic of the digital system. Then, when some trouble occurs during the period of energization of the motor of the winder, or when the battery voltage necessarily drops enough to stop rotation of the motor, and, therefore, falls below a satisfactory operating level for the oscillation circuit, the clock pulses are no longer produced, and the logic for interrupting the current supply to the motor, for example, the logic for the timer no longer operates. Since, in this case, the logic causes current supply to the motor run on, the motor continues to be supplied with current. This gives rise to a big problem in that the battery generates heat and in extreme cases leaks chemicals. Such problem may be encountered in any other apparatus where the battery is used as the electrical power source of the digital system. Some solution to this has, therefore, been sought.

An object of the present invention is to eliminate the above-described drawbacks of the prior art, and to provide a reset pulse generating device responsive to detection of a stoppage of oscillation of a clock pulse oscillation circuit for immediately returning the condition of a system to the initial one thereby making it possible to avoid undesirable influences on the instrument to be controlled.

The drawing is an electrical circuit diagram, partly in block form, of an embodiment of a reset pulse generating device according to the present invention.

The reset pulse generating device of the invention will next be described in greater detail by reference to the drawing.

In FIG. 1, a first analog switch 2 has an input which is connected to an electrical power source VDD, for example battery. The control inputs of the first analog switch 2 and a second analog switch 4 are respectively connected to receive clock pulses from a clock pulse oscillation circuit 6 and the output of a first inverter 8 through which the clock pulses passes, or the inverted signal of the clock pulses. When the clock pulse from the clock pulse oscillation circuit 6 is high, (hereinafter described as H or H level), the first analog switch 2 is rendered conductive, and a first capacitor 10 is charged by the battery VDD. Since, at this time, the inverted signal of the clock pulse goes low (hereinafter described as L or L level), the second analog switch 4 remains non-conductive. Then when the clock pulse changes to L level, the first analog switch 2 is rendered non-conductive. Since, at this time, the inverted signal of the clock pulse assumes the H level, the second analog switch 4 is rendered conductive, so that the charge stored on the capacitor 10 is discharged, and stored on a second capacitor 12. Then, when the clock pulse changes to the H level again, the first analog switch 2 is rendered conductive, so that the first capacitor 10 is charged. Since, at this time, the inverted signal of the clock pulse becomes L, the second analog switch 4 is rendered con-conductive and the charge stored on the second capacitor 12 is discharged through a resistor 14. The time constant of the second capacitor 12 and the resistor 14 is chosen so as to initiate the next charge before the voltage at the input of a second inverter drops below its threshold value as the charge on the second capacitor is discharged. Hence, the input of the second inverter 16 is always at the H level. Therefore, as long as the production of the clock pulses continues, the output of the second inverter 16 assumes the L level. Except when the power-up clear signal from a power-up clear signal forming circuit 20 at the time of turning on the battery is at the H level, and this signal is applied to another input of an OR gate 18, an early-stage reset circuit 22, has its input set to an L level and does not carry out its early-stage resetting function. This permits a digital system 23 to operate in response to the clock pulses from the clock pulse oscillation circuit 6.

Now assuming that for some reason something causes the clock pulse oscillation circuit to stop producing more clock pulses and that in the first case the phase of the last clock pulse is H, then the inverted signal of this clock pulse is maintained at L then, the second analog switch 4 remains non-conducting. Therefore, as the charge stored on the second capacitor 12 is discharged through the resistor 14, the input voltage of the second inverter 16 reaches its threshold value in a predetermined time at which the output of the second inverter 16 changes for the first time to H. In the second case where the phase of the last clock pulse is L, then the first analog switch 2 remains non-conducting. Because the inverted signal of the clock pulse is maintained at H level, as the second analog switch 4 remains conductive, the charge stored on the first capacitor 10 is discharged through the resistor 14. Then, the input voltage of the second inverter 16 falls below the threshold level in the predetermined time and changes its output for the first time to H level. Thus, the accidental stoppage of production of the clock pulses, regardless of the level the last clock pulse results in, the second inverter 16 changing its output to H in the predetermined time. This H level serves as a reset pulse. Therefore, the output of the OR gate 18 also is changed to H in response to inversion of the output of the inverter 16, so that the early-stage reset circuit 22 is actuated. This makes it possible to place the digital system 23, for example, a digitally-controlled camera system in its initial state.

As has been described in greater detail, according to the present invention, a very simple device suffices to make it possible to return the system the initial state as soon as the clock pulses stop. This offers a great advantage from the standpoint of industries whose systems are protected from destruction.