Darlington BiCMOS Driver Circuit

For purposes of insuring the integrity of a voltage level corresponding to a logic-1 in a load connected to the output of a BiCMOS driver circuit, it is desirable to have logic-1 from the output of the driver near or above the supply voltage to the driver circuit. If this desired situation were to occur, better discrimination between logic-0 and logic-1 would be possible. Additionally, for the sake of switching speed or rather a fast response time, it is desirable to have a BiCMOS driver which has low input loading (low amount of current drawn by the input of the circuit). Furthermore, high output loading capability (capability of supplying high current to an output load) is desired. Unfortunately, prior art BiCMOS drivers have been unable to furnish low input loading together with high output loading capability and a logic-1, at their outputs, near or above the supply voltage of the driver circuit.

A more detailed explanation of the limitations and problems associated with the prior art follows below with references to the accompanying FIGS. 1 and 2.

A standard BiCMOS driver is shown in FIG. 1. A logic-0 (low voltage) at the input node, IN, produces a logic-1 at node A from CMOS inverter 2. NMOS transistors 4 and 6 and bipolar transistor 8 are turned off due to the logic-0 at input node, IN. Node A has a voltage potential of approximately Vcc, the circuit supply voltage. Pull-up bipolar transistor 10 turns on due to the Vcc voltage from node A at its base and thus delivers power to output node, OUT.

Switching speed of the BiCMOS driver, shown in FIG. 1, is dependent upon the size of PMOS transistor 16 of CMOS inverter 2. The larger PMOS transistor 16 is, the more charges required to charge up MOS capacitor 15 in PMOS transistor 16 and therefore, the more current required to charge up or discharge capacitor 15, i.e. the more input loading. Consequently, switching speed of the BiCMOS driver decreases with an increasing size of PMOS transistor 16 (assuming that MOS capacitor 15 in PMOS transistor 16 increases with the size of PMOS transistor 16). Therefore, in order to increase switching speed, input loading of MOS capacitor 15 within PMOS transistor 16, should be decreased and consequently the size of PMOS transistor 16 should be decreased. However, since the pull-up speed of bipolar transistor 10 directly affects the switching speed of the BiCMOS driver, a large PMOS transistor 16 is required to quickly supply enough power to the base of bipolar transistor 10 so that it can quickly pull up the voltage at output node OUT. Therefore, in the prior art, maximum switching speed of the BiCMOS driver could not be attained due to constraints on the size of PMOS transistor 16 and base loading requirements of bipolar transistor 10.

High output loading capability is determined by the size of pull-up bipolar transistor 10. A high output loading capability is desired since increased output loading capability necessarily implies the ability to drive a larger load at the output and/or increased fan-out (fan-out being the maximum number of lines that can be driven by an output line) from node OUT. Pull-up bipolar transistor 10 must be large in order to provide enough current to output node OUT so that high output loading is possible. This further adds constraint on PMOS transistor 16's size in that PMOS transistor 16 must be large in order to drive pull-up bipolar transistor 10. Large PMOS transistor 16 creates a low resistance path to Vcc during times it is turned on (input node IN at logic-0) to prevent the base of the pull-up, node A, from booting (rising) significantly higher than Vcc. Since the resistance associated with PMOS transistor 16 is small, the RC time constant associated with parasitic capacitor 12 is relatively small. Charge leaks off the plate connected to node A of parasitic capacitor 12 too quickly to enable it to boot (raise) node A significantly past Vcc. Thus, the output node of the BiCMOS driver, node OUT, is only pulled up to approximately Vcc-Vbe. A timing diagram for the circuit in FIG. 1 is shown in FIG. 2. As shown in FIG. 2 a high output loading along with a maximally high voltage level corresponding to logic-1 could not be attained by the prior art.

It is therefore a primary object of the present invention to provide a new and improved device BiCMOS driver circuit.

It is a further object of the present invention to provide a new and improved BiCMOS driver circuit which provides fast switching speed.

It is still a further object of the invention to provide a new and improved BiCMOS driver circuit which provides low imput loading.

It is yet still a further object of the invention to provide a new and improved BiCMOS driver circuit which provides high output loading.

It is another object of the invention to provide a new and improved BiCMOS driver circuit which provides a high output level logic-1.

The foregoing objects of the invention are accomplised by a BiCMOS driver circuit which uses capacitance to bootstrap its logic-1 output level up to or near the circuit supply voltage. The BiCMOS driver allows low input loading by providing a circuit at the input comprising a CMOS inverter which includes a relatively small p-channel transistor. The BiCMOS driver further provides high output loading by connection of the p-channel transistor to a bipolar transistor which forms a darlington configuration with a pull-up transistor at the output of the circuit.

FIG. 1 is a prior art drawing of a BiCMOS driver circuit.

FIG. 2 is a timing diagram showing key node votages, of the prior art BiCMOS driver circuit in FIG. 1, over a time interval.

FIG. 3 illustrates a first preferred embodiment of the invention wherein parasitic capacitance is used to bootstrap the voltage of the base of a pull-up transistor past Vcc.

FIG. 4 is a timing diagram, showing key node voltages of the invention over a time interval, of the first preferred embodiment of the invention shown in FIG. 3.

FIG. 5 illustrates a second prefered embodiment of the invention wherein a capacitor circuit is used to bootstrap the voltage of the base of a pull-up transistor past Vcc.

FIG. 6 is a timing diagram, showing key node voltages over a time interval, of the embodiment of the invention shown in FIG. 5.

FIG. 7 illustrates a third preferred embodiment of the invention wherein two inverters are substituted for components found in the capacitor circuit of the second preferred embodiment found in FIG. 5.

FIG. 8 is a timing diagram, showing key node voltages over a time interval, of the embodiment of the invention shown in FIG. 7.

FIG. 9 illustrates a fourth preferred embodiment of the invention which accepts two inputs though a logic gate.

FIG. 3 is a schematic drawing of one preferred embodiment of the invention. Bipolar transistor 22 is connected to pull-up bipolar transistor 10 in a darlington configuration in order to increase the current gain measured from node OUT to node B. CMOS inverter 18 drives transistor 22 and is connected to the base of transistor 22. Bipolar transistor 10 is connected to the output of CMOS inverter 2 which includes p-channel transistor 16. Node OUT, is connected to to the emitter of transistor 10 and to pull down means comprising bipolar transistor 8, and n-channel transsitors 4 and 6. A small size for p-channel transistor 16 is now permitted (for instance, a channel width of 24 microns as opposed to a prior art channel width of 200 microns) and used since transistor 22 can provide enough current to pull-transistor 10 in order to furnish a high output loading characteristic for the circuit. A low input loading is now provided since transistor 16 is small. Parasitic capacity 12 can now be used advantageously since small p-channel transistor 16 provides a large enough impedance path between Vcc and node A such that the RC time constant associated with p-channel transistor 16 and parasitic capacitor 12 is relatively large. Parasitic capacitor 12 can now bootstrap the voltage on node A up significantly past Vcc due to the fact that the discharge rate of capacitor 12 is now long. Node A will eventually drop in voltage down to Vcc, and node OUT drops down to Vcc-Vbe. However, by the time the driving function of the circuit has been completed. A higher voltage level, above that found in the prior art is now available for logic-1 levels. The rest of the circuit shown in FIG. 3 works as follows: Pull-down bipolar transistor 8 serves to pull the output node, OUT, down near ground, corresponding to a logic-0. N-channel transistor 6 discharges parasitic capacitor 14 at appropriate time intervals, i.e. during a high output at output node OUT. N-channel transistor 4 drives transistor 8 during times a logic-0 is desired at the output. For a more in-depth analysis of the above BiCMOS circuit, FIG. 4 illustrates a timing diagram showing the voltages at key locations, at certain times, in the circuit. A shown in FIG. 4, Nodes OUT, B and A are rising with a low input level. Note the increased rise times associated with these nodes as opposed to the prior art nodes shown in FIG. 2.

FIG. 5 is a schematic drawing of a second preferred embodiment of the invention.

This embodiment is the same as that shown in FIG. 3 except that it adds capacitor 26, capacitor 28, and resistor 30, all of which contribute to the operation involving booting node A significantly up past Vcc. As shown, capacitor 26 is connected to and between node A and node E. Capacitor 28 is connected at one plate to node E and resistor 30. Capacitor 28 is also connected to circuit ground at its other plate. Additionally, the nonparasitic capacitor circuit allows output node OUT to reach higher levels and switches faster than the embodiment shown in FIG. 3. This circuit removes the dependency of booting up node A solely from parasitic capacitor 12. The operation of this circuit is as follows: During the time output node OUT switches from low to high, node E is lagging in voltage behind node OUT because of the loading effect of capacitor 28. Capacitor 28 charges up until the voltage at node OUT equals the voltage at node E at which time current from node OUT to node E through resistor 30 stops flowing. At the same time node A has been bootstrapped up past Vcc as a consequence of the increasing charge at node E. Node A begins its drop in voltage from above Vcc to approximately Vcc at approximately the time node E reaches approximately Vcc. This drop is caused by the discharge of the plate of capacitor 26, through transistor 16 at its Vcc connection, which is connected to node A. FIG. 6 illustrates a timing diagram showing voltages at key locations, at certain times, in the circuit. As can be seen from FIG. 6 the rise times and voltage limits reached are higher than those of the prior art shown in FIG. 2. Additionally, the voltage limits and rise times are higher than those shown in FIG. 4.

FIG. 7 illustrates a third preferred embodiment of invention which is a variation of FIG. 5 wherein capacitor 28 and resistor 30 of FIG. 5 are replaced by two CMOS inverters in series. The two CMOS inverters 66 and 67 offer decreased internal loading over the capacitor and resistor circuit. The timing diagram for this circuit is shown in FIG. 8. FIG. 8 demonstrates a flatter and higher output voltage characteristic than those shown in either FIGS. 2, 4, or 6.

FIG. 9 illustrates a fourth preferred embodiment of the invention as a BiCMOS driver of FIG. 5 connected to a NOR gate such that the entire circuit of FIG. 9 can be characterized as a BiCMOS NOR driver. This circuit permits the use of a NOR driver without large loading inputs and therefore permits fast driver switching speed. Only inputs of logic-0 at inputs in1 and in2 will produce a logic 1 at the output. Current is allowed to travel through p-channel transistor 50, p-channel transistor 49 and into pull-up bipolar transistor 10 during the in1=logic-0 and in2=logic-0 inputs. All other inputs are prevented from letting current flow to the bases of either transistors 22 or 10 by circuitry which includes resistor 52 and n-channel transistors 40, 42, 44, 46, and 55.

It is also within the scope of the invention to precede the BiCMOS drivers in the embodiments disclosed above with NOR gates including more than two inputs. Furthermore, NOR gate logic need not be used. The drivers could also be preceded by an AND gate, NAND gate, or OR gate or a combination thereof, all of which may contain more than two inputs.

Although the invention has been described in detail herein with reference to its preferred embodiment and certain described alternatives, it is to be understood that this description is by way of example only, and is not to be construed in a limiting sense. It is to be further understood that numerous changes in the details of the embodiments of the invention, and additional embodiments of the invention, will now be apparent to, and may be made by a person of ordinary skill in the art having reference to this description. For instance, n-channel transistors may be substituted for p-channel transistors consistently throughout and vice-versa. Furthermore, although preferred, CMOS inverters need not be used. All existing types of inverters are contemplated. It is contemplated that all such changes and additional embodiments are within the spirit and true scope of the invention as claimed below. Accordingly, the invention is intended to be limited only by the scope of the appended claims.