Cellular Addressing Permutation Bit Map Raster Graphics Architecture

This invention relates to a new computer graphics image creation system frame buffer memory controller, and flexible frame buffer addressing architecture for raster graphics machines. The invention provides a new frame buffer address generator and address circuitry for accessing frame buffer memory locations with different word and cell configuration addressing modes to increase performance and efficiency. The invention provides a new graphics image data generator for creating, modifying, and updating graphics image data in the frame buffer memory locations accessed by the multiple addressing mode word and cell configurations of the address generator. The graphics image data generator provides e.g. vector drawing, polygon fill, "Bit Blt's" or bit block transfers, and refresh display of a raster view surface. The invention also relates to new and unusual permuted bit map organization of graphics image data in the frame buffer memory locations. The frame buffer address circuitry incorporates linear permutation networks that permute the user X,Y or X,Y,Z coordinate addresses to replace standard bit maps with permuted bit maps that accommodate multiple word and cell addressing modes. Parallel processing of accessed data is achieved using a frame buffer comprised of multiple memory banks. The invention also includes new three-dimensional permuted bit map organization with variable number of multiple planes in the third or Z dimension for varying the number of bits defining each pixel.

In computer raster graphics machines, an image is typically displayed by raster scanning on a CRT display screen or other raster display view surface. Each minimum picture element at a display screen or view surface location is referred to as a pixel and each pixel is defined by one or more bits at one or more memory locations of the image data memory. In the simplest raster graphics display, the pixel at each display location is defined by one bit at a corresponding memory location of the image data memory.

The graphics image data memory is referred to as the image frame buffer, image refresh buffer or image bit map. The frame buffer is typically implemented by solid state random access memory (RAM) integrated circuit (IC) chips which may also constitute multiple memory banks. The frame buffer is referred to as a refresh buffer because the image frame on a CRT display screen is refreshed with the contents of the frame buffer, typically 30 or 60 raster cycles per second. The framebuffer is also referred to as a bit map because the contents or bits at the memory locations of the frame buffer are mapped onto the display screen or view surface by a raster scan generator. The contents of the frame buffer are organized in a linear stream by a video scan line generator to control CRT beam intensity.

Typically there is a fixed one to one correspondence between the memory address locations in the frame buffer and the pixel positions on the display screen or view surface identified as the user/viewer X,Y coordinate system. Where each pixel of the raster display view surface is defined by more than one bit for example 1, 2, 4, 8, or 16 bits, etc., the frame buffer memory locations are considered spatially organized into planes for example 1, 2, 4, 8, and 16 planes etc. corresponding to the multiple bits per pixel. The planes may be viewed as adding a third dimension to the bit map. The multiple bits per pixel bear a many-to-one correspondence with pixel positions of the user X,Y coordinate system view surface and are used to define color tone, gray scale, resolution, etc., and provide an image with greater definition.

The contents of the frame buffer are delivered to the video display section in a linear sequence by successive memory cycles. Successive memory cycles access the frame buffer in standard bit map word mode addressing or word configuration addressing of the multiple RAMs or memory banks constituting the frame buffer. Each memory cycle or memory access cycle accesses each of the memory banks consecutively and pulls out a sequence of bits from the successive RAMs or memory banks which may be visualized as a horizontal word or portion of a row of the standard bit map and a horizontal word or portion of a row of pixels on the user X,Y coordinate system view surface. Each scan line of the raster pattern is composed of a sequence of such words retrieved from the bit map forming complete rows or scan lines across the view surface. Typically, approximately half of the memory bandwidth or memory cycle time of the frame buffer is used for refresh memory access.

The other portion of the memory bandwidth or memory cycle time is available for updating the frame buffer or refresh buffer image memory. This is also referred to as writing, drawing or painting new images, image portions or image elements in the frame buffer. In the case of a CRT display, updating is typically accomplished by interleave during refresh. The new contents are displayed by refresh of the image on the display screen or view surface. A disadvantage of the conventional raster graphics word mode architecture and standard bit map is that the update of the frame buffer by "drawing" and "painting" is accomplished using the same word mode addressing and horizontal word configuration for accessing the multiple RAMs or memory banks. This is a disadvantage because the one-dimensional horizontal word mode or word configuration addressing, while it is adapted for efficiently accessing the contents of the frame buffer for refreshing the entire screen, cannot capitalize on the simple geometry of smaller two-dimensional areas of vectors to be drawn.

In vector drawing and painting only a defined portion of the frame buffer need be accessed for drawing, painting or modifying a small portion of the view surface area. The word mode addressing constrains the raster graphics machine to access numbers of memory locations far in excess of that required for a particular frame buffer update for example for drawing a vector. This is because the conventional word mode architecture and addressing looks only at long horizontal word sequences or row portions of the bit map in successive memory cycles. The vector or character to be drawn may conform more realistically to a small vertically oriented two-dimensional rectangle. Excessive time of multiple memory cycles is therefore required for updating the frame buffer in drawing and painting and the available frame buffer memory band width or available memory cycle time is inefficiently used.

The efficiency of performance of the raster graphics machine can be measured as a function of the number of bits defining pixels on the screen which are actually changed or updated each memory cycle. For example, if each memory cycle accesses 64 bits at 64 memory locations of the memory banks in the form of a 64 bit horizontal addressing word, then a 16 bit or 16 pixel vertical or diagonal vector is drawn or updated in the frame buffer inefficiently. In a single plane frame buffer perhaps only a single bit corresponding to a single pixel of the screen is updated each memory word access cycle. Therefore, up to 16 of the word memory access cycles may be required to complete the drawing of the vertical or diagonal vector updating only one bit each 64 bit word memory access cycle.

A cellular architecture for raster-scanned frame buffer displays is described by Satish Gupta and Robert F. Sproull of Carnegie-Mellon University and Ivan E. Sutherland in "A VLSI Architecture for Updating Raster-Scan Displays" Computer Graphics, Volume 15, Number 3, pp. 333-340, August 1981, also published in Proceedings of SIGGRAPH 81. pp. 71-78, Association of Computing Machinery, 1981. Gupta, Sproull, and Sutherland disclose an 8.times.8 bit cell organization of the frame buffer memory instead of the conventional horizontal word oriented memory organization for accessing the frame buffer by a single two-dimensional 8.times.8 bit cell configuration addressing mode.

According to this cell addressing concept, the frame buffer addressing and control circuits and bit map are designed to permit accessing successive memory address locations of the memory banks in a cell configuration corresponding to a square cell of pixels on the view surface or display screen. The cell configuration rectangle is composed of a similar number of bits or pixels as a horizontal word mode addressing word, for example 64 bits. However the cell addressing configuration viewed on the display screen or viewing surface is two-dimensional. As a result the frame buffer may be updated and a vertical or diagonal vector or two-dimensional character can be drawn in a reduced number of memory access cycles for updating or drawing the required bits and pixels. Vector drawing performance, which conventionally may be limited to one bit or pixel changed or updated per memory cycle, is upgraded to multiple bits or pixels changed or updated per memory access cycle.

The 8.times.8 cell addressing mode permits greater performance in number of pixels updated each memory access cycle when updating the frame buffer for drawing two-dimensional vectors, characters and bit block transfers. A disadvantage of the Gupta, Sproull, and Sutherland system however is that refresh of the display is less efficient than is the case with horizontal word mode addressing because the rectangular addressing mode cell must be used for refresh or display of the contents of the frame buffer across the view surface. Only one line of the 8.times.8 bit cell from each memory access cycle is used for assembling a particular refresh scan line. The Gupta et al. system architecture can achieve only one addressing mode and is constrained by the selected cell configuration and a bit map organization that permits only one addressing mode.

Another cell organized raster display architecture with a single 8.times.8 pixel cell is described by Jordan and Barrett in "A Cell Organized Raster Display for Line Drawings", CACM, Volume 17(2):70, February, 1974 and "A Scan Conversion Algorithm with Reduced Storage Requirements", CACM, 16 (11):676, November, 1973. Further background on computer graphics raster display frame buffer architecture is provided by Foley & Van Dam, Fundamentals of Interactive Computer Graphics, Addison-Wesley Company, Reading, Mass., 1982, Chapters 3, 10 and 12 et. seq. and Newman and Sproull, Principles of Interactive Computer Graphics, Second Edition, McGraw-Hill Book Company, New York, N.Y., 1979, Chapters 15-19. According to Foley and Van Dam the Tektronix 4025 and 4027 (Trademark) displays utilize cell encoding in which memory is allocated by storing cells of 8.times.14 pixels. In these prior references the architecture is limited to one addressing mode with a generally simple or straightforward standard or conventional bit map organization that can accommodate only one addressing mode cell configuration during frame buffer memory access cycles.

In the Texas Instrument TI 34010 Graphics System Processor or GSP, a different number of planes, for example 1, 2, 4, 8 or 16 planes, can be selected. This raster graphics system is therefore capable of defining pixels by different selected number of multiple bits. A different horizontal addressing word is associated with each different selection of number of planes. There are, therefore, different addressing words. A different but standard type bit map is associated with each selection of a different number of planes. However, once the number of planes and corresponding standard bit map is selected only one addressing word or mode is available.

Further discussion of the prior art and state of the art in raster addressing modes is found in applicant's Information Disclosure Statement along with discussion of distinguishing and contrasting features of the present invention. Applicant's Information Disclosure Statement and references cited are incorporated herein by reference.

It is therefore an object of the present invention to provide new and flexible raster graphics architectures and frame buffer bit maps which accommodate multiple different cell and word addressing modes or multiple cell and word configurations for accessing the raster display frame buffer memory locations.

Another object of the invention is to provide frame buffer addressing and control circuits which permit selection from a range of cell or word configuration addressing modes to match a particular image drawing requirement for optimizing performance. The invention capitalizes on the simple geometry of vectors and characters to be drawn or updated when addressing the frame buffer. That is, the new architecture of the present invention is intended to permit selection of the appropriate mode from a plurality of alternative cellular addressing modes to optimize and maximize the number of pertinent bits of the frame buffer bit map and corresponding pixels drawn or updated each memory cycle. By this arrangement the number of memory access cycles is minimized reducing the time required for graphics drawing operations. Optimum use is made of the available memory bandwidth and memory cycle time not required for display screen refresh.

A further object of the invention is to provide multicellular addressing modes including both alternative two-dimensional cells and horizontal words. A feature and advantage of this flexible architecture is that vector drawing performance is dramatically improved with the two-dimensional cellular addressing while preserving the high efficiency of horizontal word access to the frame buffer for refresh of the raster display.

Yet another object of the invention is to provide flexible organization of the frame buffer memory address locations into single and multiple planes adding a flexible third dimension to the bit map while preserving multicellular and word addressing modes for each selection of number of planes. According to this feature the frame buffer architecture effectively accommodates multiple three-dimensional addressing mode cell and word configurations for selectively varying image pixel display definition in color scale, gray scale, resolution, etc.

A related object of the invention is to provide an image creation system and image data generator for raster graphics machines capable of operating in the new flexible addressing raster graphics frame buffer architecture and bit map. The data generator is capable of raster operations on graphics image data accessed according to any of the multiple addressing modes.

In order to accomplish these results and accommodate multiple cell and word addressing modes a highly unusual bit map organization is provided by the present invention. To this end the memory locations and corresponding memory addresses of the frame buffer memory banks are not organized in the conventional row and column arrangement of a standard bit map or SBM corresponding to a simple arithmetic or identity bit map relationship with the user/viewer X,Y coordinate system. Rather the addresses or memory locations of the frame buffer are permuted in an unusual order. The image data frame buffer bit map constitutes a linear permutation or transformation from the simple row and column user X,Y coordinate address arrangement on the display screen or view surface. To visualize the consequences of this permuted order, each memory bank instead of controlling an orderly sequence of columns of pixels on the view surface controls a complex distribution of pixels across the screen comprising a complex linear permutation of the original conventional columns and rows of pixels in the user/viewer X,Y coordinate system.

According to the invention the addressing and control circuits for the frame buffer incorporate logical linear permutation networks or operators for achieving and implementing the unusual organization. The bit map itself is organized as a complex logical linear permutation of the user X,Y coordinate system organization of image pixel address positions on the display surface. The linear permutation operators incorporated into the frame buffer addressing and control circuits store the image data bits in the frame buffer in a permuted or "warped" order constituting a novel permutation bit map or PBM which accommodates the addressing access in alternative multiple cell configuration and word modes. An image data generator circuit is also provided which incorporates logical linear permutation networks and linear permutation operators in order to normalize image data retrieved from the frame buffer in the multiple access modes for performing Boolean operations on image data retrieved from the frame buffer. The unusual permuted or warped order is recreated in processed image data for return to the frame buffer permutation bit map.

An address generating circuit or AGEN with associated address circuitry receives command signals from a host computer, CPU, microprocessor, or programmed graphics processor etc. The AGEN also receives image data address coordinate information in the original user X,Y coordinate system or space corresponding to a standard coordinate space. The AGEN and associated address circuits transform the image data addresses to the permuted or "warped" address space establishing the permuted bit map or novel PBM coordinate space of the frame buffer. The AGEN in turn delivers command words or operation codes to the frame buffer image data generating circuit or DGEN which processes graphics image data retrieved from the permuted bit map for updating the frame buffer memory and for refresh of the raster display.

In implementing the new raster graphics architecture, logical linear permutation networks (LPN's) incorporating self-symmetric reversible logic functions or gates permute the addressing sequence from the user X,Y coordinate space to a permuted frame buffer or PBM memory bank and bank address space, BA. The LPN's are incorporated in both the address circuits and the data generator or image creation circuits. These LPN circuits implement logical or Boolean linear permutation operators or primitives such as exchange and cyclic or rotation LPN operators. So called wire linear permutation network operators or primitives or wire LPN's such as reversal, butterfly, and shuffle LPN operators are also combined with the logical LPN's.

The invention incorporates into the flexible addressing architecture a third dimension in the form of a flexible number of bit planes of organization of the frame buffer along a third Z coordinate. The number of planes selected along the Z coordinate coincides with the number of bits defining each pixel and effectively adds a flexible third dimension or bit depth Z to the bit map and user coordinate system. The three-dimensional user X,Y,Z coordinate system or SBM space is therefore permuted or warped according to the invention to accommodate multiple three-dimensional addressing mode cells and words in a novel three-dimensional PBM space or permutation bit map.

The addresses received at the address generator and associated circuitry in the X,Y,Z user coordinate space are transformed in a preferred example to the physical memory bank and bank address PBM coordinate space in two permutation steps. First the addresses in the user X,Y,Z coordinate space are transformed to an abstract permuted C,U,S address space or bit map composed of three-dimensional block section addresses S representing subdivisions of the three-dimensional address bit map in multiple planes and corresponding subdivisions of a raster view surface encompassing the bit depth dimension. The block sections are in turn subdivided into three-dimensional cells with cell addresses C, each cell comprising memory locations from each of the successive memory banks of the frame buffer accessed in one memory access cycle. The cells are in turn subdivided into units U of image data which in the preferred implementation are units of four bits referred to as quad pixels, one unit derived from each memory bank of the frame buffer memory in a memory access cycle.

This transformation from the user X,Y,Z coordinate space to abstract C,U,S organization coordinate space is accomplished using a novel multiplexing or switch LPN which is actually a logical LPN constructed to operate on more than one index and capable of mixing or multiplexing two or more dimensions of the SBM, PBM, and intermediate address spaces. The intermediate C,U,S bit map address space is in turn translated by further address circuitry incorporating the logical LPN's into concrete memory bank designations B, and memory bank address coordinates A.sub.y and A.sub.z. The A.sub.y coordinate address portion controls vertical access for a single plane mode and the A.sub.z coordinate address portion controls plane selection for address modes with vertical height of one unit, as hereafter more fully developed. The physical memory bank address coordinate space designated B,A.sub.y,A.sub.z having the unusual permuted order and constituting a three-dimensional permuted frame buffer memory or permutation bit map permits memory accessing in any of the desired addressing cell configuration modes.

By way of example, in a single plane bit map with the cell or word size selected and arranged to be 64 bits, the addressing mode cell and word configurations range from the horizontal 64.times.1 refresh word for use in accessing the frame buffer during screen refresh cycles and selected raster operations, to horizontally and vertically oriented cell rectangles, for example 32.times.2 bit, 16.times.4 bit, and 4.times.16 bit cells for updating the frame buffer while drawing vertically and horizontally oriented two-dimensional vectors and characters. A square cell 8.times.8 bit addressing mode is also provided. Furthermore, the cell configurations within blocks may be rearranged and implemented in three dimensions over 2, 4, 8, and 16 planes of depth organization according to the number of bits required to define each pixel, one plane for each bit of the multi-bit pixel.

In implementing the image data generating circuit or DGEN, logical linear permutation networks implementing logical or Boolean linear permutation operator primitives such as exchange or cyclic permutation networks are again required. Wire LPN's such as reversal, butterfly, and shuffle linear permutation networks are also combined with the logical LPN's. For raster operations including raster ops or Bit Blt's, source data retrieved from the frame buffer memory of the Bit Blt or bit block transfer is merged with destination data retrieved from the frame buffer for rewriting in the frame buffer memory after appropriate masking. According to one example embodiment, data retrieved from the frame buffer is normalized, that is, permuted or transformed back to the user X,Y,Z coordinate system or standard coordinate space for performing such raster operations. A pre-permutation operation is therefore implemented by a pre-permutation network including logical LPN's so that the source data and destination data are represented in the same coordinate space. Alternatively, data may be matched for logical operations in either the normalized X,Y,Z coordinate space or in the permuted C,U,S or B,A.sub.y,A.sub.z coordinate spaces. Alignment and masking steps are incorporated as required.

Finally, after merger of matched and aligned source and destination data in a logical function or Boolean logic circuit, a post-permutation or "postnet" operation is performed to return any normalized data to the unusual permuted or PBM address space organization of the frame buffer memory location addresses for rewriting in memory. Overall, DGEN transformations from the physical memory bank address coordinate space B,A.sub.y,A.sub.z to the user X,Y,Z coordinate space are represented by logical LPN functional pre-permutation or prenet transformations X,Y,Z=f(B,A.sub.y,A.sub.z), while the post-permutation or postnet logical LPN operations are the reverse, B,A.sub.y,A.sub.z =f(X,Y,Z).

In the preferred three-dimensional system architecture the intermediate transformation through an intermediate coordinate system between the initial user X,Y,Z coordinate system and the permuted physical memory bank coordinate system B,A.sub.y,A.sub.z represents the organization of the image data bits or pixels or the memory location addresses into blocks, cells, and units. This mode of organization constitutes an important novel and distinguishing feature of the raster graphics system invention. Because there are always at least two different cell or word addressing modes, the alternative cells or words give rise to a new level of organization or subdivision of the bit map and view surface referred to as the "block". The block width is the same as the largest horizontal dimension of the available cell or word addressing modes. The block height is the same as the largest vertical dimension of the available cell or word address modes. The cell size in bits is defined by the product of the horizontal dimension H.sub.i in bits times the vertical dimension V.sub.i in bits of each cell and word in the two-dimensional implementation and is the same for all available addressing mode cells or cell configurations and words. The cell size in bits in two dimensions is therefore equal to H.sub.i .times.V.sub.i, is the same for each word and cell configuration or shape, and is selected on the basis of the overall performance desired, a larger cell size in number of bits giving better performance. Furthermore, the same number of cells for each addressing mode fills out each block without overlap and the block size in two dimensions is H.sub.max .times.V.sub.max where H.sub.max is the largest horizontal dimension, for example 64 bits for the 64.times.1 bit display word, and V.sub.max is the largest vertical dimension, for example 16 bits for the 4.times.16 bit vertically oriented cell. In the multi-plane three-dimensional architecture, the number of planes P is added as a factor in the cell size H.sub.i .times.V.sub.i .times.P.sub.i and block size H.sub.max .times.V.sub.max .times.P. The blocks in each case define boundaries within which all the addressing modes are accommodated in a set of an equal number of cells and within which a set of the same number of cells from each addressing mode form a boundary subset.

In the present invention the frame buffer memory comprises a plurality of separately addressable memory banks for parallel processing. The address circuit addresses each memory bank B of the frame buffer memory in a memory access cycle. Each memory access cycle accesses or generates a single cell and each memory bank contributes a unit of image data, for example a quadbit or quadpixel to each cell. Cell size is therefore related to the number of available memory banks. Block size is related to the number of different addressing mode cell or word configurations and the cell size. The unit of image data retrieved from each memory bank, for example quads of bits, is related in size to the bit width of the memory bank components, for example four bit wide memory banks. The frame buffer address circuit is operatively arranged to receive graphics image data addresses organized in a user X,Y,Z coordinate system of horizontal rows X and vertical columns Y corresponding to the pixel positions on the raster display or view surface. The user X,Y,Z coordinate system includes a bit depth dimension Z corresponding to the planes of the frame buffer memory. The address circuit linear permutation networks (LPN's) transform and permute the graphics image data addresses in the user X,Y,Z coordinate system to addresses in a B,A.sub.y,A.sub.z coordinate system. The B,A.sub.y,A.sub.z coordinate system is a linear permutation of the user X,Y,Z coordinate system, a linear permutation bit map, permuted bit map or PBM addressable by the frame buffer address circuit in at least two different addressing mode cell or word configurations. At least one of the addressing mode cell or word configurations corresponds to a two-dimensional cell in the user X,Y coordinate system, a two-dimensional cell in the user X,Z coordinate system, or a three-dimensional cell in the user X,Y,Z coordinate system. A feature of the invention is that the permuted bit map or PBM can operate in multiple word addressing modes in multiple planes in the X,Z coordinate system when Y the vertical dimension is set at zero. The present invention provides a multiple word addressing permuted bit map in the X,Z coordinate system by changing the number of planes in the same bit map and changing the horizontal dimension of the horizontal addressing and display word. This feature of the invention provides permuted bit maps for multiple word and multiple cell addressing modes with reference to either the X,Y coordinate system, X,Z coordinate system, or X,Y,Z coordinate system of the user.

In the preferred examples, the linear permutation networks comprise at least one Boolean or logical linear permutation network (LPN) incorporating self-symmetric reversible Boolean logic functions or gates. A feature and advantage of this arrangement is that there is a reversible one-to-one relationship between input and output so that graphics image data cannot be lost. The designated memory bank B in the B,A.sub.y,A.sub.z coordinate system is a function of X,Y,and Z in the X,Y,Z coordinate system having a functional relationship of the form:

where f.sub.1 and f.sub.2 are functions comprising logical linear permutation networks, for example an exchange linear permutation network, E.sub.p. For optimum flexibility, f.sub.2 comprises an exchange LPN, E.sub.p, and a reversal LPN, R.sub.p. Specifically, in the preferred embodiment B is the following function of X,Y and Z:

where S.sub.p is the shuffle wire LPN, R.sub.p is the reversal wire LPN, and wherein sm is related to the selected permutation bit map or PBM referred to as the static addressing mode set or static mode hereafter described and defined.

The memory bank cell address locations A.sub.y in the B,A.sub.y,A.sub.z coordinate system may generally be a function of Y in the X,Y,Z coordinate system having a functional relationship of the form:

where f.sub.3 comprises a wire linear permutation network, for example a reversal LPN, R.sub.p. Specifically, in the preferred embodiment A.sub.y a function of Y in the form:

The frame buffer bit plane addresses A.sub.z may be a function of Z in the X,Y,Z coordinate system having a functional relationship of the form:

These functional relationships of logical linear permutations from X,Y,Z to B,A.sub.y,A.sub.z or from the image pixel space to the PBM are implemented in the frame buffer address circuits AGEN and in the "postnet" or post-permutation circuit of the DGEN. Conversely, the reverse functional relationships permuting and normalizing from the PBM B,A.sub.y,A.sub.z coordinate space to an X,Y,Z coordinate space are implemented in the "prenet" or pre-permutation circuit of the DGEN as follows:

The linear permutation transformation from the user X,Y,Z coordinate system bit map to the frame buffer memory address B,A.sub.y,A.sub.z coordinate system permuted bit map may be accomplished as explained above in two steps of linear transformations. A first linear permutation network function transforms and permutes the graphics image data addresses in the user X,Y,Z coordinate system to addresses in an abstract C,U,S coordinate system of three-dimensional multi-plane block sections S, cell subdivisions C of the block sections corresponding to the addressing mode cells, and graphics image data units U, each cell comprising an equal number of data units. The C,U,S coordinate system forms a first linear permutation bit map or first permuted bit map. The first linear permutation network functional relationship is of the form:

where f includes the switch linear permutation network Q.sub.p. Specifically, the cell address C, unit address U, and third dimension block section address S are given by the following functions of the switch or multiplexing LPN Q.sub.p :

where h and p are address mode selection parameters in which h is the logarithm to the base 2 of the horizontal dimension H of the selected word or cell addressing mode in units of 4 bits, quadbits, or quads, p is the logarithm to the base 2 of the selected number of planes, v is the logarithm to the base 2 of the vertical dimension V of the selected word or cell addressing mode in units of bits, and L=h+v+p for the selected addressing mode. L is the logarithm to the base 2 or Log.sub.2 of the number of logical memory banks and also the number of units U in a cell C.

A second linear permutation network transforms and permutes the graphics image data addresses in the abstract C,U,S coordinate system to memory bank addresses in the B,A.sub.y,A.sub.z coordinate system of designated memory banks B, memory bank address locations A.sub.y, and the third dimension memory bank bit plane addresses A.sub.z of the frame buffer memory. The functional relationship of the second transformation and linear permutation is of the form:

where g also includes the logical LPN's for the final transformation to B and the switch linear permutation network Q.sub.p for the final transformation to A.sub.y and A.sub.z Each of the first and second linear permutation network transformations of the two-step process further include wire LPN's. Specifically, the memory bank designation B and bank cell address locations A.sub.y and A.sub.z are given by the following linear permutation operations, where B is essentially the same functional permutation of C,U,S as it is of X,Y,Z:

and A.sub.y and A.sub.z are functions of the switch or multiplex LPN, Q.sub.p :

The data generator circuit is operatively coupled to the frame buffer address circuit and frame buffer memory for updating the frame buffer with vector drawing, polygon filling, and raster operations and for refresh and display of the raster display or view surface with the graphics image data contents of the frame buffer memory. Because of the permuted bit map established in the frame buffer memory bank address locations by the address generator and address circuits of the invention, the data generator circuit is provided with a first prenet or pre-permute linear permutation network. The pre-permute LPN provides selected transformation and linear permutation of graphics image data accessed from the frame buffer memory in the permuted B,A.sub.y, A.sub.z coordinate system or PBM space to the user X,Y,Z coordinate system or standard space thereby normalizing graphics image data accessed from the frame buffer for raster operations. Whereas the AGEN and address circuits operate on addresses or indices only, the DGEN LPN circuits operate directly on the data. A second postnet or post-permute linear permutation network is also provided in the data generator circuit. The post-permute LPN provides transformation and linear permutation of processed graphics image data remaining in the normalized user X,Y coordinate system or standard space to the permuted B,A.sub.y,A.sub.z coordinate system or PBM space of the frame buffer memory bank address locations for return to the frame buffer memory permutation bit map.

The pre-permute or prenet and post-permute or postnet LPN's are essentially the same logical linear permutation networks used in the address generator and associated address circuitry. The logical LPN's are self-symmetric and reversible incorporating reversible Boolean logic gates such as XOR and XNOR gates. These gates are assembled to form, for example the exchange linear permutation networks E.sub.p and reversal exchange networks E.sub.p R.sub.p as hereafter described for use in the address generator and associated address circuitry and data generator circuitry. The self-symmetric properties and reversible operative characteristics of the logical LPN's permit reversible transformation and permutation back and forth between the normalized user X,Y,Z coordinate space and standard bit map and the unusual permuted B,A.sub.y,A.sub.z coordinate space and permuted bit map. Essentially the same logical linear permutation networks are incorporated in both the AGEN and associated address circuitry and the DGEN. While the address circuit LPN's operate on the indices or addresses only, the DGEN LPN's operate selectively directly on the data for performing raster operations, Bit Blt's, and polygon fills on graphics image data retrieved from the PBM space of the permuted bit map.

The invention thus contemplates a new method for graphics image data generation for updating frame buffer memory bank address locations A in the memory banks B of a frame buffer memory in a raster graphics machine and in particular for raster operations. Referring to a general two-dimensional implementation, the steps of the method are as follows: organizing the frame buffer memory bank address locations into a permuted or warped bit map by receiving graphics image data addresses in the user X,Y coordinate system and transforming and permuting the addresses from the user X,Y coordinate system through linear permutation networks to a permuted B,A coordinate system or PBM space of designated memory banks B and memory bank address locations A; retrieving graphics image data from the frame buffer memory bank address locations in the permuted B,A coordinate system or PBM space for processing in raster operations: pre-permuting and normalizing the order of retrieved graphics image data from the permuted B,A coordinate system to the normalized user X,Y coordinate system or standard space through pre-permute linear permutation network means for matching source data with destination data during raster operations; post-permuting graphics image data remaining in the normalized user X,Y coordinate system after processing in raster operations to the permuted B,A coordinate system or PBM space through post-permute linear permutation network means: and returning the graphics image data in the permuted B,A coordinate system to the frame buffer memory bank address locations thereby completing raster operations in the permuted bit map or PBM space.

The invention also contemplates new methods for vector drawing in the PBM space of the permutation bit map and for refresh of a raster display using display words retrieved from the frame buffer permutation bit map. Operations of the AGEN and associated address circuits with the DGEN including its data path section, vector and mask section, and video section are fully integrated for operation between SBM and PBM coordinate spaces or systems. The invention also contemplates extending the new methods to a user X,Y,Z coordinate system of a multiplane bit map and logically permuting the X,Y,Z standard bit map in three dimensions to a three-dimensional permutation bit map or PBM addressable and accessible by a variety of three-dimensional word and cell configuration addressing modes. Data path manipulations are carried out on graphics image data retrieved from the multiplane PBM's accessed by addressing mode variable not only in horizontal and vertical bit dimensions but also in bit plane depth dimension, i.e. variable in number of planes.

A variety of alternative methods and hardware embodiments are contemplated by the invention for implementing the new flexible addressing frame buffer architecture, image data creation and generation system, and frame buffer addressing and control circuits. The features and advantages of these embodiments of the invention are set forth in the following specification and accompanying drawings and tables.

FIG. 1 is a general block diagram of a raster graphics machine incorporating the image creation system and frame buffer controller of the present invention including the data generator or DGEN, the address generator or AGEN, and further frame buffer memory addressing circuitry.

FIG. 2 is another general block diagram configuration of the raster graphics machine with the frame buffer memory organized in multiple planes.

FIG. 3 is a diagram of block and cell organization of the frame buffer memory bank address locations according to one example of the present invention corresponding to a block subdivision of the view surface with multiple addressing mode cells or cell configurations for accessing the frame buffer memory bank address locations.

FIGS. 4A, 4B and 4C are diagrams of the block of the frame buffer memory bank address location showing access to the block according to three different addressing mode cells or cell configuration.

FIG. 5 is a circuit diagram for implementing the cyclic logical LPN operator C.sub.p for operation on address or index bits in address space.

FIG. 6 is a circuit diagram for implementing the multiplexing switch hybrid LPN operator Q.sub.p while FIG. 6A is a detail of the 2-to-1 selector switch.

FIG. 7 is a circuit diagram for implementing the exchange logical LPN operator E.sub.p for operation on address or index bits in address space.

FIG. 8 is a circuit diagram for implementing the reversal wire LPN operator R.sub.p for operation on address or index bits in address space.

FIGS. 9A, 9B, and 9C present circuit diagrams for implementing the shuffle wire LPN operator S.sub.p, while FIG. 9D is a circuit diagram for a combinational implementation of R.sub.p and S.sub.p.

FIGS. 10 and 10A are a diagrams illustrating the fundamental theorem of linear permutation network theory and the mutual derivability and transformation in three dimensions between the X,Y,Z: C,U,S: and B,A.sub.y,A.sub.z coordinate spaces and in two dimensions between the X,Y: C,U: and B,A coordinate spaces.

FIG. 11 (parts 1 and 2) is a general block diagram and flow chart of the address and data path components showing the mapping flow of address data and graphics image data between the address generator or AGEN, address logic circuits, frame buffer memory banks, and data generator or DGEN.

FIG. 12 (parts 1 and 2) is a general block diagram of the address generator or AGEN for processing graphics image data received in the user X,Y, Z coordinate system.

FIG. 13 is a pin description block diagram for the address generator chip showing the AGEN pinouts.

FIG. 14 (parts 1 and 2) is a block diagram of the cell address generation section of the address generator or AGEN.

FIG. 15 is a block diagram and flow chart of the refresh word cell address generation section of the AGEN.

FIG. 16 is a block diagram and flow chart of the data generator or DGEN.

FIG. 17 is a pin description block diagram of the data generator chip showing the DGEN pinouts.

FIG. 18 is a generalized block diagram of a logical linear permutation network incorporating exchange logical linear permutation operators E.sub.p for operating on data in the DGEN in data space and for implementing the fundamental equation of the best mode PBM.

FIG. 19 is a detailed logic circuit of a linear permutation exchange element of FIG. 18 for operating on data bits in the data space.

FIG. 20 (parts 1 and 2) is a data flow chart showing flow of data between standard and PBM coordinate spaces in the DGEN during Bit Blt's or bit block transfers and polygon fill graphics operations.

FIG. 21 is a data flow chart showing flow of graphics image data between standard and PBM coordinate spaces in the DGEN during vector drawing operations.

FIG. 22 is a data flow chart showing flow of data during vector operations all in standard space or all in PBM space in an alternative implementation of the DGEN.

FIG. 23 is a data flow chart showing flow of graphics image data between standard and PBM coordinate spaces during refresh of the raster display.

FIG. 24 is an alternative general block diagram and flow chart of the address and data path components showing the mapping flow of address data and graphics image data between the AGEN and address logic circuits, frame buffer memory banks, and DGEN and data path components.

Table 1 is a table of one block of a cyclic permutation bit map showing the permutation and assignment of memory banks in the permuted B,A coordinate system relative to the view surface pixel positions in the user X,Y coordinate system using a cyclic linear permutation network or rotator to achieve one example architecture which accommodates multiple addressing mode word or cell configurations.

Tables 2, 3, and 4 are tables defining the cyclic logical linear permutation network C.sub.p, the multiplexing switch hybrid linear permutation network Q.sub.p, and the exchange logical linear permutation network E.sub.p respectively used in executing linear permutation operations for establishing for example the cyclic permutation bit maps and cyclic PBM embodiments of the present invention.

Tables 5 through 8 are tables of blocks of the reversal exchange or exchange and reversal permutation bit map according to the invention showing the respective cell configuration addressing modes as respective partitions of the exchange and reversal permutation bit map block.

Table 9 is a table defining the reversal wire LPN, R.sub.p used in combination with, for example the exchange logical LPN E.sub.p for establishing the reversal exchange or exchange and reversal permutation bit map of the present invention.

Table 10 is a summary of the multicellular addressing modes of the respective static modes for the optimum double exchange shuffle and reversal permutation bit map implemented by combinatorial linear permutation operations on address bits or index bits by at least two exchange logical LPN's E.sub.p and two wire LPN's, the shuffle LPN S.sub.p and the reversal LPN R.sub.p.

Tables 11 through 25 are tables of blocks of three-dimensional double exchange shuffle and reversal permutation bit maps according to the invention partitioned to show selected ones of the multiple three-dimensional cell configuration addressing modes for selected static modes. Tables 11 through 15 are each single partitioned blocks showing different selected cell configuration addressing modes AM in one plane for static mode sm=0. Tables 16 through 19 are each partitioned blocks showing selected different three-dimensional cell configuration addressing modes AM in two planes for static mode sm=1. Tables 20 through 24 are each multiple partitioned blocks showing selected different three-dimensional cell configuration addressing modes AM in four planes for the static mode sm=2. Table 25 is a multiple partitioned blocks showing a selected three-dimensional cell configuration addressing mode AM in eight planes for the static mode sm=3.

Table 26 is a table of the fundamental equations defining the frame buffer architecture, addressing circuits, data generator circuits, and linear permutation networks for transformation between the user X,Y,Z coordinate system, abstract cell, unit and block section C,U,S, coordinate system, and the memory bank address B,A.sub.y,A.sub.z coordinate system; and Table 26A is a table of the fundamental equations using alternative symbolism.

Table 27 is a table defining the shuffle wire LPN, S.sub.p, used in combination with the exchange logical LPN, E.sub.p, and the reversal wire LPN, R.sub.p, for establishing the best mode three-dimensional double exchange shuffle and reversal permutation bit map of the present invention.

Table 28 is a table of the frame buffer memory bank address equations and address connections in the three-dimensional universal implementation of the invention.

Table 29 is a table of the valid dynamic cellular addressing modes AM for each different multiple plane static addressing mode sm.

Table 30 is a table of the functional permutation and correlation between the C,U,S address or index bits and the X,Y,Z index bits for the different dynamic addressing modes AM in static mode sm=0.

Table 31 is a table of the corresponding external address line equations of the frame buffer memory bank address locations for different addressing mode cell configurations in static mode sm=0.

Table 32 is a table of the functional permutation and correlation between C,U,S address or index bits and X,Y,Z index bits for the different addressing modes AM in static mode sm=1.

Table 33 is a table of the corresponding external address line equations of memory bank address locations for the different addressing mode cell configurations in static mode sm=1.

Table 34 is a table of the functional permutation and correlation between the C,U,S address or index bits and X,Y,Z index bits for the different addressing modes AM in static mode sm=2.

Table 35 is a table of the corresponding external address line equations of memory bank address locations for different addressing mode cell configurations in static mode sm=2.

Table 36 is a table of the functional permutation and correlation between C,U,S address bits or index bits and X,Y,Z index bits for the different dynamic addressing modes AM in static mode sm=3.

Table 37 is a table of the corresponding external address line equations of the memory bank address locations for the different addressing mode cell configurations in static mode sm=3.

Table 38 is a table of the functional permutation and correlation between C,U,S address or index bits and X,Y,Z index bits for the different dynamic addressing modes AM in static mode sm=4.

Table 39 is a table of the corresponding external address line equations of memory bank address locations for the different addressing mode cell configurations for static mode sm=4.

Table 40 is a table list of the AGEN pinout signal descriptions corresponding to the pinout abbreviations in FIG. 13.

Table 41 is a table list of the DGEN pinout signal descriptions corresponding to the pinout abbreviations of FIG. 17.

Table 42 is a table of cell address equations in Boolean format for formulating the cell address lines, circuits and connections corresponding to the cell address lines CA of FIG. 24.

A general system block diagram of a raster graphics system 10 implementing the graphics architecture of the present invention is illustrated in FIG. 1. The frame buffer memory 12 is provided by an array of physical memory banks or components, for example at least eight physical memory banks, with a bit width of, for example, 4 bits, to support the novel permutation bit map.

In the detailed example hereafter described, the frame buffer memory is provided by eight physical memory banks "time sliced" twice each memory access cycle. The two "pulls" from each physical memory bank each memory cycle thereby provide sixteen effective or logical memory banks. The sixteen effective memory banks constitute sixteen permutation "objects" for the novel logical linear permutation operators or networks incorporated in the addressing and data path circuits.

By way of example, each memory bank is composed of four integrated circuit RAM chips providing memory banks four bits wide with four input/output lines having the same address. During a memory access cycle graphics image data units U of four bits, referred to as quads, quadbits, or quadpixels, are pulled from the memory banks. Time slicing pulls two quads from each of the eight physical memory banks, or one quad from each of the sixteen effective or logical memory banks each memory access cycle. The memory addressing word or cell is therefore composed of 16 quads or 64 bits. The data path system components are designed to accommodate the 64-bit words for example by multiplexed 32-bit data paths. Thus each 64 bit word is composed from two interleaved 32 bit words or "pulls".

If the frame buffer is composed of dynamic RAM's or DRAM's, a dynamic RAM controller or DRAMC 14 may be required for DRAM cell refresh. Alternatively, the address generator trace may perform this function.

The address generator or AGEN 15 executes graphics instructions received on the ICODE line from the programmable graphics processor or PGP 16 which may alternatively be a host or system CPU, and acknowledges instruction requests on the BUSCODE lines. The AGEN 15 generates appropriate addresses for the frame buffer in response to instruction requests on the address lines or AD lines and on the address bus or ADBUS 18 which is for example a 32 bit bidirectional bus for addressing the frame buffer 12 through additional addressing logic circuits 20. The addressing logic circuits 20 include an address buffer latch and logic gates to drive four unique bank address lines to the sixteen logical memory banks (eight physical memory banks time sliced twice). The AGEN 15 and associated addressing logic 20 together establish and implement the permutation bit map as hereafter described. The AGEN 15 also delivers instruction sequences in the form of data operation codes or DOP codes on the DOP line to the data generator or DGEN 22.

The data generator 22 is the data path component comparable to a bit block transfer chip or Bit Blt chip for receiving instruction sequences from the AGEN 15 and executing graphics operations on graphics image data accessed from the frame buffer corresponding to the address sequences generated by the address generator. The graphics operations executed by the DGEN 22 in combination with AGEN 15 include vector drawing or vector addressing from relative or absolute positions, raster ops or bit block transfers known as Bit Blt's, polygon fill, character drawing, stripe sequencing, etc., and refresh of the raster display. 64-bit graphics image data words or cells are transferred to and from the frame buffer 12 in multiplexed--32-bit words on the data lines or D lines and data bus 24 for example a 32 bit bidirectional bus also referred to as the DBUS or MBUS 24 under addressing control of the AGEN 15.

The graphics image data resides in the memory banks of the frame buffer in the permuted order established by the address generator. This permutation bit map accommodates multiple word and cell addressing modes. The DGEN 22 is constructed and arranged to execute graphics data operations and carry out data path manipulations on graphics image data received in the unusual permuted order of the permutation bit map established by AGEN. The DGEN is provided with logical linear permutation operators for normalizing data and for returning data to the unusual permuted order after completion of data path manipulations for return to the frame buffer permutation bit map. While the logical linear permutation operator circuits or networks of the AGEN operate on the indices or addresses of the graphics image data, the corresponding logical LPN circuits of the DGEN operate directly on the data objects. The DGEN networks and circuits are capable of transforming the graphics image data organization between the user X,Y or X,Y,Z coordinate system corresponding to a standard bit map or SBM space and the memory bank and bank address coordinate space corresponding to the permutation bit map coordinate system or PBM space according to the requirements of the particular graphics data operation or data path manipulation. The data path manipulations including masking, alignment, and logical operations required for example for vector drawing, Bit Blt's, and polygon fills are appropriately arranged according to the SBM or PBM coordinate space of the data words.

The DGEN 22 also prepares display words for refresh of the CRT display 25 on the video output lines or VID lines. The DGEN 22 includes a FIFO interface for assembly of display words and carries out the first level of video shifting. Video shift registers 26 are included when required for higher band widths, for example band widths higher than 40 MHz. The first level of video shifting performed in the data generator 22 accommodates and adjusts for the permuted order of display addressing mode words received from the frame buffer permutation bit map for assembling normalized sequences to control the video scan lines. This shifted video data may be used directly with a color lookup table (LUT) and digital-to-analog converter (DAC) for refresh of the CRT display 25. The video sync generator 28 controls the display timing and the request for refresh cycles from the AGEN 15.

The AGEN 15 and DGEN 22 and respective ADBUS 18 and MBUS 24 are split by a bus transceiver 30. The bus transceiver 30 allows concurrent addressing of frame buffer memory banks with simultaneous data transfers between DGEN and the frame buffer memory banks. Bus transceiver 30 also allows concurrent loading of the next instruction data during execution of the current instruction. This split arrangement for concurrency of addressing and data transfers is referred to as "Harvard" architecture. A second bus transceiver 32 provides concurrent isolation of the AGEN 15 and the PGP bus 34. The bus transceivers 30 and 32 therefore result in a three-stage hierarchical data pipeline having constant information bandwidth but increasing bit bandwidth with the programmable graphics processor 16 constituting the first stage. PGP 16 breaks down geometric objects from the data base of a system CPU into high level geometric primitives along with the necessary transforms for converting or generating position information in the user X,Y or X,Y,Z coordinate system. The AGEN 15 and DGEN 22 constitute the second stage converting the position data to a bit stream of pixels for frame buffer storage while the refresh display constitutes the third stage. It is in the second stage of converting the position data to a bit stream of pixel data that AGEN and DGEN permute the order to establish novel two and three-dimensional PBM's in the frame buffer.

Other components of the general system include a system clock which delivers, for example, 40 MHz clock signals on the ICLK lines to drive the AGEN 15 and DGEN 22 instruction execution sequences and provide other system timing requirements. A pixel processor 36 may be added to implement occlusion algorithms and color shading.

A further block diagram of the raster graphics system showing a multiplane embodiment of the present invention is illustrated in FIG. 2. Components similar to those of the block diagram of FIG. 1 are designated by the same reference numeral. This more complete block diagram shows more clearly the hierarchical pipeline organization contemplated by the present invention. In this example the host or system CPU on CPU bus 38 incorporates a database of an instantiation hierarchy of abstract symbols which are broken down into high level geometric objects by database traversal. The high level geometrical objects are broken down into the high level geometric primitives by the programmable graphics processor PGP 16 as heretofore described, enhanced by local memory 40 and optional user interface peripherals 42. The PGP 16 is isolated from the CPU bus 38 by bus transceiver 44. The further stages of the hierarchical data pipeline are as described above.

In the system example of FIG. 2 the frame buffer memory banks 12 are partitioned or organized into N planes 50, 51 . . . 50N. In the block diagram of FIG. 2 it is contemplated for example that the set of memory banks 12 and data generator or DGEN 22 be duplicated for each plane of the frame buffer memory. The planes of the frame buffer memory represent the number of bits defining each pixel and constitute a third depth dimension or Z coordinate of the user/viewer coordinate system. Alternatively, the same set of memory banks comprising the frame buffer memory may be partitioned and organized into N multiple planes, each plane cutting across all of the eight physical memory banks or sixteen logical memory banks. In this instance and the detailed example hereafter described, a single data generator or DGEN component 22 may execute the data path manipulations for all planes. The memory controller 46 provides necessary dynamic memory refresh and may also incorporate supplemental addressing logic gates or circuits 20 associated with the operation of the address generator or AGEN 15. The address generator may be supplemented with a pixel processor 36. The AGEN 15 and DGEN 22 are capable of driving a 320 MHz monitor 25 for resolutions up to for example 2,048.times.2,048 pixels.

At the system block diagram level of FIGS. 1 and 2 the raster graphics system of the present invention resembles presently available raster graphics machines and work station graphics architectures. The subtle differences of the present invention lie within the address generator or AGEN 15 and associated address logic circuitry and within the data generator or data path component DGEN 22. While the AGEN 15 at the system block diagram level appears to be a conventional address generator, it incorporates either internally in the AGEN or both internally in the AGEN and externally in associated address logic circuitry 20 logical linear permutation networks, operators, or circuits hereafter described which permute the graphics image data addresses to establish in the multibank frame buffer memory novel permutation bit maps which may be accessed and which accommodate a variety of different word and cell configuration address modes. Similarly, while the DGEN appears in a capacity similar to a conventional data path chip or Bit Blt chip, it also incorporates the logical linear permutation networks, operators, or circuits in order to process and manipulate graphics image data retrieved from the frame buffer permutation bit map in the unusual permuted order. The DGEN according to the present invention provides a variety of strategies for handling data received in the unusual permuted order and carrying out the necessary graphics operations of for example vector drawing, polygon filling, 64-bit horizontal word block transfers, and image refresh and display.

The multicellular addressing capability inherent in the permutation bit maps or PBM's of the present invention contrast with the conventional standard bit maps or SBM's closely associated with the user/viewer X,Y or X,Y,Z coordinate system. The conventional SBM's are capable of being addressed or accessed in only one addressing mode whether by one-dimensional word or two-dimensional cell. The multicellular addressing capability of the present invention is illustrated in the diagrams of FIGS. 3 and 4 showing a block or subdivision of the raster display view surface also corresponding to the novel block organization of the permutation bit map of the frame buffer. The block organization concept is fundamental to the present invention, the consequence of the coexistence or concurrency of multiple cell addressing modes. The block or block section is the smallest rectangular subdivision of the raster display view surface in which all of the different addressing mode cells and words form equal boundary subsets. An equal number of cells or words from each of the different addressing modes fill out the block without overlap.

Referring to FIG. 3 there is shown a novel block 60 according to the present invention which may be understood as representing a rectangular subdivision or portion of a raster display view surface, for example a CRT screen, in the user/viewer two-dimensional X,Y coordinate system space. As hereafter more fully described with reference for example to Table 1 and subsequent tables the block 60 also represents an abstract subdivision organization of the memory banks and memory bank address locations of the frame buffer permutation bit map in PBM space. An important feature of the present invention and system embodiment is that the block 60 concept is transferable and carries over between the user X,Y coordinate system and the permuted B,A coordinate system, that is between the standard coordinate space and the permuted PBM coordinate space. This transferable block organization principal arises solely because of the concurrency of multiple addressing mode cells and words and is entirely novel originating with the present invention.

In the system example described above the addressing word and cell size is 64 bits, composed of 16 quads, quadbits or quadpixels, 1 contributed by each of the 16 effective or logical memory banks each memory access cycle. In the example of FIG. 3 the block 60 may be interrogated or accessed by either of 3 addressing mode cells. The 64.times.1 bit cell 62 is basically the horizontal word addressing mode used in accessing the frame buffer memory for refresh of the CRT screen. The 64.times.1 bit horizontal words 62 is also used according to the present invention for example for Bit Blt's and polygon filling. The 16.times.4 bit cell 64 represents a two-dimensional cell larger in the horizontal dimension and therefore useful according to the invention for accessing the frame buffer memory to update the frame buffer for example for drawing horizontally oriented vectors. The 4.times.16 bit cell 66 is another two-dimensional cell addressing mode but larger in the vertical dimension and therefore useful according to the invention for accessing the frame buffer and updating the frame buffer by drawing vertically oriented vectors. It is apparent that the dimensions of block 60 are set by the maximum dimensions of the respective addressing mode cells 62, 64 and 66. The horizontal dimension of block 60 is equal to the maximum of the horizontal dimensions of the addressing cells, namely the 64 bit horizontal width of the one-dimensional 64.times.1 bit display word 62. The vertical dimension of block 60 is the maximum vertical dimension of the addressing cells namely the 16 bits of vertical height of the 4.times.16 bit vertically oriented cell 66. The overall dimension of block 60 is therefore 64.times.16 bits. A display surface or view surface having a resolution of for example 1024.times.1024 pixels would be composed of approximately 1000 or exactly 1024 blocks, 16 blocks across in the horizontal X direction and 64 blocks down in the vertical Y direction. A display surface or view surface having a resolution of 2048.times.2048 pixels would be composed of 32 blocks across in the X coordinate direction and 128 blocks down in the vertical Y direction for approximately 4000 or exactly 4096 blocks.

Referring further to FIG. 3, each of the horizontal word mode cells 62 is composed of 16 horizontally oriented quadpixels 61 arranged in a single row. Each quadpixel or quad 61 is in turn composed of 4 bits 63 arranged in a horizontal row. In the case of a single plane frame buffer each pixel is defined by a single one of the bits 63. The horizontally oriented two-dimensional addressing mode cell 64 is also composed of 16 quads 65 in this instance arranged in 4 columns and 4 rows of quads 65. Each quad is arranged as a horizontal row of 4 bits. The vertically oriented two-dimensional addressing mode cell 66 is composed of 16 quadpixels 67 arranged in a single vertical column. Each quad is also composed of 4 bits in a horizontal row. The basic unit U of the block geometry in the preferred examples is the horizontally oriented quad, although the basic unit of data could also be a bit or other multiple bit configuration. Each of the three illustrated addressing mode cells is composed of 16 of the units U or quads and therefore 64 bits and the geometry of the cells is in part determined by the 64 bit cell size and the data units U of quads arranged as horizontal units of 4 bits. The dimensions or boundaries of the block 60 are then determined.

As shown in FIGS. 4A, 4B and 4C the block is the smallest subdivision of the X,Y coordinate system view surface in which all of the different addressing mode cells coincide at the boundaries with the same number of cells. In FIG. 4A, 16 of the one dimensional horizontal word mode cells 62 fill out and access all of the bits or pixels of the block 60 without overlap. The 16 horizontal words or cells 62 in effect form a single column filling the block. In FIG. 4B, 16 of the horizontally oriented two-dimensional addressing mode cells 64 access all of the bits or pixels filling out block 60 with four columns and four rows of the cells without overlap. In FIG. 4C 16 of the vertically oriented two-dimensional addressing mode cells 66 access all of the bits or pixels of block 60 without overlap. The 16 cells 66 in effect form a single row filling out the block. In each instance the block size of 64.times.16 bits or 1024 bits is the same and there is no redundancy or overlap in the cell coverage of the block. In other words, each set of addressing mode cells forms a boundary subset of the block.

The carryover of the block level of organization from the user/viewer X,Y coordinate system or standard space to the permutation bit map, permuted PBM space, or B,A coordinate system of the frame buffer of the present invention is illustrated in the example of Table 1 which represents a block corresponding to the blocks of FIGS. 3 and 4. The 16 effective or logical memory banks identified by 16 hexadecimal digits 0 through F are the permutation objects presented in permuted order with reference to the pixel X and Y coordinates of the corresponding block portion or subdivision of the user raster display view surface. In the convention of Table 1 and the subsequent tables and specification the X coordinate is the horizontal coordinate increasing from left to right. The Y coordinate is the vertical coordinate increasing from top to bottom. In Table 1 the X coordinates are presented in the fundamental data units U of quads from 0 to 16 quads expressed in hexadecimal digits 0-F so that the bit dimension of the X coordinate axis is actually 64 bits, but 16 quads or data units U. This is because the quads are always horizontally oriented comprising units of 4 bits in a horizontal row. The Y coordinate is expressed in units of bits with the Y coordinate dimension extending from 0 to 16 expressed in hexadecimal digits 0-F because the basic data units U or quads have a vertical dimension of one bit only. Thus, the block size represented by Table 1 remains 64.times.16 corresponding to the block of FIGS. 3 and 4 with a distortion or compression of the actual horizontal width because the X coordinate positions are in quad units.

Within the body of Table 1 are presented the assignments of the 16 logical memory banks B to pixel positions on the view surface identified by the first hexadecimal digit in each pair of digits in the permuted order of a cyclic permutation bit map representing one example embodiment of the invention. Each of the 16 memory banks contributes 1 quad or unit to each addressing mode word or cell and a total of 16 quads or units to the block. Each memory bank is therefore provided with 16 bank addresses A which correlate with cell addresses C for each block. While the bank address assignment A for a particular pixel or pixel position remains invariable, the correlated cell address C of the pixel changes according to the selected addressing mode cell configuration as hereafter further described. Once the block address and addressing cell mode have been specified, only the memory bank B and memory bank address A or cell address C needs to be specified for each pixel or quadpixel position on the view surface. The bank address A or cell address C is the second hexadecimal digit in each pair of digits and one possible example of an arbitrary assignment of bank cell addresses is shown in the body of Table 1. Each memory bank B is interrogated or accessed each memory access cycle at an address A and the 16 memory bank and bank cell addresses B,A produce one addressing mode cell.

In a standard bit map the succession or order of memory bank assignments across each row would be the same orderly sequence of columns from 0 to F with the standard bit map bearing a simple functional arithmetic relationship to the X,Y coordinate system amounting to a substantial identity. As is apparent in Table 1, the memory bank assignments of the present invention appear in a permuted order. The memory banks control or determine the graphics image data value at pixel locations across the block subdivision of the view surface in an arrangement amounting to a complex linear permutation of the X,Y coordinate system. For example memory bank 9 delivers 16 quadpixels to the block for controlling the graphics image pixel values in a complex array across the block which cannot easily be characterized by initial study. As hereafter presented this functional relationship is a complex logical linear permutation that enables the three different addressing mode cells to access the entire block without redundancy or overlap.

As shown in Table 1 three example addressing mode cells are outlined corresponding approximately to the three cells appearing on the block of FIG. 3. The dimensions of Table 1 are however distorted from the actual dimensions of a block of the view surface as appearing in FIG. 3 because of the quads appearing in Table 1 identified by hexadecimal digits which actually have a horizontal breadth or dimension of 4 bits. Table 1, if presented in true scale corresponding to the view surface, would be four times wider in its horizontal dimension therefore coinciding with the block of FIG. 3. Examining for example the deployment of the horizontal refresh cell 62 on the memory bank Table 1, in each of the 16 horizontal word cells that would fill Table 1, each of the 16 memory banks is represented contributing 1 quadpixel and there is no redundancy or overlap. Similarly deploying the vertically oriented 4.times.16 bit cell at 16 locations across Table 1 would result in 16 vertically oriented two-dimensional cells in each of which the 16 memory banks are represented contributing a quadpixel without overlap or redundancy. Finally deploying the horizontally oriented two-dimensional addressing mode cell 64 across the memory bank assignments of Table 1 would produce 16 cells in each of which all of the 16 memory banks are represented contributing 1 quadpixel without redundancy or overlap.

It is apparent that the permutation bit map of Table 1 has so arranged the assignment of memory banks and bank cell address locations to pixel positions on the screen so that three different addressing mode cell configurations may be accommodated. It is in this respect that the present invention greatly increases performance over standard bit map machines. In the system of the present invention up to 16 pixels of for example a vertically oriented vector may be drawn each interleaved memory cycle accessing a 16 quad or 64 bit cell. The cell can be selected to optimize the number of pixels updated according to whether the vector is horizontally or vertically oriented. For arbitrary angle vectors the multicellular addressing mode architecture of FIGS. 3 and 4 and Table 1 still delivers an average performance of at least 6 pixels updated per memory access cycle in contrast to the one pixel updated per memory access cycle characteristic of standard bit map machines. The present invention thus increases vector drawing speeds by a factor of 5 to 10 times that of conventional standard bit map systems.

The cyclic linear permutation network PBM represented in Table 1, while a vast improvement over standard bit maps, is nevertheless a suboptimal embodiment of the present invention. It is presented to illustrate minimum requirements of the present invention for achieving multicellular addressing modes. In particular, the frame buffer must be composed of multiple memory banks with separate unique addresses, the memory banks constituting "permutation objects" of linear permutation networks incorporating at least one logical LPN. The number M of logical memory banks is a power of 2, and in the following example M=16. The logical linear permutation network or operator which implements the cyclic PBM of Table 1 is the rotation or cyclic linear permutation network or operator C.sub.p. The functional definition of the LPN operator C.sub.p is presented in Table 2.

The cyclic linear permutation operator C.sub.p is referred to as a logical LPN or linear permutation operator because it operates on at least two operands, address variables, or index variables in two dimensions and because it is based upon and incorporates self-symmetric or reversible logic or Boolean gates such as XOR and XNOR gates. According to this requirement the inputs and outputs of the logical linear permutation networks are reversible and data cannot be lost. The addressing and data path circuits included in the AGEN and associated address logic and the DGEN can implement the raster graphics system for readily switching back and forth between the standard X,Y coordinate space and the permuted B,A coordinate system or PBM space without loss of data. The cyclic operator C.sub.p operates on two index variables and modifies the index bits by a modulus addition or subtraction. The inverse of the C.sub.p operator is given by another C.sub.p LPO in which one of the operands is a negative of either of the index variables.

The cyclic LPN is implemented in addressing logic circuitry in index or address space by arrangement of reversible or self-symmetric logical XOR or XNOR gates arranged as an adder as shown in FIG. 5. The cyclic linear permutation of the operands is therefore the sum of the operands with reference to a modulus equal to the number of address indices or objects being permuted. In terms of logic circuitry, the cyclic LPN C.sub.p translates to an adder or "rotator" implemented as such in the address circuits of AGEN or its associated address logic. In the data space and data paths of DGEN as hereafter described, the cyclic LPN C.sub.p is implemented by a barrell shifter or data rotator.

The particular functional relationship and linear permutation between the X,Y coordinate system and the PBM organization of the 16 memory banks B shown in Table 1 is defined by the following normal form equation.

The normal form X', Y' coordinates are related to the X,Y coordinates by the following equations:

where Q.sub.p is the multiplexing or switch hybrid LPN defined in Table 3 and E.sub.p is the exchange logical linear permutation operator defined in Table 4. The exchange linear permutation network or operator E.sub.p is a logical linear permutation operator operating on at least two operands or dimensions and incorporating or implementing self-symmetric reversible logical gates such as XOR and XNOR logic gates.

The multiplexing or switch LPN Q.sub.p is referred to as a hybrid LPN because it does not incorporate or implement such logic gates and therefore may be implemented with "wire" only operating on the index of an operand. However, the Q.sub.p LPN is a pairwise logical LPN. The Q.sub.p LPN is a unique LPN construction because it operates on indices from two or more dimensions multiplexing multiple dimensions and when implemented in pairs effectively functions as a logical LPN. Thus the pairwise logical switch operator Q.sub.p is an LPN that operates on two or more indices and when operating in pairs can perform logical operations as hereafter more fully presented. The switch LPN Q.sub.p is effectively a two-dimensional permutation logical operator which takes bits out of two different dimensions and multiplexes indexed or address bits. A circuit for implementing the switch LPN Q.sub.p in the address or index space is shown in FIG. 6 for the example of TABLE 3, while FIG. 6A shows the detail of the 2-to-1 selector switch of FIG. 6. A circuit for implementing the exchange LPN E is shown in FIG. 7.

For extending the permutation bit map of Table 1 from two dimensions to three dimensions incorporating for example a multiplane permutation bit map, the logical LPN transformation equation defining the assignment of the 16 memory banks B to pixel or bit positions of the user X,Y,Z coordinate system, two applications of the cyclic LPN or cyclic operator C.sub.p are required. That is to implement the permutation bit maps of the present invention a transformation LPN function is required which incorporates at least one logical LPN function such as the cyclic linear permutation operator C.sub.p for the two-dimensional permutation bit map and at least one logical LPN for each dimension after the first for higher dimension bit maps. For permutation of the three-dimensional X,Y,Z coordinate system to a three-dimensional PBM at least two logical LPN's are required.

In order to achieve multicellular addressing with two-dimensional cell configurations, the permutation objects, namely the 16 logical memory banks B must be a logical linear permutation function of at least two dimensions, for example both dimensions of the X,Y coordinate system namely X and Y. In the case of a multiplane three-dimensional coordinate system the memory bank designations may also be a function of at least both the X and Z coordinates. The logical LPN therefore operates on the pertinent indices or addresses of both coordinate dimensions. In the present examples these address bits also referred to as indices or index bits are four in number along each coordinate. In the Y coordinate direction of a block the address bits, indexes, or indices permuted by the logical LPN function are designated Y.sub.3, Y.sub.2, Y.sub.1 and Y.sub.0 or generally Y.sub.i where i=3, . . . , 0. In the X coordinate direction of the block the address bits permuted by the logical LPN function are X.sub.5, X.sub.4, X.sub.3, and X.sub.2 or generally X.sub.i where i= 5, . . . , 2. This pertinence of four index or address bits of X and Y is based on the following addressing scheme.

With reference to the addressing bit orders and directions, the following conventions are observed. Following the standard practice the right-most bit in an addressing word or data word expresse horizontally is the least significant bit (LSB) and is labeled with the index number or subscript i=0. The left-most bit of a word expressed horizontally is the most significant bit (MSB) and is labeled N-1 for an N bit word. Accompanying the LSB and MSB conventions is the convention that X values in the X,Y coordinate system increase from left to right while Y values increase from the top to the bottom of the X,Y coordinate system refresh image. According to one example implementation, the 64 bit cells or words in the DGEN are formed as an interleaved sequence of two 32 bit words to and from the frame buffer memory. According to the convention of identifying the order of data structures having multiple parts with increasing memory address order, the first 32 bit word to be transmitted or received has the lower memory address number. Similarly the 32 bit words of the AGEN composed of two 16 bit operands are arranged so that the 16 bit word with the lower register are placed in the least significant bits of the 32 bit word. In the case of the three-dimensional bit map with a Z coordinate for multiple planes, a convention is followed that the first plane or top plane is identified by index bit zero with higher numbered plane progressing downward in pixel depth. For refresh of the display each scan line composed of successive horizontal display words of successive blocks begin on a block address boundary.

Binary power of two X,Y addressing may be used to relate the X,Y position of a pixel on the raster display view surface to address values or positions of the memory banks and memory bank cell addresses which contain the pertinent pixel. While linear addressing may also be used, preferable for windowing systems, the following binary addressing scheme is described. The X,Y address is a concatenation of the index bits for Y and X. The X address of a pixel location of the view surface in the X,Y coordinate system is given by the address or index bits

where X.sub.N-1, . . . , X.sub.6 represents the block address in X, where X.sub.5, . . . , X.sub.2 represents the address in X of a quadunit within a cell, and where X.sub.1, X.sub.0 identify the four bits within the quad data unit. For a view surface and bit map with resolution of for example 1024.times.1024 pixels the view surface is subdivided and filled out by 1024 blocks of the dimensions 64.times.16 bits as described above. For a resolution of 2048.times.2048 pixels, the raster view surface and bit map are subdivided into 4096 blocks. A minimum of 10 to 12 address bits are therefore required to identify a particular block specified in part by the block address bits X.sub.N-1, . . . , X.sub.6. This X coordinate portion of the block address carries over directly between the X,Y coordinate system and the B,A coordinate system or PBM without permutation according to standard or conventional addressing transformation to memory.

The string of four address or index bits X , . . . , X.sub.2 identifies a quad in the horizontal X direction of the block which may be identified with a cell address corresponding to a coordinate position in the X,Y coordinate space. This is because in the horizontal X coordinate direction each coordinate position represents a quad of four bits or pixels. Each row of the block along the horizontal X direction is composed of 16 quads (64 bits), which quads can be identified by four index bits X.sub.5, . . . , X.sub.2. Each horizontal X coordinate position quad is controlled by or contributed by a different one of the 16 memory banks B as shown in Table 1. The memory banks B are also organized into blocks having the same block address for particular blocks. Once the block address is specified it is the same for all memory banks and all 16 memory banks contribute to the block. The specified block of a particular memory bank is divided into 16 cell addresses for the 16 cells of the block to which the memory bank contributes and constitutes one quad. As previously explained, each memory bank contributes one data unit or quad to each of the 16 cells of a block. The quad for a particular cell is therefore identified by the cell address A within the memory bank B. This cell address A and the memory designation B of the PBM coordinate system is related to the X,Y coordinate positions through the logical linear permutation transformation.

In the case of the X coordinate direction it is only the cell addresses of the quads for the cell address or index bits X.sub.5, . . . , X.sub.2 that are permuted representing four index bits. In the definitions of the different logical and wire LPN's of Tables 2, 3, 4, etc. the number of index bits L is therefore four and the modulus where applicable for example in defining the cyclic LPN C.sub.p is also 4. The block address bits X.sub.N-1, . . . , X.sub.6 are not permuted but carry over by conventional addressing to the memory banks. In other words the block is the set of bits in memory for which every memory bank has the same address. Every memory bank has the same block address in a particular block. The block organization of the present invention arises because there are portions of the address that do not change. Similarly the address bits X.sub.1, X.sub.0 which identify a bit or pixel position within the quad are not permuted by the LPN's. Rather it is only the four index bits of the cell address portion which change according to the selected addressing mode and therefore it is only the cell address bits that are permuted. It is the cell portion of the address that changes.

The Y address of a pixel location of a view surface in the X,Y coordinate system is given by the following address index bits:

where Y.sub.M-1, . . . , Y.sub.4 represents the Y coordinate portion of the block address and Y , . . . , Y.sub.0 represents not only the quad within a cell but also a particular bit or pixel location because in the vertical or Y direction the dimension of a quad unit is only one bit. The vertical dimension of a block is 16 bits or 16 pixel positions which can be specified by the 4 index bits Y.sub.3. . . , Y.sub.0. Again, the Y portion of the block address Y.sub.M-1, . . . , Y.sub.4 carries over directly between the X,Y coordinate system or SBM space and the B,A coordinate system or PBM space without permutation according to standard or conventional transform addressing. The complete block address is given by the concatenation of X and Y coordinate block address portions:

As stated above, the block address is not permuted and carries over to the memory bank address space in a conventional arithmetic relationship.

By way of example, the handling of the block address during refresh of the display is as follows. At the start of each frame determined by the clock ID on the display data bus, the block address counters or registers are loaded with the display start block address stored in the block address register 92 of the AGEN 15 illustrated in FIG. 12. This register is loaded with the first block address to be displayed. The block portion of the address is incremented across a horizontal scan line each time the clock ID from the display bus indicates the start of a display memory access cycle. A scan line is composed of aligned rows from 16 successive blocks across the screen. As each new scan line starts, the clock ID causes the Y portion of the address to be incremented one row. If the Y portion has reached its maximum count, namely the 16the row 0-F of the block, the block address is also incremented in the vertical Y direction. If the Y portion is not at its maximum count remaining within the same block, the block address is reloaded for the next scan line. In this way the display addresses repeat the same series of block addresses 16 times across 16 consecutive lines with each of the 16 lines using a different Y.

Display accesses use only the the 64.times.1 bit display word access so only the Y portion of the display address is needed to generate the 16 quad addresses which are all the same. Update addresses from the address registers of AGEN 15 use any of the selected two dimensional cell addressing modes. The update addresses may use both the X and Y portions of the address in addition to the specification of the selected cell configuration addressing mode.

The string of four address or index bits Y.sub.3, . . . , Y.sub.0 identifies a bit or pixel position in the vertical Y direction of the block which may be identified with a cell address in the X,Y coordinate space. Each column of the block in the vertical direction is composed of 16 bits or pixel positions from 16 quads which can be specified by the index bits Y.sub.3, . . . Y.sub.0. Each vertical Y coordinate position is controlled by or contributed by a different one of the 16 memory banks B designated by the hexadecimal digits 0-F as shown in Table 1.

As noted above, the memory banks B are also organized into blocks, each with the same block address for a particular specified block. Once the block address is specified each memory bank contributes 16 data units or quads to each block from 16 memory bank addresses A. Each of the memory bank addresses A contributes 1 unit of graphics image data or 1 quad to each cell of the lock for each different cell addressing mode that is specified. The memory bank addresses A are correlated with differing cell addresses C for the different addressing mode cell configurations. Each of the 16 memory banks B therefore has 16 bank addresses A within each block which can also be identified with 16 changing cell addresses C. The bank addresses A within a block are thus correlated with cell addresses C for any particular specified addressing mode cell configuration. These 16 cell addresses C represent the 16 data units or quads contributed to each block, one unit per cell. This cell address is established once the block and the addressing mode are specified. This is because the block portion of the permutation bit map according to the invention is organized to contribute one and only one data unit or quad to each cell. At this level, once the addressing mode is specified the bank addresses A within a block can be identified with the cell addresses C because each one of the 16 quads or graphic data units is associated with one of the 16 cells of the block for each of the different addressing modes. In the tables hereafter set forth for each of the different addressing modes, it is the memory banks B and cell addresses C for each of the specified addressing modes that are set forth as functions of the user X,Y or X,Y,Z coordinate pixel positions.

The bank addresses A and memory bank designations B of the PBM space or coordinate system are therefore related to the X,Y coordinate space through the linear permutation of index bits in both X and Y namely X.sub.i where i=5, . . . , 2 and Y.sub.i where i=3, . . . , 0. In the definitions of the various logical and wire LPN's of Tables 2, 3, 4, etc. the number of index bits L permuted remains 4 throughout for the selected example embodiments. Also the modulus where applicable is also 4. As stated above, the block address bits are not permuted.

Similarly as developed in subsequent address equations, the address bits or index bits for specifying the 16 memory banks B of a block are the four index bits B.sub.3, . . . , B.sub.0. The address bits or index bits for specifying the 16 cell addresses A of a block are the four index bits A.sub.3, . . . , A.sub.0. The address equations are therefore vector equations summarizing multiple equations. In the preferred example embodiments the number of permuted index bits per dimension or coordinate subject to linear permutation transforms remains 4 throughout, namely X.sub.i, Y.sub.i, B.sub.i, A.sub.i where the number of index bits L is four and i can assume one of the 4 values. The number of index or address bits L for each index variable e.g. X.sub.i, Y.sub.i, B.sub.i, A.sub.i, etc. is related to the number of logical memory banks M as the logarithm to the base 2. That is, L=log.sub.2 (M). In extending the present invention to the third dimension Z with 16 possible planes of organization of the frame buffer this also remains true of the index bits X.sub.i, Y.sub.i,Z.sub.i of the SBM coordinate system as well as the index bits B.sub.i, A.sub.yi, A.sub.zi of the PBM coordinate system.

A major achievement of the present invention is in the novel construction of a whole class of permutation bit maps with the following unique characteristics. Within each block the memory banks and bank cell addresses are so arranged in correlation with the pixel positions of the view surface and user X,Y coordinate system that multiple different cell addressing modes may be selected and yet each memory bank contributes one and only one data unit (in these example embodiments the quad) to each cell for whatever selected configuration. The different cell and word addressing modes or configurations therefore fill out or access each block covering all of the bits or pixel positions without redundancy and without overlap, forming boundary subsets of the block. Each memory access cycle for whatever selected addressing mode accesses each memory bank and accesses one cell or word to which each memory bank contributes one and only one data unit, in the present examples represented by a quad.

This achievement of the present invention requires a linear permutation transformation between the standard X,Y coordinate system and the PBM or B,A coordinate system incorporating at least one logical LPN in the case of a two-dimensional bit map and at least one logical LPN for each dimension after the first for higher dimensional bit maps. Thus for a three-dimensional PBM at least two logical LPN's are required in the functional transformation. Furthermore there is no limitation according to the present invention on the number of dimensions of the bit map. For example a four-dimensional PBM may be constructed based upon linear permutation of for example a user X,Y,Z,T coordinate system incorporating at least three logical LPN's where the fourth dimension is time. Such a four-dimensional LPN is useful, for example, in double or multiple buffer graphics. It should be noted that in linear permutation computations, the values of the data are not changed, only their ordering. Thus the variables may be viewed as coordinates of where the data is located and the mapping function f may be viewed as a computation which changes the number of a data item to a different number and therefore is a transformation from one coordinate system to another. The application of permutation theory to frame buffer addressing is a unique use of this mathematics in which the data ordering is carried out in more than one dimension. The mathematical literature treats only single dimension problems, while the present invention is concerned with novel multidimensional frame buffer addressing with linear permutation operators. According to the invention, there is always a one to one mapping of data from one set to another in such a way that the data may be transformed bank to its original order by an inverse transformation. Mapping functions which have this one to one and invertable property are called linear permutation operators or LPOs for short. LPOs are mathematical functions which satisfy the rules of an algebra and may be manipulated by formulas to prove desirable properties and achieve the end results.

The physical implementation of LPOs in any combination is called a "Linear Permutation Network" or LPN for short. In general an LPN implemented in index space requires considerably less circuitry than the equivalent LPN implemented in data space. For this reason, all LPNs in the address circuitry or the address generator are implemented in index space. As used herein the terms LPO and LPN are sometimes used interchangeably though it is the LPNs that are the physical circuitry implementations of the LPOs.

A more versatile permutation bit map embodiment of the present invention is summarized in Tables 5, 6, 7, 8, and 8A, each showing a 64.times.16 bit size block (16.times.16 quad size block) of the permutation bit map. The Tables give the memory bank and bank cell addresses B,A or B,C as a function of X,Y or X,W where W=R.sub.p (Y). A close inspection of the assignment of memory banks designated by the first hexadecimal digit 0-F of each pair of hexadecimal digits in the body of the tables to pixel or quadpixel positions of the X,Y coordinate system reveals a difference in the permutation order resulting from exchange and reversal linear permutation networks in contrast to the cyclic LPN which generated Table 1. Tables 5 through 8A are also shown with the horizontal X coordinate increasing from left to right and the vertical Y coordinate increasing from top to bottom.

A feature and advantage of the exchange and reversal PBM of Tables 5 through 8A is that additional addressing modes AM are accommodated. Each addressing mode AM is designated by two numbers hv where h is the exponent to the base 2 of the number of quads in the horizontal direction and v is the exponent to the base 2 of the number of bits in the vertical direction composing each cell of the addressing mode. As shown in Table 5 the block may be addressed or accessed by the 64.times.1 bit horizontal word addressing mode AM40 for refresh of the display and for bit block transfers and polygon fills. Table 6 shows the partitions of the block into vertically oriented 4.times.16 bit cells of addressing mode AM04 useful for updating the frame buffer for drawing vertically oriented vectors with high performance. A high number of pixels may be updated, as many as 16 pixels, each memory access cycle. Table 7 shows the partition of the block into 16 horizontally oriented 16.times. 4 bit cells in AM22 useful for updating the frame buffer for drawing horizontally oriented vectors with high performance. With respect to Table 5, 6 and 7 the exchange and reversal PBM equals the capability of the cyclic PBM of Table 1. In addition however as illustrated in Tables 8 and 8A the block may be partitioned into and addressed and accessed by square configuration 8.times.8 bit cells and horizontal 32.times.2 bit cells for appropriate applications. In each instance the 16 memory banks still each contribute one and only one data unit or quad in each cell and the 8.times.8 bit cells of Table 8 and the 32.times.2 bit cells of Table 8A fill out or cover the block without redundancy or overlap forming further boundary subsets for addressing modes AM13 and AM31.

Reviewing Tables 5 through 8A it is apparent that the assignment of memory bank addresses B to pixel positions on the view surface represented by the X,Y coordinate system blocks of the tables is fixed and invariant. In these examples the memory bank designations B are shown as the first hexadecimal digit while the bank addresses A or actually the corresponding addresses C for the specified addressing mode AM are the second hexadecimal digit. Thus the bank designations B do not change in the same static mode. The cell assignments or cell addresses C however do change with the different cell addressing modes. Tables 5 through 8A show the unvarying bank assignments B and the logical linear permutation of the banks as permutation objects in the transformation by logical linear permutation from the X,Y coordinate system to the logical memory bank coordinate system. The memory bank cell addresses which correspond at this level with cell address C also become "permutation objects" but the permutation is not unvarying and changes according to the selected addressing mode cell configuration. All 16 memory banks are represented in each cell for whatever configuration addressing mode but the memory bank cell addresses of the bank address locations A within the memory banks vary as hereafter described in further detail with reference to the example embodiments of the permutation bit map invention.

In order to achieve the permutation bit map of Tables 5 through 8A, the 16 memory banks are coordinated or assigned to the X,Y coordinate pixel positions according to the logical linear permutation functional transformation expressed in the following equation:

where E.sub.p is the exchange logical linear permutation network defined in Table 4 and R.sub.p is the reverse or reversal wire linear permutation network defined in Table 9. A circuit for implementing the wire LPN R.sub.p is shown in FIG. 8.

With respect to the LPO and LPN notations and table definitions, the location of a specific data item in a set of data is defined by an index variable (also called a data coordinate) and expressed by capital letter variable names such as X, Y, and Z; B, A.sub.y, and A.sub.z ; C, U, and S etc. All data sets contain a power of 2 number M of data objects so that each index variable requires L=log.sub.2 (M) bits. The individual bits in an index variable are Boolean values which are represented by either a subscript notation such as X.sub.i or by appending the actual bit number to the variable such as X.sub.0, X.sub.1 and so forth. The bits in an index variable are order sensitive and bit-0 will always be used to denote the least significant bit. For example, in a system having 16 memory banks, the "bank number" index variable B has 4 bits defined as follows:

All the LPOs on an index variable involve simple operations on the bits of the index in such a way as to preserve the invertibility property. All expressions in an LPN must involve variables with the same number of index bits. Thus, general formulas may be derived which describe a system of any size for implementation in a specific system which specifies the desired value of L. The LPO definitions are given in terms of the i-th bit of an index variable.

Formulas involving the index bit numbers are performed using module arithmetic based on the modulus L. Thus if j and k are index variable bit numbers, then:

The reversal operator R.sub.p results in the reversal of the index variable bits of a single index variable. R.sub.p simply reverses the order of the bits in an index variable. A second reversal R.sub.p will restore the original order so that R.sub.p is its own inverse. The exchange (E.sub.p) LPO is a logical LPO which involves two index variables and the XOR Boolean primitive. Note that XOR and XNOR are the only Boolean functions of two variables which are invertable. The exchange LPN or LPO is the exclusive "or" Boolean function of the two variables. The inverse of E.sub.p is the exchange or substitution of any two variables all as set forth in TABLE 4. In general, E.sub.p commutes over any wiring LPO whereas the logical C.sub. LPO does not commute over any wiring LPO. Furthermore, C.sub.p does not commute over E.sub.p.

More generally the reversal exchange permutation bit map is defined by the following general form of the fundamental equation:

where f.sub.L is a function of a logical LPN while f.sub.w is a function of a wire LPN or linear permutation operator. In the multiplane implementation of the reversal exchange permutation bit map the fundamental equation may also be applied in the two dimensions of X and Z for permutation of the addressing in different numbers of planes as follows:

The changing memory bank cll and unit addresses C and U which change according to the selected addressing mode AM are given by the following LPN permutations:

and h is the exponent or logarithm to the base 2 of the number of quads in the horizontal dimension of the selected addressing mode cell. The multiplexing or switch LPN Q.sub.p expresses the changing bank cell addresses necessary to achieve the multiple cell addressing modes. The address mapping of the memory bank address locations A is given by:

According to the best mode of the invention a three-dimensional permutation bit map is constructed with linear permutation of the user X,Y,Z coordinate system addresses in three dimensions using a novel combination of both logical and wire linear permutation networks including at least two applications of logical linear permutation operators. In this preferred three-dimensional PBM embodiment nearly 50 different cell configuration addressing modes are available for accessing the blocks. These cell configurations of the best mode PBM are summarized in Table 10. As heretofore described the preferred implementation is described with reference to a frame buffer composed of 8 physical memory banks each with a unique set of addressing lines. The physical memory banks are time sliced twice each memory access cycle providing 16 effective logical memory banks for permutation in the three-dimensional permutation bit map.

Because of the third dimension, the dimension of the block or block section includes not only the horizontal dimension of 16 quads or 64 bits and the vertical dimension of 16 bits in the case of a single plane P=1, but also the depth dimension of number of planes P of up to 16 planes. The block dimension is therefore H.sub.max .times.V.sub.max .times.P bits where P the number of planes may have the value of 1, 2, 4, 8 or 16 bits. The block size does not exceed 1024 bits. Each block is composed of and may be partitioned into three-dimensional cells. The horizontal cell width is designated H with a maximum cell width Hmax, the vertical cell height is designated V with a maximum cell height V.sub.max, and the pixel depth is similarly designated P.

The many addressing modes of the preferred permutation bit map hereafter described are summarized in Table 10. Referring to Table 10 most of the addressing modes pertain to the optimum permutation bit map or PBM of the present invention although the system also accommodates a number of standard bit map or SBM addressing modes. The second column designates or names the respective addressing modes by a four digit number denoted hvps. The origin of this designation is as follows. Of the columns on the right three of the columns designated H, V and P specify the respective horizontal, vertical and plane depth dimension of each of the addressing cell configurations in bits. The capital letter designations are thus reserved for specifying dimensions in bits. Of the left-hand columns the lower case columns designated h, v, and p represent logarithms to the base two of the horizontal, vertical and plane depth dimension specified by the respective upper case letters H, V, and P with the following qualification. The v and p designations are in fact the exponents to the base 2 of the respective V and P dimensions in single bits. The h designation referring to the horizontal dimension is however the exponent to the base two of the number of quads defining the cell in the horizontal dimension. Thus, for example on the first line identifying the 64.times.1 bit horizontal word cell configuration the horizontal dimension is 64 bits or 16 quads and h is the exponent 4 to the base 2 which gives 16 quads which also equals 64 bits.

The fourth designation of the addressing mode using hvps notation is the s referring to the static addressing mode or static mode. Not all of the PBM addressing modes are available at the same time under the mathematical constraints of the three-dimensional permutation bit map architecture. Only those addressing modes are concurrently available which satisfy a contiguity requirement hereafter defined. The optimum multicellular addressing PBM architecture according to the present invention allows the user to select one of five static modes s or sm, designated by the numbers s=0, . . . , 4 each static mode affording a rich set and selection of alternative cell configuration addressing modes with greatly improved performance characteristics appropriate to particular applications. As shown in Table 10 these addressing modes which are available concurrently to the user are designated by the same digits equal to 0, 1, 2, 3 or 4. The logarithm to the base 2 parameters h,v,p corresponding to the H,V, and P parameters are combined with the static mode character s to form the four character address mode or AM designation for example AM3100, the second addressing mode of Table 10. The AM3100 is a horizontally oriented 32.times.2 bit cell. For each of the identified cell addressing modes the most appropriate uses for the cell configuration are listed in the right-hand column of Table 10. In this column under the heading "USE", the B refers to use in bit block transfers while the V refers to use in vector drawing. In some instances both are appropriate uses.

In referring to Table 10 it is noted that the product of the bit dimensions H.times.V.times.P of the three-dimensional modes are achieved by varying any two of the three parameters but the product of the parameters always equals exactly the 64 bit cell size of the preferred example embodiment. It is also noted that the sum of the corresponding exponents or logarithms h,v,p always equals 4 and this sum is designated L:

a parameter useful in the defining equations of the logical and wire linear permutation networks. In the present examples, M=16 and L=4. The number 4 coincides with the number of address bits or index bit permuted in a linear permutation operation for any particular coordinate dimension, the number of least significant address bits or index bits of interest for each dimension or degree of freedom. It is the four least significant bits in each of the dimensions that is permuted to achieve the three-dimensional permutation bit map. In the case of the X coordinate dimension this however coincides with the address bits X.sub.5, . . . , X.sub.2 because the data units are in quads and the lowest bits X.sub.1 , X.sub.0 identify a bit or pixel position within the quad.

Optimum or best mode permutation bit maps in three dimensions corresponding to representative selected addressing modes of the static modes of Table 10 are illustrated in Tables 11 through 25. These permutation bit maps are referred to as double exchange shuffle and reversal bit maps implemented by a combinatorial linear transformation function incorporating two exchange logical linear permutation networks or operators and shuffle and reversal wire linear permutation networks or operators as hereafter more fully defined. A single block of the three-dimensional double exchange shuffle reversal PBM is shown in each of the Tables 11 through 15. Each table presents the coordinates of the user X,Y,Z coordinate system represented in two dimensions with the X coordinate in the horizontal direction increasing from left to right and the Y and Z coordinates in the vertical direction increasing from top to bottom. The assignment of memory banks in the body of the table corresponding to pixel or quadpixel locations of the view surface for the block subdivision are represented by three hexadecimal digits. The first digit is the logical memory bank designation B which may be compared with the first digit in Tables 1 and 5 through 8A. The second hexadecimal digit represents the bank cell address C for the specified addressing mode AM within the memory bank while the third hexadecimal digit represents the three-dimensional block section or cell address A.sub.z or S. For Tables 11 through 15 this third address designation is zero because these tables represent addressing modes in a single plane permutation bit map. The partitions show selected ones of the different addressing mode cell configurations AM available in static mode sm=0. All the addressing word modes where v=0 and V=1 for example are not shown although they are listed in TABLE 10. Upon close inspection the subtle differences of the double exchange shuffle reversal permutation bit map from the exchange reversal permutation bit map and cyclic permutation bit map are apparent. It is the characteristic and subtle permuted organization of the double exchange shuffle reversal permutation bit map which enables the rich selection of available cell configuration addressing modes in multiple planes as summarized in Table 10. Tables 16-25 represent multiple partitioned blocks showing representative selected ones of the different three-dimensional cell configuration addressing modes AM in multiple planes for higher static modes sm 0. All of the available three-dimensional AM's are listed in TABLE 10.

Equations for defining the linear permutation transformations to establish the PBM's of Tables 10-25 are summarized in Table 26 including the set up equations. Equations for word mode addressing AMhWp are a special case where W=v=0. An alternative symbolism or notation for expressing the same fundamental equations from TABLE 26 is used in the equivalent equations set forth in TABLE 26A. All of the applicable linear permutation operators or LPN's have already been defined except for the shuffle wire LPN S.sub.p which is defined and summarized in Table 27. Circuits for implementing the shuffle LPN S.sub.p are shown in FIGS. 9A-9D.

The shuffle LPO S.sub.p is a wire LPN or LPO that rotates the bits of an index variable. The phase of the rotation is given by a phase shift parameter or shuffle phase parameter. The inverse of a shuffle is a shuffle with negative shuffle phase shift parameter or a negative of the original shuffle phase shift parameter. A positive shuffle phase shift gives a left to right rotation while a negative shuffle phase shift gives a right to left rotation. Note that R.sub.p and S.sub.p are non-distributive. S.sub.p is used to implement the selected static addressing mode or selected static mode (sm) permutation bit map.

The general fundamental equation for the linear permutation transformations between the standard and PBM spaces for the best mode three-dimensional linear permutation bit map is of the normal form:

where f.sub.L1 and f.sub.L2 are logical LPN functions and X', Y', and Z' may involve further wire or logical LPN functions of the original user pixel coordinates X, Y, and Z. In the preferred example f.sub.L1 and f.sub.L2 are or incorporate the exchange LPN operator E.sub.p and Y' and Z' incorporate shuffle S.sub.p and reversal R.sub.p operator LPN functions of Y and Z. In particular, the preferred fundamental equations are of the form:

The reverse transformation from the permutation bit map coordinate space B,A.sub.y,A.sub.z to the user X,Y,Z standard coordinate system also in the functional form of the fundamental equations as follows:

The intermediate transformations, for example between the X,Y,Z and C,U,S coordinate system require the multiplexing switch hybrid LPN Q.sub.p as set forth in the equations of Table 26 and 26A. The fundamental circular relationship between the three coordinate system spaces X,Y,Z: C,U,S; and B,A.sub.y,A.sub.z is shown in FIG. 10. This diagram illustrates the fundamental theorem of linear permutation network theory that if two of the three mutually derivable functional transformations are given, then the third is also given.

To establish the best mode linear transformations in two dimensions the fundamental equation for the linear permutation transformations between the SBM and PBM spaces may take the following general form:

where F.sub.L is a logical linear permutation network or operator function while f.sub.W is a wire linear permutation network or operator function. The memory bank cell and unit address equations may take the form:

It should be no that the closest prior art relating to raster graphics architecture and frame buffer bit maps, such as for example the Texas Instrument TI 34010 Graphics System Processor or the Carnegie Mellon University (CMU) cellular architecture discussed above, if characterized in terms of linear permutation network theory do not go beyond and cannot be characterized as going beyond a transformation of the following general format:

For a two-dimensional bit map a single logical LPN is sufficient to establish a novel PBM according to the invention with a rich selection of multiple alternative cell and word configuration addressing modes. Moreover the two-dimensional permutation may take place in either the X,Y coordinate plane or the X,Z coordinate plane to provide a novel two-dimensional permutation bit map in either plane. For example the fundamental permutation transformation equation in two dimensions may also be applied in the X,Y plane as follows:

As described above in transition to a three-dimensional bit map or even higher dimensional bit map, a plurality of logical linear permutation network operators or functions are required in the fundamental transformation equation, one for each dimension after the first. In this way a multidimensional permutation bit map may be established with a rich and varied selection of three-dimensional or higher dimensional cell and word configuration addressing modes. In each instance, for however many dimensions of the multidimensional permutation bit map according to the invention, the fundamental mapping equation for the memory banks B is independent of the addressing modes. That is the transformations or assignments of the memory banks B and memory bank address locations A to pixel positions of the view surface remains invariant for any particular selected permutation bit map while it is the cell addresses C which vary according to the selected addressing mode. Because of this characteristic feature of the invention the multiplexing or switch LPN Q.sub.p does not appear in the fundamental mapping equations for B. The multiplexing operator Q.sub.p expresses the multiple addressing cell and word modes for any particular permutation bit map of the invention and therefore appears particularly in the cell address, data unit address, and cell related parameter and coordinate equations of Tables 26 and 26A. The importance of the permutor or operator Q.sub.p is in expressing the different dynamic cell and word configuration addressing modes applicable and permitted with a selected permutation bit map. The particular permutation bit map is selected in the described example embodiment by selecting the static mode, sm or s number shown in Table 10.

The valid dynamic multiple cellular addressing modes AM for each of the different selected static modes sm or permutation bit maps of the preferred example embodiment are also summarized in Table 29. Each static mode sm may be viewed as a different permutation bit map or PBM with different fixed assignment or permutation of memory banks relative to the coordinate positions for pixel positions of the user view surface. For each different PBM or sm the valid available addressing modes AM are indicated by the affirmative letter Y in Table 29. The constraint which determines whether or not an addressing mode is available of a particular PBM or sm is referred to herein as the contiguity requirement. According to the contiguity requirement only contiguous modes are available. The contiguity or contiguous modes refers to addressing equations in which the address bits or index bits, namely the least significant bits of X and Y and Z must be adjacent or contiguous bits. For example, Table 30 is a table of the addressing permutation and correlation between the C,U,S address or index bits and the X,Y,Z index bits for the different dynamic addressing modes AM available in static mode sm=0. It is apparent upon inspection of this Table that the contiguity requirement is met by indicated addressing modes AM because the least significant bits or X,Y or Z are always adjacent or contiguous bits with reference to the numerical order of the index i.

The satisfaction of the contiguity requirement by most of the addressing modes available for the PBM or static mode sm or SM=1, the PBM or static mode sm or SM=2, the PBM or static mode sm or SM=3 and the PBM or static mode sm or SM=4 is further shown in Tables 33, 36, 39 and 42 respectively. Each of these tables also shows the transformation of address bits between the user X,Y,Z coordinate system and the intermediate block cell and unit coordinate system C,U,S. It should be noted that in each of these tables the index bit number (written in the specification as a subscript) follows the coordinate dimension letter X,Y or Z and in these tables corresponds to this subscript. In the Tables 33,36 39 and 42 the index bit digits for Y and Z in which i=3, . . . , 0 and for X in which i=5, . . . , 2 are written next to the dimension coordinate letter for convenience only. In the LPN definition tables 2,3,4,9 and 27, these index bits are written as actual subscripts.

The final physical memory bank address connections A, in two dimensions, and A.sub.y,A.sub.z in three dimensions are derived and formulated from the fundamental permutation bit map equations of the present invention in four basic steps. In the first step the static modes for the system and the possible static mode transforms or static transforms are established. Each static mode is a specific mapping of pixels from the standard X,Y coordinate system to physical memory bank locations. A range of static modes are available in the preferred embodiment each in effect constituting a different physical permutation bit map with a different range of dynamic addressing modes or addressing mode cell configurations. A defined set of dynamic addressing mode cell configurations will operate on the permutation bit map defined by a particular static mode. The static transforms may involve any combination of wiring and switch LPOs or LPNs but do not include other logical LPNs. The result of this first step or static transforms is a set of modified functions of X,Y and Z for example X,Y.sub.s,Z.sub.r where Y.sub.s is a shuffle linear permutation function of Y and Z.sub.r is a reversal linear permutation function of Z. In the alternative notation of TABLE 26A the initial modified variables are, for example X,W.sub.y and W.sub.z.

In the second step of defining and formulating the address line connections and equations, the memory bank designations or assignments B and the memory bank address assignments A in two dimensions and A.sub.y and A.sub.z in three dimensions are established as a function of the modified static transform variables X, Y.sub.s and Y.sub.z or X, W.sub.y, W.sub.z. These are the fundamental equations for B, A.sub.y, and A.sub.z at the beginning of TABLES 26 and 26A. These bank assignment transformations or logical bank assignments establish the range of possible addressing mode cell configurations. The bank assignment LPNs are any combination of logical LPOs or LPNs. Specifically the bank assignment transform function involves cyclic C.sub.p and exchange E.sub.p linear permutations in any combination which includes all the index space variables. The switch LPO Q.sub.p with at least one constant index may be included to construct specific permutation bit maps such as the cyclic permutation bit map of TABLE 1 . If the number of dimensions of the index space is N+1 then the bank assignment transform function must include exactly N occurrences of a logical LPO according to the invention. These bank assignment transformations must be invertible as shown in the fundamental equations of TABLES 26 and 26A.

The third step in formulating the address line connections is the dynamic cell address transformation deriving the address cell and unit coordinates in two dimensional index space or C,U,S in three dimensional index space from the modified static transform variables X,Y.sub.s,Z.sub.r or X,W.sub.y,W.sub.z. This cell address transform defines the possible dynamic cell address modes for the given sets of static transformation equations from steps 1 and 2. Each address mode is selected by selection parameters related to the dimensions of the selected addressing mode cell as heretofore described with reference to TABLE 10. Only those addressing modes which satisfy the contiguity requirement discussed above may be useful. The cell address transformation of this third step involves only the logical switch operator Q.sub.p using the address mode selection variables for the switch index threshold parameters designated h in TABLE 3 and variously including h,L-p, and p' in TABLES 26 and 26A. The cell mode transform must be invertible and the inverse transform must be expressible only in terms of the U,C or U,C,S index variables. Similarly in the inverse transform only Q.sub.p LPOs or LPNs may be used as set forth in TABLES 26 and 26A. The cell address variables U,C, and S in TABLE 26 are expressed in the alternative notation U,C.sub.y,C.sub.z in TABLE 26A.

The final step in defining the memory bank address line connections physically defining the architecture of the system is to derive the physical address mapping of the bank address assignments A.sub.y and A.sub.z (also designated AY and AZ in the address equations) in terms of the memory bank assignments or designations B and the cell addresses C in two dimensions or C,S in three dimensions. In the alternative notation of TABLE 26A the memory bank address line assignments A.sub.y and A.sub.z (AY and AZ) are formulated in terms of the variables B,C.sub.y and C.sub.z. The fundamental theorem diagrammatically illustrated in FIG. 10 permits this final index or address line transformation. This is also possible in the preferred embodiment of the present invention because the E.sub.p and Q.sub.p operators commute. Once the memory bank address assignments A.sub.y and A.sub.z are formulated in terms of the memory bank assignments B and cell addresses C,S or C.sub.y,C.sub.z, equivalent Boolean equations may be derived for implementation of the memory bank cell address lines and line connections. This is accomplished by replacing the LPO operators in the final equations for A.sub.i namely A.sub.y and A.sub.z with their Boolean logical equivalent. These address lines for A.sub.y and A.sub.z are shown in FIG. 11. The fundamental equations for A.sub.y and A.sub.z in combinational mathematics are summarized in TABLE 26 and 26A. The corresponding equivalent Boolean equations AY and AZ for determining the actual cell address line circuits and connections are given in TABLES 28, 31, 33, 35, 37, and 39. The index bits ij following AY and AZ are the variable bit number i [3:0] and the "pull" number j either 0 or 1.

While the example embodiments have been described with reference to frame buffer memory address and data spaces of 2 and 3 dimensions, the present invention is applicable to n dimensional spaces defined by n coordinates, index variables or address variables. In each instance the fundamental equations may be generalized for linear permutation transformations between an n dimensional or n coordinate standard user/viewer space , an n dimensional abstract data unit and cell address space, and finally an n dimensional memory bank and bank address coordinate space.

The memory bank address connections for the corresponding addressing circuits to achieve the best mode example are set forth in Table 28 along with the addressing equations set forth in condensed Boolean equation format. These address line equations are spelled out in further detail for the different static modes in Tables 31, 33, 35, 37, and 39. The external address equations compute and generate the address lines. They convert the fundamental equations and setup equations of Tables 26 and 26A expressed in the combinational mathematics of linear permutation operators to logic circuitry expressed by the Boolean logic equations. The symbolism conventions of the addressing equations and external address equations are as follows.

The capital letters H and P are actually the log values expressed in the specification as lower case h and lower case p. However, they are written in Tables 31, 33, 35, 37, and 39 in capital letters because it is the convention to write the Boolean address equations in all capitals. The expressions HLT and PLT refer to "h less than" and "p less than". It should be noted that the subscripts as they appear in the specification as subscripts are shown in the Tables on the same line as the referent. Thus AY refers to A.sub.y. In the external address equations the plus sign "+" refers to the logical "OR" operation, a blank space refers to the logical "AND" operation, the complement symbol "'" refers to the logical complement or "NOT" operation and the .phi. symbol refers to the exclusive or "XOR" operation. These external address equations convert the fundamental equations of Tables 26 and 26A into logic circuits.

A generalized block diagram and flow diagram of a raster graphics system according to the invention showing the AGEN 15 and associated address circuits 20, frame buffer memory banks 12, and the DGEN 22 are illustrated in FIG. 11. This block diagram shows the basic configuration of a frame buffer address and data controller for raster graphics machines with the elements of novelty incorporated by the present invention. As shown in FIG. 11, the AGEN 15 includes the basic linear permutation networks in block diagram form for converting graphics data address information in the user X,Y,Z coordinate system to the intermediate cell, data unit, and block section coordinate system C,U,S. To this end the network blocks incorporate respective wire linear permutation networks S.sub.p and R.sub.p and the important cell address permutation hybrid LPN Q.sub.p in the functional relationships that are summarized in Table 26.

In the example of FIG. 11 the full linear permutation transformation from the user X,Y,Z coordinate system to the memory bank and bank address coordinate system B,A.sub.y,A.sub.z is not completed within the AGEN 15. This embodiment of the invention is referred to as the exterior addressing mode for AGEN 15. The addressing permutation transformations are completed in associated address circuitry 20, which for example incorporates the external address circuitry of Tables 31, 33, 35, 37 and 39. The associated address circuit 20 includes the linear permutation networks for completing the transformation from the intermediate C,U,S coordinate system to the physical memory bank and memory bank address coordinate space B,A.sub.y,A.sub.z. Completion of the linear permutation transformation is accomplished by the logical, wire, and hybrid LPN's E.sub.p,S.sub.p,R.sub.p, and Q.sub.p as set forth in the equations of Table 26 implemented in the functional blocks of the associated address circuitry 20 as shown in FIG. 11. The resulting memory bank addresses are summarized by the addressing equations and the memory bank address line address connections summarized in Table 28, 31, 33, 35, 37 and 39.

Data retrieved from the memory bank address locations is then processed for specified graphics operations in the DGEN 22. Detailed description of the components and elements of DGEN 22 as shown in both FIG. 11, Part 2 and FIG. 16 is provided hereafter with reference to the description of DGEN 22 at FIG. 16. For the present purposes, the block diagram of FIG. 11 shows the novel elements required to be implemented in the graphics data generating component because of the unusual permuted order of the data retrieved from memory banks 12. According to the graphics operation to be performed, for example, bit block transfers, polygon filling, vector drawing, etc., data must be reordered from the PBM space of the B,A.sub.y,A.sub.z coordinate system to the SBM standard coordinate system in certain instances. To accomplish this, pre- and post-linear permutation networks are provided for example in association with the EXNET elements 110 and 120 of FIG. 11 hereafter referred to as the PRENET and POSTNET of FIG. 16 for performing linear permutations. Alternatively, vector graphics data to be written in memory must be transformed from the user X,Y,Z coordinate system to the intermediate PBM coordinate space C,U,S for matching and masking with destination data, etc. Masks must be matched with source or destination data also during Bit Blt and polygon fill operations. Linear permutation networks for matching and masking data to be merged or masked all as hereafter described in further detail are set forth in the LPN functional block elements of the DGEN 22 in FIG. 11. All of these parameters for performing the operations on graphics data in DGEN 22 are summarized and defined in Table 26. Additional linear permutation operators may be incorporated for example in the TRANSLATE component or element of DGEN 22 in FIG. 11 according to the selected permutation bit map in the frame buffer and therefore the PBM organization of data retrieved from the frame buffer.

The basic features of the AGEN component 15 are described with reference to FIGS. 12 and 13. The AGEN component 15 is a dedicated address and rasterization sequence controller which supplies addresses to a memory control 22 or memory circuit and generates the sequences of operations which allow the DGEN component 22 to modify the contents of the bit-map of the frame buffer memory. The AGEN supports varying architecture styles of high performance graphics systems. The AGEN includes all the standard basic primitive generation features and provides a number of unique capabilities relating to PBM's not found in any conventional addressing device. The significant capabilities of the AGEN may include the following.

The AGEN 15 provides automatic generation of addresses for controlling permutation bit-maps in the user selectable cell address mode. Up to 1 Giga-byte of memory per DGEN may be directly addressed in single plane mode or up to 64 Mega-bytes of memory per DGEN may be addressed for applications using DGEN in the 16 plane mode. The AGEN 15 provides a full set of pipeline drawing state registers allowing the setup of the next instruction to be completed before the completion of the current instruction.

Complete control of the bit level rasterization may be provided for vector begin point, end point and break point bias. There is full bit level clipping, and clip edge interrupt. Full bit level picking is also provided with programmable pick identification code, and interrupt independent of the clip process. The memory block address generation as heretofore described supports direct mapped, binary mapped and linear bit-map styles of addressing. The major AGEN graphics generation instructions may be aborted and then resumed after register restoration. Full address generation is provided for the screen refresh function in response to refresh request inputs. The AGEN 15 supports single to multiple plane addressing as well as the sequencing of pixel level data transfers for user supplied pixel processing. Thus, the AGEN incorporates those features known in the computer graphics art and in addition the PBM addressing capabilities of the present invention.

As illustrated in FIG. 13 of the drawings, AGEN is a 68 pin component using 60 pins for the functional system interface and 8 pins for power and ground connection. The general purpose and characteristics of these pins are summarized in TABLE 45 and set forth in further detail as follows:

ADDRESS/DATA

Bus This is the primary 32-bit bidirectional bus interface of the AGEN to the rest of the system. Data received and transmitted on this bus include: (1) instruction words and operands form the programmable graphics processor, (2) addresses of data for input to the DGEN components, (3) addresses of data for writing into memory from the DGEN components and (4) control words for the system components. Input data is enabled for reading by AGEN over these lines by the ADE signal. AGEN sinks a maximum of one 74LS load from the bus signal drivers for input.

ADDRESS/DATA ENABLE

This active low signal forces the AD bus into an open condition allowing the reception of data into the AGEN registers while also allowing bus transfers in which AGEN is not involved. This signal is generated by the external bus control logic. AGEN sinks a maximum of four 74LS loads from this signal.

MASTER RESET

This active low signal causes complete initialization of the AGEN control circuits, including the initialization of the refresh state counters. After the low to high transition of this signal, AGEN generates a READY bus-code indicating a satisfactory operational state and readiness to execute instructions. AGEN sinks a maximum of four (4) 74LS from this signals.

INSTRUCTION CLOCK

This is the primary source of timing for all AGEN internal operations. The maximum rate is 40 MHZ with minimum dynamic state rate of 1 MHZ. Typical graphics systems will normally drive this signal at its maximum specified rate. The signal is able to sink the equivalent of ten 74LS loads at the maximum rate and has a duty cycle of no less than 40% and no more than 60%. AGEN assume that this clock is free running (never stops). All active low AGEN output strobe signals occur within 20% of the high to low transition of this clock.

BUS OPERATION CODE

This is a multi-purpose code which indicates the instruction execution state in response to a status request which is an a synchronous interrupt request to the programmable graphics processor or the definition of the type of bus cycle to be executed for AGEN data input and output. These lines are valid when the BUSTROBE signal are low and are capable of driving a minimum of two 74LS loads at a 10 MHZ maximum rate.

BUS OPERATION STROBE

An active low output signal indicates that the BUSCODE is valid. The high to low transition may be used by external circuits to load the BUSCODE into external registers for finite-state machine control. This signal is capable of driving a minimum of two 74LS loads at a 30% duty cycle maximum rate of ICLK divided by four.

BUS CYCLE WAIT DELAY

This active high input signal causes the AGEN to delay any AD bus transaction for the number of clock cycles for which it remains high. The leading edge must be received by AGEN two and one-half ICLK cycles prior to any AGEN operation which would otherwise utilize the AD bus. This signal is used primarily to insert "wait states" for memories whose read or write cycle time is greater than two ICLK cycles and to allow external use of the AD bus for direct PGP access to the bit-map memories. This signal must be high for at least two ICLK cycles. The AGEN sinks a maximum of one 74LS load from this signal.

INSTRUCTION READY

This is an active high level signal indicating that the AGEN is available to accept a instruction request (IRQ) instruction code (ICODE) input. This signal is guaranteed by the AGEN to be low for no longer than four ICLK periods allowing external polling of the AGEN instruction status. This signal by itself does not indicate that AGEN is available to receive a new AD bus instruction or operand. The AGEN pulls this signal low within two clock cycles of the receipt of an IRQ and also drops the signal for an AGEN initiated bus cycle. The signal remains high for a status or interrupt request bus-code output allowing external circuitry to distinguish the meaning of a bus-code. This signal is capable of driving two 74LS loads at 50% duty cycle at a rate of ICLK divided by four. That is, AGEN drops this signal at most once every four ICLK periods.

INSTRUCTION REQUEST CODE

This four bit code indicates to the AGEN the type of operation which is being requested by the external hardware including soft reset, status request, refresh data request and graphics instruction execution. These signals are valid when the IRQ signal is low. The AGEN sinks a maximum of one 74LS load from these lines. The drive circuits are required to change the values of these lines no more often than four ICLK cycles.

INSTRUCTION REQUEST

Active low input signal indicates to AGEN that the instruction request code (ICODE) is valid. The ICODE is processed beginning at the high to low transition of this signal. This signal is synchronous with the ICLK train and the high to low transition within 20% after the high to low transition of ICLK. The signal is required to remain low for at least two clock cycles and must not be issued more frequently than every four ICLK cycles. For operand input, it is normal for IRQ to be received every four ICLK cycles. IRQ may be generated while IRDY is low but will not be honored until IRDY becomes high. AGEN sinks a maximum of one 74LS load from this signal.

DGEN OPERATION CODE

These code signals are issued by the AGEN to indicate the primary type of instruction to be executed by the DGEN(s). May also be decoded by external circuitry along with the bus-code when applicable to gain detailed information regarding the type of bus operation being conducted. For example, the memory controller determines whether a read, write, refresh read or read-modify write sequence is to be executed based on the DOP code and Blt's in the BFLD. A low value of OPSTROBE indicates to the external logic BFLD. that DOP is valid. DOP values do not change more frequently than every four ICLK cycles and AGEN sinks a maximum of two 74LS loads on these lines. These signals are normally connected directly to the equivalent pins of the DGEN (after appropriate buffering as necessary depending on the number of DGEN components). The DOP, BFLD and PFLD signals taken together form the NGEN input instruction and are collectively called the DOPBUS signals.

DGEN OPERATION STROBE

An active low output signal indicates to the DGEN (and external circuits) that the DOPBUS signals are valid. The high to low transition may be used to load external registers. OPSTROBE remains low for a minimum of two ICLK cycles and is issued normally at rate of once every four ICLK cycles.

DOPBUS BREAK FIELD

This four bit quantity is used by the DGEN to determine the sequence of XY counting when assembling the vector data to be drawn. For other DGEN instruction, Blt's in the BFLD are used to extend the DOP code to allow more than eight instructions to be interpreted by DGEN. The BFLD bits are also used by DGEN to indicate the beginning or end of a block transfer line operation.

DOPBUS PIXEL FIELD

This four bit quantity is used by the DGEN to determine the line style pixel values when assembling the vector data to be drawn. For other DGEN operations, the PFLD indicates the permutation control index or the DGEN global logical operation code (GLOG). External circuitry is allowed to modify GLOG on a per DGEN basis to facilitate multiple auxiliary plane control.

FIG. 12 illustrates the major register groups, their functional operations and relationships for the AGEN 15. The AGEN functional operations may be logically divided into five main categories: (1) instruction and operand input and setup, (2) AD bus control and buscode generation, (3) address generation, (4) graphic primitive rasterization (conversion of a geometric primitive such as line or polygon fill to a sequence of pixels to be written), and (5) preparation and transmission of the DGEN instruction words. AGEN may be viewed as consisting of a number of independent computing and register blocks connected by an internal bus 70 and incorporating the addressing features of the skilled art in computer raster graphics. These multiple components operate together concurrently to implement the basic drawing algorithms. The general operations performed by AGEN and the definition of these functional blocks are as follows.

Refresh addressing causes the readout of the display bit-map memory data to DGEN for conversion to a serial stream which is then used to control the beam intensities for the display device. The range of addresses used for display refresh taken together are called the refresh bit-map which is defined in the address registers 72.

Vector rasterization is the conversion of a line segment defined by two end-point positions to a set of pixels which approximate the connected straight line in such a manner as to visually represent a straight line. The bit-map resolution and "square pixel" arrangement dictate that the constructed image is only an approximation, but the approximation improves as the bit-map size increases requiring more pixels to be drawn and thus requiring faster rasterization which is accomplished by the higher performance of the present architecture. The AGEN may provide a pattern mechanism which allows the drawing of line styles and automatically suppresses the drawing of vector pixels which are outside of the current display window by pixel a clipping process as hereafter described.

Block transfers allow rectangular regions of a bit-map to be moved and modified on a block basis. The use of the word "block" in this case is different from the use of the same word in the address organization. Block transfers involve generally at least the definition of a source bit-map (where the pixel data is coming from) and a destination bit-map (where the data is going to) and the locations of the corners of the rectangle in each bit-map. The most common uses of block transfers are for character drawing and window management. For "window dragging" as may be required by window management software, the source and destination bit-maps may be the same. Vector rasterization only involves the destination bit-map. Further, the source and/or destination bit-maps may be the same as the refresh bit-map in which case the result of the rasterization operation will become immediately visible on the display screen (but only if the operation were not "clipped" as described below).

Polygon fills are the rasterization of a bit-map area defined by a general polygon perimeter. This allows the drawing a filled circle for example. Because of the rasterization principle of approximation, a circle may be represented adequately on its circumference by a sequence of straight line vectors of sufficiently short length. Conceptually, polygon fill is a combination of vector rasterization for the perimeter and block transfer for the interior. The AGEN allows a polygon fill to use a source bit-map so that the interior may be rendered with arbitrary two-dimensional pattern or with a gradation of intensity for color shading.

For a drawing position operation, AGEN uses the "current position" to determine the precise X and Y location in a bit-map which is to be modified during the rasterization sequences. Instructions are provided in AGEN to set the initial value of the current position for an instruction. For example, the two end-points of a line are defined by first executing a set position instruction and then executing a vector instruction which defines the second point. The AGEN always maintains the current position in such a manner as to have the proper memory address. That is, the AGEN 15 automatically converts X,Y and Z (pixel depth) bit-map coordinates to the permutation bit-map memory addresses. All of these features available to those skilled in computer raster graphics may be incorporated into the AGEN and the DGEN.

The general process of executing an instruction consists of loading the Next Instruction Register NIR 74 with a 32-bit instruction word from the AD bus 18 after negotiating an instruction request/instruction ready IRQ/IRDY sequence with a "load next instruction" ICODE input at the READY REQUEST CONTROL 75. Depending upon the current AGEN activity, the SETUP CONTROL logic 76 may proceed to load the pipeline registers through the DRAW CONTROL 77 with input operands in preparation for the instruction execution. Any instruction operand which needs to be loaded into a register which is not pipelined and is currently in use is not executed until the register is free to be loaded. Other operations of the setup control phase are dependent upon the instruction type and involve the distribution of data with no computations executed beyond simple comparisons. Once all the operands and registers for an instruction have been processed, the instruction is transferred to the Current Instruction Register CIR 78 for execution. At this point, the setup controller is available to receive a new instruction. Instructions which only load registers do not have an execution phase.

Instruction execution may involve a computation setup phase such as is needed for computing the width, height and direction of a block transfer operation. If needed, these computations are performed by the same generators used in the actual pixel manipulation phase.

The rasterization process may be viewed as consisting of operations at the pixel level (components above the internal bus 70 in FIG. 12) and operations at the block and cell level (block below the bus 70 in FIG. 12). These operations always proceed concurrently with information from the pixel sequencing side being used to generate the proper cell and block address traces.

Operations at the pixel sequence level include line style pattern generation by PATTERN GENERATOR 80, line break generation by BREAK GENERATOR 82, assembly by the Field Assembler 87, and the appropriate counting action of the X and Y counters X,Y,Z REGISTERS 83 to reflect the current drawing position. For vector drawing, the current position is compared to the clipping and picking boundaries as defined by the CLIP and PICK REGISTERS 84 and 85 on a per pixel position basis. Any crossing of a clip or pick boundary may result in the generation of an interrupt if that interrupt is enabled.

If picking is enabled, no actual drawing is performed, that is, the AGEN (15) does not issue DGEN instruction or memory reads and writes. Otherwise the operation of the AGEN is exactly the same as for the case of pick disabled (drawing enabled). The pick process is used primarily to retrace all the drawing steps in the drawing of an image to determine the step at which a graphic primitive intersects the current user visual cursor. This allows sophisticated interactive graphics editing. Since no DGEN or memory operations are performed, the image is normally traversed much faster with pick enabled as compared to the time necessary to actually draw the image.

The clipping process is used primarily to allow the graphics primitives to traverse a coordinate space larger than the available memory and also facilitates the implementation of effective windowing systems. Neither the clip or pick process effect vector performance although they represent a small amount of overhead for block transfer and polygon fill instructions.

The actual sequence of pixel traversal is controlled by the values in the DRAW STATE REGISTERS 86 which contain all the details for the process and make these details available for user modification. Each time that a cell boundary is crossed in the pixel traversal process, the values for the cell address and block address are modified by the UPDATE CELL GENERATOR 90 and the BLOCK ADDRESS GENERATOR 92. Cell address generation depends completely on the current X,Y,Z values while block address generation depends upon information indicating which side of a memory block has been traversed and the current address values and bit-map definition values contained in the ADDRESS REGISTERS 72.

At each point in the rasterization process that a new cell has become defined, the memory address needed to read and write memory for that cell is assembled from the current cell address and block address through address multiplexer or ADDRESS MUX 91 and transmitted to the memory controller over the AD bus 18 along with the appropriate bus-code from the bus control logic 94. Concurrently, the pattern and break sequence data are assembled along with the appropriate operation code and transmitted to DGEN over the DOPBUS 95 by the DGEN INSTRUCTION GENERATOR 96. During the computational setup phase of all instructions, appropriate 32-bit setup and control words are assembled by the DGEN DATA ASSEMBLER 99 from the drawing state information and contents of the SETUP REGISTERS 98 for transmission over the ADBUS 18 to DGEN 22 along with a DGEN load register instruction from the DGEN instruction generator 96.

For vector drawing, several DGEN instructions may be generated to transmit the vector data to be assembled by the DGEN 22 for each cell. For the block transfer operations, each memory cell cycle is associated with one DGEN instruction execution. The pixel sequence blocks are not used in the process of the sequential address generation for bit-map display refresh. Rather, the block address generator and a separate REFRESH CELL GENERATOR 100 supply all the information needed to output refresh cycle addresses. This allows the pixel sequencing to proceed concurrently allowing overlap of screen refresh with rasterization.

Further details of the AGEN update cell generator 90 are illustrated in FIG. 14. For cell address generation input address data in the X,Y coordinate system of the current absolute horizontal drawing position for vectors and characters is received in the CURXL latch or register 160 with register CURX 0 162 for vectors and register CURX 1 164 for characters and respectively for the left and right side of bit transfer blocks and polygon fills. The least significant six bits are used directly to construct the cell address for source and destination address access. The current absolute vertical drawing position for vectors, characters, and the left and right side of bit transfer blocks and polygon fills is input to the latch or register CURYL 165 and registers 166 and 168 respectively CURY 0 and CURY 1. The contents of these registers are compared with the CLIP and PICK register states. The horizontal and drawing position address data is also input to the octant latch or register OCTL 170 for multiplexing with the output of octant generator 172 through MUX 174 to octant registers 175 and 176 respectively OCT 0 and OCT 1. Output from X,Y control 178 is provided to the current drawing position registers. The current X and Y position registers provide data input to the XEDGE and YEDGE registers 180 and 182.

According to the novel elements of the present invention, the final cell address data in the C,S and A.sub.y,A.sub.z memory bank coordinate system are permuted by linear permutation networks implementing the LPN operators as set forth in the functional blocks of FIG. 14. The LPN operations selected from the basic defining equations of Table 26 establish the updated cell addresses according to the selected addressing mode.

The further details of the AGEN refresh cell generator 100 are shown in the block diagram of FIG. 15. For refresh cell address generation using the refresh word mode, the refresh X and Y coordinate address data RY and RX are permuted according to the selected LPN's of FIG. 15, also derived from the basic linear permutation equations of Table 26. The outputs of refresh cell generator 100 are the refresh cell addresses in the C,S and the A.sub.y,A.sub.z coordinate systems.

The DGEN or Data Generator component 22 shown in FIG. 11, Part 2 and FIGS. 16 and 17 is the data path manipulation component of the system architecture. The DGEN 22 implements the spatial data permutations needed to allow the multiple cell address modes for variable plane bit-maps and high speed vector generation.

The purpose of the DGEN is to (1) handle the extremely high bandwidths of data that are common to high-end graphics systems, (2) generate area images (polygon fill, windows and characters), (3) generator vector (line) type images at "stroke graphics" performance and (4) perform the first level of video bandwidth generation for image refresh. On a comparative basis, DGEN can be considered to be a "Bit-Blt chip" incorporating features known to those skilled in the field or art and which takes advantage of the new permutation bit map architecture of the present invention to perform the data manipulation aspects of image generation at a speed of 5 to 10 times the rate of previously developed components.

As shown in FIG. 17, the DGEN 22 is an integrated circuit packaged in a 68 pin LCC with functional pinouts summarized in TABLE 46. The following paragraphs describe the function and use of the DGEN interface signals in further detail.

The VID[7:0] outputs represent consecutive 8-bit video words in screen refresh order. These signals are used directly to construct a system having 1, 2, 4, 8, or 16 image planes per DGEN component and operating at up to a 40 MHZ monitor bandwidth. For higher bandwidth systems, the VID[7:0] outputs are connected to external shift registers to achieve the maximum specified bandwidth of 320 megapixels for a single plane per DGEN system. The VID output may be TTL compatible or ECL compatible. In either case, the VID lines are capable of driving only one standard load. Data values on the VID lines change on each occurrence of the video strobe (VSTROBE) signal.

The D[31:0] bidirectional lines are the principle interface to the refresh memories. These lines are usually connected to the system bus 24 through bus transceivers to allow maximum bandwidth between the DGEN and the frame buffer memory banks 12. The DBUS or MBUS 24 is designed to operate at up to 20 million cycles per second providing the availability of up to 640 megapixels of data to be shared between screen refresh and image generation functions. The DGEN data formats are constructed to allow the use of 1-bit wide and 4-bit wide memory parts. The DGEN directly supports memories with page-mode and static column access modes, with or without write enable mask input. DGEN can also be used with static memories (SRAMs) with cycle times as low as 50 nsec. DGEN has been optimized for standard DRAMs in such a way that 60% of the performance of a 50 nsec SRAM memory system can be achieved at 10% to 30% of the cost of a SRAM based system. The D lines are capable of supporting 2 LS-TTL loads at the full 20 MHZ rate.

The DOP[2:0], PFLD[3:0], and FFLD[3:0] signals taken together form the 11-bit DGEN input instruction word and are referred to as the DOPBUS. These instruction words are used to control the type of operation performed by the DGEN on each memory cycle. For vector operations, the PFLD[3:0] lines represent 4 bits of a vector to be drawn and are given to the DGEN at a rate of up to 10 MHZ allowing the generation of vectors at speeds up to 40 megapixels. This allows multiple board systems without the difficulties of distributing the vector data at the 40 megapixel rate. The ICLK line is used to strip each bit from the 4-bit P field and pack these bits into the internal drawing registers. The P-field of each DGEN in a multiple plane system may be connected to the system bus using a transceiver in such a manner that single pixels with full Z-depth can be read and written in a single memory cycle. The OPSTROBE signal is used to enable DGEN operations and synchronize the internal timing chains. This means that all timing states for drawing and memory interface are resynchronized on each new memory and operation cycle.

The combination of 40 MHZ ICLK, VSTROBE and VID-bus with 20 MHZ, MBUS or DBUS and 10 MHZ OPCODE bus provides a very high performance multiple board system.

The basic functional block diagram of FIG. 16 and the block diagram of FIG.11, Part 2 illustrates the major functional components of the DGEN 22. The DGEN provides an effective 64 bit path based upon a multiplexed 32-bit data path. This provides better economy of implementation without performance degradation. The DGEN 22 may be viewed as comprising three main sections: (1) the principle data path in the center of FIG. 16, (2) the video section on the right side of FIG. 16, and (3) the vector generation section on the left side of FIG. 16.

The basic sequence for modifying memory contents consists of taking data from the DBUS 24 through the pre-operation permutation normalization circuit PRENET 110 to restore the standard bit map SBM user organization where appropriate and then storing that data in the source and destination data latches SRCO 112, SRCl 114, and DST 115. This data is then reordered by the alignment rotator or ALROT 116 and logically merged in the PLOG and LOGCOM circuit 118 to form the new result word which is post-operation permuted in POSTNET 120 to return normalized data to the unusual PBM organization and then written back into the memory. The corresponding components of FIG. 16 and FIG. 11, Part 2 are identified by the same reference numerals.

The PRENET 110 and POSTNET 120 circuits, also referred to as the EXNET circuits 110 and 120 in FIG. 11, Part 2, are the main distinguishing aspects of the DGEN as compared to existing Bit-Blt chips and indirectly form the basis for the architecture of the present invention. The need for these pre- and post- operation rotations or permutations are a consequence of the manner in which data is stored in memory to allow the access to the two-dimensional pixel cells by multiple cellular addressing modes which are the basis for the high performance vector drawing. The alignment rotation or ALROT 116 is used to adjust the position of the bits in Bit-Blt source words to the destination word boundaries prior to merging the source words with the destination words as known to those skilled in raster graphics. The LOGCOM circuit 118 and associated PLOG circuit provide the programmable means for defining in what manner the source words from source multiplexes or SRCMUX 122 (including vector bits) are combined with the existing memory destination words from DST register 115. The 16 logical operations provided include the ability to EXOR the source words with the destination for rubber banding operations and "or"-ring the source with the destination to simulate image transparency. The BITMUX 124 in the principle data path allows the selection of bits in the destination memory words to be left without modification as defined by the output from mask multiplexer MASKMUX 125. For example, in a Bit-Blt operation, the bits to the left and right of the destination image window must be left without modification.

By way of example the exchange linear permutation E.sub.p is implemented in the DGEN 22 of FIG. 16 using the PRENET and POSTNET circuits which incorporate the exchange LPNs for example of FIGS. 18 and 19. For the DGEN data input 24 to PRENET 110 the input word is the bank number designation or assignment B and the output of the PRENET circuit is the quads or quadpixels in normalized graphics data unit U coordinates. The cell address parameters E.sub.p (C,S) are then the PRENETC control for the PRENET permutation network. The output of PRENET circuit 110 goes to the DGEN registers through a possible further wire permutation network transformation in TRANSLATE 152 according to the operating static mode or permutation bit map. Thus, conveniently the control for the PRENET permutation network 110 may simply be the cell address function E.sub.p (C,S) for operation of the DGEN 22 with permutation bit maps. For operation of DGEN 22 with a standard bit map the PRENETC control is zero. The quadpixel unit coordinates U are therefore derived as functions of the memory bank designations B and cell addresses C from the fundamental equation:

PRENETC=E.sub.p (C,S)

The POSTNET output permutation circuit 120 is the inversion of the PRENET circuit 110. The POSTNET LPN circuits implement the exchange inversion of the fundamental theorem namely:

POSTNETC=E.sub.p (C,S)

Thus the input to POSTNET permutation circuit 120 from the output of multiplexer 124 is in the quadpixel normalized unit dimension coordinates U and the output is in the permuted memory bank assignment coordinates B for return to the frame buffer memory permutation bit map. The POSTNETC control may similarly be the cell address function E.sub.p (C,S) for the permutation bit map from which the memory bank coordinates B are derived as a function of C and U. While the POSTNETC control signal may be E.sub.p (C,S) for operation of the DGEN 22 with frame buffer permutation bit maps, the control signal is zero for standard bit maps. The network arrangments for deriving these signals corresponding to linear permutation functions is shown in FIG. 11, Part 2.

By way of example the shuffle linear permutation network S.sub.p may, for example, be incorporated in the TRANSLATE component to accommodate changes in the static mode or permutation bit map. The shuffle LPN operator S.sub.p introduces a static transform changing the address or index bit positions. A characteristic of the shuffle operator S.sub.p is that is changes the assignment of pixel positions in the user/viewer X,Y or X,Y,Z coordinate system to memory bank address locations in the B,A or B,A.sub.y,A.sub.z coordinate system. This change in the permutation bit map is referred to herein as a static transform and changes the static mode sm.

The shuffle LPN S.sub.p is useful only for changing the static mode or permutation bit map and cannot be used in the fundamental equation for a particular permutation bit map once the PBM is established. On the other hand the logical linear permutation network operators E.sub.p and C.sub.p alone or in combination with each other or with the wire LPN R.sub.p are useful in defining a particular assignment of pixel positions, performing the permutation without changing the address or index bits. The assignment of pixel positions to physical memory bank address locations remains the same despite operations by the operators E.sub.p, C.sub.p, and R.sub.p

Another wire LPN useful in changing the index or address bits and therefore the association of pixel positions in the user/viewer X,Y coordinate system with memory bank address locations is the butterfly LPN B.sub.p. Thus, according to the invention the bufferfly operator B.sub.p may be used instead of the shuffle operator S.sub.p for changing the permutation bit map to different static modes sm. Briefly, the butterfly linear permutation operation (LPO) B.sub.p involves the exchange of a specified arbitrary index bit number k with the least significant bit (LSB) of that address or index. For example:

Then B (2:A.sub.3,A.sub.2,A.sub.1,A.sub.0) =A.sub.3,A.sub.0,A.sub.1,A.sub.2

In this example where the specified or selected exchange index bit k=2 than the address or index bit A.sub.2 is exchanged with the least significant bit of the address namely A.sub.0. The butterfly LPO is self-inverting as follows:

The shuffle LPO S.sub.p and the butterfly LPO Bp therefore provide examples of linear permutation networks which actually exchange or change the index bit positions useful for changing the definition or organization of the permutation bit map and therefore the static mode sm. Such LPOs may be incorporated in the address circuit for changing the PBM and in the TRANSLATE component of the DGEN 22 for normalizing data retrieved from the altered or newly defined PBM. The TRANSLATE component may also include other wire LPNs necessary to normalize data retrieved from the frame buffer memory such as for example the reversal LPN R.sub.p.

The video generation section of the Bit-Blt chip is provided for two reasons: (1) buffer data from the image memory using the DGEN's high speed bus interface and (2) hide the strangeness of the bit-ordering of the PBM refresh data in the image memory. FIFO buffering 128 of the video data is standard to simplify system timing and allow more effective utilization of memory bandwidth. The inclusion of the video FIFO or VFIFO 128 in the DGEN makes standard DRAM's look like video RAM's or VRAM's. The inclusion of video FIFOs is a standard feature of commercially available video shift registers. The inclusion of the 40 MHZ video shift registers 130 in the DGEN permits inexpensive standard ECL shifters to be used to generate the final system bandwidth. Alternately, DGEN can be connected directly to some commercially available LUT/DAC (color look-up table/digital to analog converter) components which have onboard video shift registers. Providing 512 bits of FIFO storage means that only three RAS cycles to memory are needed for the refresh of each scan line in a system of 1280 by 1024 resolution. Using static column components, this represents only a negligible performance decrease in such a system relative to VRAM's and at significantly reduced cost.

The vector generation section on the left side of the DGEN 22 consists of high speed circuits which load the vector source value latch or register VVL 140 and vector mask latch or register VML 142 based on the pixel value (PFLD) and break sequence (BFLD) signal inputs. This section includes 6-bit X value and 4-bit Y value counters which define the position in the registers where the consecutive value bits are written. The X and Y counters are incremented and decremented for each bit as a function of the current drawing direction and the values of the break signals. This circuit is constructed to implement the data manipulation portion of the inner loop of any of the variations of Bresenham's vector drawing algorithm as is well known in the raster graphics field. The DGEN can also be used with non-Bresenham line generators such as the slope-DDA (digital differential analyzer) algorithm which has attractive properties in anti-aliasing as compared to Bresenham's algorithm. This interface also provides the basis for external high speed shading circuits.

In summary, the DGEN provides the lowest level detailed bit manipulations needed in any high performance graphics system without any specific constraints on the style of use. Typically, these operations are sequenced in such a manner as to have the effective results of polygon filling, window dragging and character drawing.

As illustrated in the DGEN block diagram of FIG. 16, other registers are as follows.

The MBUS or Data Bus 24, designated D[31:0] is a 32-bit bidirectional bus interface to memory and the AGEN bus transceivers. Register operations which involve the MBUS and require a 64-bit word are referred to as MBUS 64 whereas transfers involving only 32-bits are referred to as MBUS 32. MBUS 64 operations use two consecutive MBUS 32 operations.

SRC0 and SRC1 112 and 114 are 64-bit registers which hold the source bit-map data values during block transfer operations. Taken together, these registers form the 128-bit word input to the alignment rotator, the source bit-map data is made to align with the proper bit position in the destination bit-map for read and write operations.

LOGCOM 118 is a 64-bit map plane logical operation control register which allows the merging of source and destination data to be controlled on a per plane basis. This is used for plane masking (disable modification of certain planes, transparency control, setting foreground and background colors (referred to by the GKS and CGI standards as primary and auxiliary color).

The GLOG or global logical operation control register controls the merging of SRC and VVL registers for stripe and three operand operations.

VFIFO 128 is an eight word by 64-bit FIFO register set. It buffers data to be output on the VIDEO output lines through the internal video shift registers VSR 130.

DST 115 is a 64-bit destination bit map data register. It holds the current value of the destination bit-map cell for merging with the new values from the aligned source registers or the vector value registers.

VML 142 is a 64-bit vector mask latch that indicates the bits in a cell which are to be modified during vector draw operations.

VVL 140 is a 64-bit vector value latch that stores the foreground background selector value for pixels written by the vector draw and stripe draw operations.

VMR 144 is a=64-bit vector mask assembly register. Vector mask bits are first stored in this register prior to being loaded into the VML register 142. This allows the overlap of loading VMR 144 by vector instructions while writing the last word assembled into memory from the VML register 142.

VVR 145 is a 64-bit vector value assembly register. Vector pixels are first assembled into the VVR before transferring to the VVL for memory modification.

DSMR 146 is a 32-bit DGEN static mode register. It stores mode control information for video control 147. DSMR 146 is normally changed infrequently, and contains the following general information: the number of planes used per DGEN component during the refresh process; the number of 64-bit word transfers which are performed to load the VFIFO registers on each refresh load instruction execution; whether the refresh bit-map is of type standard bit-map (SBM) or permutation bit-map (PBM); and the permutation static mode to be used in the PBM normalization for any bit-map which is a PBM.

DBSV 148 is a 32-bit block transfer, vertical transfer control register. It contains the information needed by the DGEN to control data transfer and translation for an entire block transfer operation through instruction control 150. ROTC is a 6-bit rotation index. It defines the amount by which the source register value is rotated prior to merging with the destination bit-map data. XLTC controls the translation of source data from the memory by TRANSLATE component 152. The TRANSLATE component is provided for further LPN's which may be necessary for particular PBM organization. It is used primarily to convert SBM's to PBM's and PBM's to SBM's, but may also be used to translate bit-map data which does not conform to standard conventions to standard form. DIR 156 controls the direction of the block transfer operation in terms of left to right versus right to left and top to bottom versus bottom to top. This information is used to control the order in which the source registers are loaded and to control whether the source and destination scan line number registers are to incremented or decremented. This field is shared with the OCT field of the vector setup control register.

DVSH 154 is a 32-bit vector and block transfer horizontal control register. It contains the information needed by DGEN to control edge masking for block transfer operations by EDGEMASK 155, both left edge or LEDGE and right edge or REDGE, permutation control of the destination bit-map, and vector drawing position information. The WEM signal enables the write enable mask output. It allows only a portion of destination words to be modified in memory components supporting this capability. Write enable allows faster operation since the destination word does not have to be read. It only applies if "write only" logical merge values have been selected.

Linear permutation network or LPN circuits for implementing the prenet 110 and postnet 120 of the DGEN 22 for exchange permutation bit maps are illustrated in FIGS 18 and 19. FIG. 18 illustrates a combination of exchange LPNs for graphics image data operations with an exchange permutation bit map or PBM of the type described. Referring to FIG. 18, each rectangular element 190 comprises a logical exchange linear permutation network E.sub.p with two data inputs and outputs as illustrated in FIG. 19. The respective exchange LPNs 190 are in turn coupled exchange LPN overall permuting the eight data inputs D[, . . . , 7] to the permuted data outputs DLPN[0, . . . , 7].

For cyclic permutation bit maps, prenet 110 and postnet 120 may be implemented by the cyclic LPN, C.sub.p. The cyclic operator C.sub.p is implemented in index space by an adder bit in the DGEN in data space by a data rotator or barrel shifter. C.sub.p may also be used to define systems in which the data alignment rotator or ALROT 116 in the DGEN 22 is also used to perform the permutation normalization. Although this reduces the gate complexity of the DGEN, the number of unique address lines required is proportional to the number of address banks which means that the bank address lines must be computed external to the AGEN. In contrast, for the components based upon the exchange LPO E.sub.p the number of unique address lines required is proportional to the log.sub.2 of the number of memory banks M so that the address lines are computed internal to the AGEN and transmitted as part of the overall memory address word. This substantially reduces the complexity of the external circuitry.

The DGEN component 22 of FIG. 16 also incorporates the circuit element TRANSLATE 152 for incorporating additional LPNs as may be required for a particular permutation bit map or PBM, for example additional wire LPNs such as the reversal LPN R.sub.p and/or the shuffle LPN S.sub.p. Alternatively the prenet 110 and postnet 120 may incorporate directly additional logical or wire LPNs for example to implement the double exchange shuffle and reversal PBM for example summarized in Tables 11 through 25.

A fundamental concept of linear permutation theory is that LPO transformation on the order of data may be viewed (and implemented) in two fundamentally different but precisely equivalent ways namely in (1) data space and (2) index or address space. In the data space, the data is physically moved from one place to another. In the index space (or coordinate space) the data remains physically in the same space, but is accessed (read or written) in a different order. An equation using LPOs may be implemented using either. In the case of the architecture of the present invention all the AGEN and address circuit operations permute the pixel data in the memory blocks using index space operations the AGEN never physically touches the data. In contrast, most of the DGEN operations execute the same equations in data space by physically moving bits from one place to another. The invariant for all these operations is the location of pixels in memory which must be the same for all address modes accessing the same permutation bit maps. The AGEN cell addresses to memory are used to define data order transformations by allowing each memory bank to contribute pixel data from different locations. This allows the implementation of the address modes. In the transformation equations, the data from memory is generally permuted in such a way as not to be directly usable for display refresh or block transfer operations. The DGEN PRENET circuit implements the same equations in data space to allow the normalization of data to screen order for refresh and block transfer operations. The DGEN to the PBM order needed for proper physical placement of the data in the memory banks.

Summaries of various data processing steps for selected graphics operations in the DGEN 22 are illustrated in FIGS. 20 through 23. While the general data flow for particular operations such as bit block transfers and polygon fills, vector drawing, and display refresh are well known in the raster graphics field, the flow charts of FIGS. 20 through 23 show the novel requirements and steps according to the invention for normalizing data received in the permuted PBM coordinate space for logical processing, masking, merging or other selected operations and for permutation and return of process data from the normalized or standardized SBM coordinate space to the permuted PBM coordinate space for storage in the unusual order of the frame buffer bit map. In particular, normalization of data where required is generally accomplished by the prenet or prepermutation network 110 of the DGEN 22 while the permuting of process data for return to the frame buffer permutation bit map as accomplished by the postnet or postpermutation network 120.

An example bit block transfer or bit-blt operation according to the invention is set forth in FIG. 20. While such a bit block transfer operation is a standard feature of raster graphics machines the novel steps according to the present invention appear in the middle of the flow chart. According to the invention a determination is made of the coordinate space of the source word or source cell and the destination word or destination cell. If the source cell and destination cell originate from the PBM space they are respectively normalized for compatible merging of the source and destination cells. The source and destination cells or words are aligned by conventional rotation or barrel shifting prior to merging. The merged cell is then permuted to match the PBM coordinate space of the destination cell in memory prior to writing the merged cell in the frame buffer permutation bit map.

A typical vector draw operation is illustrated in the flow chart of FIG. 21. While the steps of vector drawing are well known in raster graphics machines, the novel steps according to the present invention appear in the middle of the flow chart. The new vector to be drawn is constructed in the standard user coordinate space. The memory cell or destination cell from the frame buffer permutation bit map is normalized for merging with the new vector cell in the standard coordinate space. The merged cell is then permuted for writing into the PBM coordinate space of the frame buffer permutation bit map. A further flow chart of ve:tor drawing operations by the DGEN 22 is illustrated in FIG. 22 in which all operations are carried out in either the standardized user coordinate space or in the permuted PBM coordinate space.

The refresh data flow in the DGEN 22 is illustrated in FIG. 23. While the serial processing of refresh data words for display on a raster display such as a CRT are well known in raster graphics machines, the novel steps according to the present invention appear in the middle of the flow chart. If the refresh data words are retrieved and received in the permuted PBM coordinate space, the refresh cells or words are normalized by appropriate linear permutation networks as heretofore described to order the serial refresh data words in the standardized user coordinate space for loading into the video shift registers. The examples of FIGS. 20 through 23 represent read-modify-write operations. In addition write enable (WE) operations may also be incorporated in the DGEN 22 for writing directly into the permuted PBM coordinate space of the frame buffer permutation bit map.

In arranging the data flow sequences and steps for the data generator a number of alternatives are available. One objective in selecting among the alternative steps for processing data and performing graphics operations on data retrieved from the permuted bit map is to minimize circuitry. Another objective is to increase the speed of operations. These objectives may be achieved according to the invention by maximizing the number of operations that are performed on the addresses of the data, that is the address indices in the address or index space, and minimizing the number of operations performed on the data bits in data space. According to preferred embodiments of the invention for example most of the operations are performed in index space.

A feature and advantage of this arrangement is that the index space is a log space or logarithm space with an exponential reduction in the number of permutation objects required to be permuted relative to the data space. While the data space is the coordinate system representation of the data bits, the address space or index space is a binary encoding coordinate system representation of the log indices. Graphics operations in the data space coordinate system represent an exponential increase in the number of permutation objects permuted by the LPN circuits over the operations in the index space. Therefore it is advantageous according to the invention to perform most of the operations or as many of the operations as possible in the address or index space using the address circuitry. Those LPN operations that cannot be displaced to the address circuitry are teen performed in the data generator circuitry on data in the data space.

The linear permutation operators or LPN's according to the present invention may operate in either the index space or the data space. In either case the principle of operation and definition of the LPN as heretofor described remains the same. However, because of the difference in the number of permutation objects, as between the index space or address space and the data space, the LPN circuitry is of lesser or greater complexity. For example, FIGS. 6A and 19 are equivalent in the functions performed but the simpler circuit FIG. 6A operates in the index or address space and the more complex circuit FIG. 19 operates in the data space. In terms of the number of permutation objects, the index space and data space bear to each other this logarithmic or exponential relationship. By way of example, the cyclic operator C.sub.p is implemented in index space by an adder and in data space by a data rotator or barrel shifter.

Another characteristic of the present invention which differs from conventional raster graphics machines is the provision of and requirement for two separate mappings for performing graphics operations. Throughout the operations of the multicellular addressing permutation bit map raster graphics architecture of the present invention, one of these mappings represents an invariance property, namely the pixel position/bank address mapping between the user coordinate system and frame buffer memory bank addresses X,Y and B,A in two dimensions and X,Y,Z and B,A.sub.y,A.sub.z in three dimensions. This mapping always remains constant and valid independent of the address mode selected among the multicellular addressing modes. The pixels on the user view surface always remain in the same position on the display with the same memory bank address location or assignment.

This invariant pixel position/bank address mapping is the logical linear permutation network mapping achieved by the logical LPN operators in the fundamental equations. The invariance property of this mapping is that each of the pixels or pixel positions on a display or view surface retain the same frame buffer memory bank address location or assignment for any selection of refresh addressing words. And this invariant mapping relationship is one of a logical linear permutation transformation. The pixel positions in the X,Y or X,Y,Z or higher dimension coordinate space bear a logical linear permutation functional relationship to the actual memory bank addresses B,A or B,A.sub.y,A.sub.z or higher dimension bank address space.

The conventional raster graphics machine is also characterized by a mapping between the pixel positions in the user X,Y or X,Y,Z coordinate system and memory bank address locations but this is the only mapping relationship or mapping performed by the system and it is a standard bit map or standard mapping relationship limited to a single addressing mode rather than a permutation bit map or logical linear permutation mapping relationship with multicellular addressing modes.

Not only does the present invention differ from conventional raster graphics machines in introducing this permutation bit mapping, but also in introducing an entirely new requirement of a second mapping between the pixel positions in the user X,Y or X,Y,Z coordinate system and a cell, unit, and block section organizational space C,U or C,U,S. The pixel position/cell address mapping represents the variance property, switching property, or selection property of the mapping relationships according to the present invention for selecting among a plurality of multicellular addressing modes. According to this second mapping relationship of the present invention, different addressing modes with different cells or cell configurations may be selected and defined with the pixels identified by different cell addresses in the different selected cells. That is, the different graphics data units or quads comprising the cells and constituting the contents of the cells are accessed in to the frame buffer memory with changing cell addresses according to the address mode cell configuration selected.

The pixel position/cell address mapping X,Y to C,U in two dimensions and X,Y,Z to C,U,S in three dimensions constitutes this second mapping introduced by the present invention for performing graphics operations with multicellular addressing. This mapping relationship is a multiplexing or switching linear permutation transformation using the pairwise logical linear permutation operator Q.sub.p. It is the characteristic of this pairwise LPN operator that it introduces the variable or variance property achieved by the mapping relationships of the present invention, also referred to as the switching or selection property. As a result, multiple addressing modes reading on the permutation bit map are available.

Thus, the present invention differs from conventional raster graphics machines in the following respects. First, the present invention introduces and requires at least three mapping spaces X,Y,Z: B,A.sub.y,A.sub.z ; and C,U,S in contrast to prior art and conventional raster graphics machines which operate between only two mapping spaces. Second, the present invention introduces and requires at least two mapping relationships between at least three novel mapping spaces. One of these mapping relationships represents the invariance property of the system of the present invention, while the other mapping relationship represents the variance or selection property of the system of the present invention. This is in contrast to conventional raster graphics systems which operate with only one invariant mapping relationship. Third, these novel mapping relationships according to the present invention constitute linear permutation transformations which introduce permuted or permutation bit maps. According to one of the mapping relationships the invariant pixel position/bank address mapping is achieved by logical linear permutation networks performing logical linear permutation operations with reversible self-symmetric Boolean logic gates. On the other hand, the second variance or selection pixel position/cell address mapping is accomplished using the pairwise logical multiplexing or switching linear permutation networks Q.sub. p resulting in changing cell addresses for the units of graphics image data according to the selected addressing mode cell configuration.

It is these co-acting features of the multiple bit mapping concept of the present invention which enables and achieves multicellular addressing. In particular, there must be multiple mapping spaces, at least three, with multiple mapping relationships, at least two, between the mapping spaces. One of the mapping relationships represents and implements the invariance property of the pixel position/bank address mapping relationship. At least one other mapping relationship represents the variable or selection property of the pixel position/cell address mapping relationship for the different and multicellular addressing modes. Finally, the mapping spaces and associated bit maps must include permuted, warped, or permutation bit maps in order to be read upon by multiple cell configurations in successive memory cycles and these permutation bit maps are achieved by mapping relationships or transforms in the nature of linear permutations implemented by logical (invariant) (e.g. E.sub.p and C.sub.p) and pairwise logical (switching) (e.g. Q.sub.p) linear permutation networks and operators.

A further example of the multicellular addressing permutation bit map frame buffer architecture of the present invention is described with reference to FIG. 24 and Table 42. This example pertains to a frame buffer raster graphics machine according to the invention with three pixel dimensions X,Y,Z and two blocks dimensions in memory bank address space B,A and cell and unit address space C,U. This system similarly is based upon 16 memory banks B so that L, the logorithm to the base 2 of the number of memory banks, representing the number of index bits of each of the variables X,Y,Z,B,A,C,U is four. The fundamental equations defining this system are as follows:

The static mo or number is indicated by sm while sm' is equal to L-sm. The final address mapping equation for the bank address assignments A in terms of the memory bank designations or assignments B and cell addresses C is given in the final equation.

This address mathematical notation is converted to Boolean logic equation notation in Table 42. This table gives the address circuit lines and connections for the address lines CA between the AGEN 15 and frame buffer permutation bit map memory 12 FIG. 24. In FIG. 24 and accompanying text the bank address assignments A are denoted by the letters CA referring to the designation as cell address lines. The address line designations CA are derived from the fundamental equations for A from Table 42. In this example the basic graphics image data unit U is the quadpixel or quad of four horizontal bits, the block size is 64.times.16 bits and the index size is L=4. Thus each of the variables is expressed by four index the address equations for A in the linear permutation mathematics notation and CA in the Boolean equation notation is diagrammatically presented in the address data mapping flow elements of AGEN 15 in FIG. 24. Of the various registers, XCUR is the origin of the current X variable value, DDH is the source of the h parameter (represented by H in FIG. 24 and Table 42), SM is the source of the static mode parameter number sm (indicated by SM in the Table 42 and FIG. 24), ZCUR is the source of the current variable Z bit value, and YCUR is the source of the current variable Y index bit.

The operation of the data generator circuit component DGEN 22 is similar to that heretofore described except that the DGEN 22 of FIG. 24 operates on data flows from a block organization of two dimensions B,A or C,U.

By way of example the exchange linear permutation E.sub.p is implemented in the DGEN 22 of FIG. 24 using the PRENET 110 and POSTNET 120 circuits which incorporate the exchange LPNs for example of FIGS. 18 and 19. For the DGEN data input 24 to PRENET 110 the input word is the permuted bank number designation or assignment B and the output of the PRENET circuit is the quads or quadpixels in normalized graphics data unit dimension U coordinates. The cell address parameter or index C may then be the permutation control CON for the PRENET permutation network. The output of PRENET circuit 110 goes to the DGEN registers 112, 114 through a possible further wire permutation network transformation according to the operating static mode and permutation bit map definition functions. Thus, conveniently the PCON control for the PRENET permutation network 110 may simply be the cell address C for operation of the DGEN 22 with frame buffer memory permutation bit maps. For operation of DGEN 22 with a frame buffer memory standard bit map the PCON control is zero. The quadpixel unit coordinates U are therefore derived as functions of the memory bank designations B and cell addresses C from the fundamental equation:

The POSTNET output permutation circuit 120 is the inversion of the PRENET circuit 110. The POSTNET LPN circuits implement the exchange inversion of the fundamental theorem namely:

Thus the input to POSTNET permutation circuit 120 from the output of multiplexer 124 is in the quadpixel normalized unit dimension coordinates U the output is in the permuted memory bank assignment coordinates B for return to the frame buffer memory permutation bit map. The POSTNET control index PCON may similarly be the cell address C for the permutation from which the memory bank coordinates B are derived as a function of C and U. While the PCON permutation control signal may be the cell address C for operation of the DGEN 22 with frame buffer permutation bit maps, the control signal is zero for standard bit maps.

For vector operations, the permutation control index PCON[3:0] is derived using the state information in the DGEN registers. For all other operations (including refresh) the PCON parameter is derived from the state information in AGEN and transmitted to DGEN as part of the DOPBUS instruction. The scheme for deriving PCON is the same in both cases from the fundamental theorem equation:

The equations for deriving PCON for a PBM are as follows: ##EQU1##

For an SMB, PCON=0.

The DGEN registers which are used to form the permutation control index signal PCON in the case of vector operations are as follows:

XDST[5:2] supplies the X index

YDST[3:0] supplies the Y index

ZDST supplies the Z bit for DSM=1 or sm=1 operations

DDH[2:0] supplies the h parameter

DGEN operates on successive 32-bit words called "pulls" to implement the full 64-bit cell. PRENET and POSTNET thus operate on successive 32-bit pulls and sequence rules handle the ordering of the pulls to be consistent with the permutation translation. These rules are as follows:

1. The memory control always reads or writes the pulls in numerically increasing order independent of the permutation control value PCON.

2. DGEN loads the lower or upper 32-bits of a register in the order defined by PCON as follows:

a If PCON is 0 then the first pull is saved (or read from) the lower 32 bits and the second pull operates on the upper 32 bits of a register.

b. If PCON is 1 then the first pull is saved (or read from) the upper 32 bits and the second pull operates on the lower 32 bits of a register. These rules are based upon the XOR property of the PCON bits. PCON may be implemented as a counter bit. All DGEN operations have been defined in such a way that successive DSTROBE signals may toggle PCON and PCON will always indicate whether the pull is for the upper 32-bits (PCON=1) or the lower 32-bits (PCON=0) for the entire sequence of the operation. For SBMs, PCON is initially set to zero and PCON then is allowed to count as usual.

In the example of FIG. 24 and Table 42 the designations for the address lines for A, designated CA, to the eight physical memory banks (16 logical memory banks) are followed by two index bits ji, e.g. CAji. The first index bit number j is the "pull" number 0 or 1, while second bit number i is the variable bit number i[3:0] specifying which of the four component bits of the variable. This is not to be confused with the address line designations Ay and A.sub.z or A.sub.Y and A.sub.Z of FIG. 11 and Tables 28, 31, 33, 35, 37 and 33 where the variables AY and AZ are followed by two index bits ij, e.g. AYij and AZij where the first index bit number i is the variable bit number i[3:0]and the second bit number j is the "pull" number 0 or 1.

While the invention has been described with reference to particular example embodiments it is intended to cover all variations, modifications and equivalents within the scope of the following claims.