Nitride/Oxide/Nitride Capacitor Dielectric

FIG. 1 is a cross-sectional view of a composite dielectric capacitor constructed according to the prior art.

FIG. 2 is an energy band diagram for the capacitor of FIG. 1 constructed according to the prior art.

FIG. 3 is a cross-sectional view of a composite dielectric capacitor constructed according to the invention.

FIG. 4 is an energy band diagram for the capacitor of FIG. 3 constructed according to the invention.

FIG. 5 a cross-sectional view of a composite dielectric capacitor constructed according to another embodiment of the invention.

FIG. 6 is a cross-sectional view of a composite dielectric capacitor constructed according to another embodiment of the invention.

Referring now to FIG. 3, a cross-sectional diagram of a capacitor 102 constructed according to the invention is shown. Capacitor 102 has substrate 108, which is single crystal silicon n-type silicon, preferably having <100> orientation. Substrate 108, in the location of capacitor 102, or overall, may be originally of a dopant concentration, or may be implanted to have a desired n-type or p-type dopant concentration, as desired for the operation of the capacitor 102 (as described, for example, in U.S. Pat. No. 4,249,194 issued Feb. 3, 1981 and assigned to Texas Instruments Incorporated). A layer 109 of silicon nitride (Si.sub.3 N.sub.4) overlays the surface of substrate 108 in the desired location, or overall as the case may be; an exemplary end thickness of layer 109 may be in the range of 7.5 nm to 10.0 nm. A layer 110 of silicon dioxide (SiO.sub.2) overlays nitride layer 109; an exemplary thickness for layer 109 may be in the range of 4.0 to 6.0 nm. The layer of silicon dioxide may be thermal oxide, TEOS oxide, or formed by any other well-known technique; preferably oxide layer is formed by the oxidation of a portion of layer 109 as will be described below. A second layer 112 of silicon nitride (Si.sub.3 N.sub.4) is disposed above oxide layer 110, with a thickness in the range, for example, of 7.5 nm to 10.0 nm. Gate electrode 114, formed of polycrystalline silicon, a refractory metal or metal silicide, aluminum or any other well-known gate material is disposed above nitride layer 112 to serve as the second plate of capacitor 102, the first plate being substrate 108.

FIG. 4 illustrates the energy band diagram for capacitor 102 according to the invention. FIG. 4 shows the energy bands for oxide layer 110 and nitride layer 112 similarly as in FIG. 2 for oxide layer 10 and nitride layer 12. Accordingly, in the same manner as capacitor 2 of FIGS. 1 and 2, the leakage of capacitor 102 in the bias condition where gate electrode 114 is at a negative potential relative to substrate 108 is much reduced over a capacitor having only a layer of silicon dioxide as the dielectric material.

However, capacitor 102 has nitride layer 109 underlying oxide layer 110. Accordingly, the energy band diagram of FIG. 4 is symmetric about oxide layer 110. In the condition where gate electrode 114 is positive relative to substrate 108, the electron source for dielectric leakage is substrate 108. As in the case of capacitor 2 of FIGS. 1 and 2, the high energy gap for silicon oxide layer 110 will block hole current, leaving electron current as the primary leakage mechanism. The presence of nitride layer 109 serves as a barrier to electrons sourced from substrate 108, though, in the same manner as nitride layer 112 serves as a tunneling barrier to electrons source from gate electrode 114. Accordingly, in the bias condition of gate electrode 114 being positive relative to substrate 108, the number of electrons reaching silicon dioxide layer 110 is much reduced over that for capacitor 2 of FIGS. 1 and 2, and over that of a capacitor having a single silicon dioxide dielectric layer. Since the number of electrons reaching silicon dioxide layer 110 is reduced, the number of electrons capable of tunneling through oxide layer 110 is also reduced, resulting in reduced leakage current from plate-to-plate of capacitor 108 of FIGS. 3 and 4.

An exemplary fabrication method for capacitor 102 of FIG. 3 begins with the provision of n-type substrate 108, having an orientation preferably of <100>. The thicknesses given herein will be by way of example only, and are not meant to be limiting in any sense. As mentioned above, the dopant concentration of substrate 108 is not critical to the invention, but may be of any desired level by way of selection of the starting material, or by way of ion implantation and diffusion. Substrate 108 receives a standard pre-furnace cleanup, such as by way of Megasonic agitation, followed by a hot nitric acid cleanup and a de-ionized water rinse. A wet etch deglaze in 10% HF can then be performed, if desired. Layer 109 of silicon nitride Si.sub.3 N.sub.4 is then deposited by way of low pressure chemical vapor deposition (LPCVD) to a thickness of approximately 12.0 nm.

Immediately after the LPCVD of nitride layer 109, substrate 108 therewith is subjected to oxide growth in steam, for formation of oxide layer 110. An exemplary method for formation of oxide layer 110 is exposure of substrate 108 with nitride layer 109 in place in a furnace at 950 degrees Celsius, for five minutes in an argon environment, followed by ten minutes exposure to oxygen gas, followed by forty-six minutes of steam, followed by five minutes of argon. As a result, a portion of nitride layer 109 is oxidized, resulting in layer 110 of silicon dioxide approximately 5.0 nm thick, with silicon nitride layer 109 having a resulting thickness approximately 9.0 nm thick.

Silicon nitride Si.sub.3 N.sub.4 layer 112 is then deposited by LPCVD over oxide layer 110 to a thickness of approximately 11.0 nm. Subsequent cleanup and LPCVD deposition of polycrystalline silicon to form gate electrode 114 is then performed according to conventional techniques. The polysilicon layer from which gate electrode 114 is formed may be phosphorous doped as desired. The polysilicon may then be patterned by way of conventional photolithography techniques, and etched to define gate electrode 114 as shown in FIG. 3. The underlying layers 109, 110 and 112 may also be etched with the same pattern as gate electrode 114, as desired. Subsequent processing to complete the integrated circuit into which capacitor 102 is to be incorporated now can follow.

For capacitor 108 constructed as described hereinabove, the electric field required to cause plate-to-plate leakage of approximately 10.sup.-4 amperes is approximately 50% greater than the field required to cause such leakage in a similarly sized capacitor having a single silicon dioxide layer as the capacitor dielectric. The symmetry of capacitor 108 so constructed is within 10% of the effective electric field value. It should be noted that, for a similarly constructed capacitor 2 of FIGS. 1 and 2, the leakage improvement is theoretically at the 50% improvement seen for capacitor 108 according to the invention for the negative bias condition, but would remain at the single silicon dioxide layer level for the positive bias condition.

It should be apparent, of course, that various configurations of capacitors having the nitride/oxide/nitride composite dielectric film may be constructed. Referring to FIG. 5, a trench capacitor 202 is illustrated, formed into a trench 201 which is etched into substrate 208 as is well known in the art. Along the sidewalls and bottom of trench 201 is Si.sub.3 N.sub.4 layer 209, silicon dioxide layer 210, and Si.sub.3 N.sub.4 layer 212, formed in a similar manner as described hereinabove for the planar capacitor 108 of FIG. 4 but disposed within trench 201. It should be noted that LPCVD silicon nitride is quite conformal when deposited, allowing trench capacitor 202 to be easily formed according to the instant invention; indeed, nitride layer 209 is likely to be substantially more uniform in thickness in trench 201 than a layer of silicon dioxide thermally grown in trench 201. Gate electrode 214 is then deposited within trench 201 as is well known in the trench formation art, to form capacitor 202.

Referring now to FIG. 6, another embodiment of the capacitor according to the instant invention is illustrated. Capacitor 302 of FIG. 6 is formed on a silicon layer 322 which is isolated from substrate 308 by an insulating layer 320. Silicon layer 322 may be polycrystalline silicon, or may be single-crystal silicon which is recrystallized from the polycrystalline form, or in any other form known for forming silicon-on-insulator material. Si.sub.3 N.sub.4 layer 309 is disposed above silicon layer 322, silicon dioxide layer 310 is disposed above nitride layer 309, and Si.sub.3 N.sub.4 layer 312 is disposed above oxide layer 310 in the manner described hereinabove. Gate electrode 314 is then formed and patterned to form the second plate of capacitor 308.

An isolated capacitor may also be formed by the combination of the capacitor 302 of FIG. 6 disposed into a trench, as well as in a multitude of other configurations apparent to those of ordinary skill in the art.

As a result of the above structure for a capacitor dielectric, a capacitor may be formed with an enhanced dielectric constant over a single silicon dioxide layer and thereby with improved capacitance per unit area. Such a capacitor has improved leakage characteristics which are independent of the polarity of bias, and may be formed by using known process steps in the semiconductor art.

Although the invention has been described in detail herein with reference to its preferred embodiments, it is to be understood that this description is by way of example only, and is not to be construed in a limiting sense. It is to be further understood that numerous changes in the details of the embodiments of the invention, and additional embodiments of the invention, will be apparent to, and may be made by, persons of ordinary skill in the art having reference to this description. It is contemplated that such changes and additional embodiments are within the spirit and true scope of the invention as claimed below.