PCM Recording and Reproducing Apparatus Having Common Data Frame Construction for Signal Sources of Varying Quantization Bit Number

The present invention relates to a PCM (Pulse Code Modulation) recording and reproducing apparatus, and more particularly to that which gives a bit number appropriate to frame constructions for a plurality of kinds of quantization bit numbers.

There exists a PCM audio recorder as a device for recording and reproducing signals by conducting an A/D conversion by sampling analog signals at a sampling frequency Fs to obtain PCM data, constructing a frame by putting together a plurality of PCM data, and dividing (sharing) the same into a plurality of tracks. FIG. 1 shows a frame and a block construction of such a PCM recording apparatus, figure (a) shows a frame construction and figure (b) shows a block construction. One frame comprises 252 bits, and this comprises 14 samples of PCM data each quantized into 16 bits, 10 bits of a synchronous signal, 2 bits of a control signal, and 16 bits of C1 inspection data for error detection and correction. FIG. 1(b) shows a block construction in which frame constructed signals are recorded in a total of 8 tracks with 6 tracks for the PCM data and 2 tracks for the error detection correction data. The frame construction of FIG. 1 is determined in the following way.

Suppose that the number of channels of analog signals is N, the number of samples constituting one frame is S, and the number of tracks for recording the PCM data is Tr, the frame and block frequency F.sub.B is represented by the following formula. ##EQU1##

Supposing that the number of bits in one frame is T.sub.S, T.sub.S is represented by the following.

Herein, B is a quantization bit number of a sample (number of bits per sample), and m is a number of additional bits such as of a synchronous signal. The transmission frequency Fc for transmitting the bits in the frame is represented by the following formula.

Then, if the ratio of F.sub.C and F.sub.S .times.N becomes a simple integer, F.sub.C and F.sub.S .times.N can be generated from one clock, and the values of S and m are selected so as to enable the same. In the case of FIG. 1, N=2, S=14, Tr=6, and the block frequency F.sub.B becomes ##EQU2## when the F.sub.S is 48 kHz. Because the synchronous signal comprises 10 bits, the control signal comprises 2 bits, and C.sub.1 inspection data comprises 16 bits, the m=10+2+16=28. In addition, B=16, and thus T.sub.S =16.times.14+28=252 bits from the formula (4). Accordingly, from the formula (5) F.sub.C =252.times.1.143 kHz=288 kHz, and the ratio of F.sub.C and F.sub.S .times.N becomes a simple integer, that is, 288:48.times.2=3:1. Such a clock can be generated by the clock generator of FIG. 2.

In FIG. 2, the reference numeral 1 designates a master clock oscillator, the reference numeral 2 designates a .div.6 frequency divider, the reference numeral 3 designates a .div.42 frequency divider, the reference numeral 4 designates a 252 counter, and the reference numerals 5, 6, 7, and 8 are output terminals. A signal of 288 kHz is generated by the .div. master clock oscillator 1, and this signal is sent to the 6 frequency divider 2, the 252 counter 4, and the output terminal 6. The output of the .div.6 frequency divider 2 becomes 48 kHz, and this is sent to the .div.42 frequency divider 3 and the output terminal 8. The 252 counter 4 outputs clock signals required for such as the generation of the synchronous signal and the control signal to the output terminal 5. The .div.42 frequency divider 3 outputs clocks of block frequency F.sub.B to the output terminal 8.

FIG. 3 shows a block diagram of a PCM recording and reproducing apparatus which uses such a frame construction. In FIG. 3, the reference numeral 9 designates an input terminal for 2 channels of analog signals. The reference numeral 10 designates an A/D converter, the reference numeral 11 designates an encoder circuit, the reference numeral 12 designates a track sharing circuit, the reference numerals 13, 14, and 15 designate modulation circuits, the reference numerals 16, 17, and 18 designate recording amplifiers, the reference numerals 19, 20, and 21 designate recording heads, the reference numerals 22, 23, and 24 designate reproduction heads, the reference numerals 25, 26 and 27 designate reproduction amplifiers, the reference numerals 28, 29, and 30 designate demodulation circuits, the reference numerals 31, 32, and 33 designate time axis correction circuits (hereinafter referred to as "TBC circuit"), the reference numeral 34 designates a decoder circuit, the reference numeral 35 designates a D/A converter, the reference numeral 36 designates each channel analog output terminal, and the reference numeral 37 designates a clock generator.

The device operates as follows.

First of all, at the recording side, recording an analog signal input from the input terminal 9 is converted into PCM data having a quantization bit number B=16 by the A/D converter 10, and two error correction detection codes, that is, C.sub.2 inspection data and C.sub.1 inspection data are added thereto by the encoder circuit 11 so as to enable detecting and correcting errors due to limitations of the recording medium. A control signal is added to the encoded signal by the track sharing circuit 12, and the encoded signals split into 8 tracks to be sent to the modulation circuits 13, 14, and 15. These signals are modulated into signals appropriate for recording and reproducing on a recording medium by the modulation circuits 13, 14, and 15, a synchronous signal is added thereto, and this signal is recorded on a medium through the recording amplifiers 16, 17, and 18 and the recording heads 19, 20, and 21. At the reproduction side, the signals reproduced by the reproduction heads 22, 23, and 24 are amplified by the reproduction amplifiers 25, 26, and 27, the synchronous signals are detected and protected by the demodulation circuits 28, 29, and 30, the clocks are reproduced, and the clocks and the data from which the synchronous signals are separated are sent to the TBC circuits 31, 32, and 33. In the TBC circuits 31, 32, and 33 jitter and wow flutters are removed from the reproduced data, and the corrected data are sent to the decoder circuit 34. In the decoder circuit 34 error detection and correction of the data is conducted using the C.sub.1 inspection data and the C.sub.2 inspection data, the data is converted into the original analogue signal by the D/A converter 35, and it is output from the output terminal 36. Besides, the control signal is used for the control of the apparatus such as the control of the existence or non-existence of emphasis or the control of the frequency F.sub.S. The clock generator 37 is fundamentally constituted as shown in FIG. 2. A clock of frequency F.sub.S is sent to the A/D converter 10 and the D/A converter 35, and clocks of frequency F.sub.C and F.sub.B and the output of the output terminal 5 are sent to the track sharing circuit 12, the modulation circuits 13, 14, and 15, and the TBC circuits 31, 32, and 33.

In such a recording and reproducing apparatus a frame/block construction of FIG. 4 is utilized in a case where a second quantization bit number B.sub.2 =20 is used. Because there is only a difference in the quantization bit number relative to FIG. 1, T.sub.S becomes 20.times.14+28=308 from the formula (4), and F.sub.C becomes 1.143 kHz.times.308=352 WkHz from the formula (5). In this way, the bit number of one frame varies dependent on the quantization bit number such that 252 for a quantization bit numnber 16 and 308 for a quantization bit number 20. The main portion of a clock generator which corresponds to these two quantization bit numbers is shown in FIG. 5. In FIG. 5, the reference numeral 38 designates a master clock oscillator having a frequency of 3.168 MHz, the reference numeral 39 designates .div.11 frequency divider, the reference numeral 40 designates a .div.66 frequency divider, the reference numeral 41 designates a .div.9 frequency divider, the reference numeral 42 designates a 252 counter, the reference numeral 43 designates a .div.42 frequency divider, the reference numeral 44 designates a 308 counter, and the reference numerals 45, 46, 47, 48, 49, and 50 designate output terminals. When the quantization bit number is 16, the signals of the output terminals 45, 46, 47, and 48 are used as outputs, and when the quantization bit number is 20, the signals of the output terminals 47, 48, 49, and 50 are used as outputs.

The frame construction of the above-described PCM recording and reproducing apparatus has the following drawbacks.

First of all, as is apparent from FIGS. 2 and 5, the frequency of the master clock need become higher by eleven times as from 288 kHz to 3.168 MHz in order for the device to accommodate two quantization bit numbers, and this disadvantageously reduces the freedom of selection of clocks in a PCM recording and reproducing apparatus which uses various clocks for encoding. Further, the signals of the output terminals 45 to 50 are sent to the track sharing circuit 12 and the TBC circuits 31, 32, and 33, and if the bit number of one frame is changed, the control becomes complicated because these circuits usually use memories. Furthermore, when the bit number of one frame is changed the synchronous signal protection circuit in the decoder circuits 28, 29, and 30 does not operate, and the clocks to be sent to the TBC circuits 31, 32, and 33 must be switched for each track, thereby making the hardware complicated.

An object of the present invention is to provide an improved PCM recording and reproducing apparatus in which a frame bit number is the same with respect to more than two quantization bit numbers without making the master clock frequency higher, and which is capable of constituting using a track sharing circuit, modulation circuits, demodulation circuits, and TBC circuits of simple construction.

Another object of the present invention is to provide an improved PCM recording and reproducing apparatus which has a PCM data arrangement capable of increasing the cross fade period without lowering the burst error correction ability, and of having a constant memory capacity.

A further object of the present invention is to provide an improved PCM recording and reproducing apparatus capable of conducting encoding and decoding easily even in cases having different quantization bit numbers with the use of the same error correction encoder and decoder.

Other objects and advantages of the present invention will become apparent from the detailed description given hereinafter; it should be understood, however, that the detailed description and specific embodiment are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.

According to the present invention, there is provided a PCM recording and reproducing apparatus in which N channels (N is an integer) of analog signals are analog-to-digital converted by a sampling frequency Fs to be converted into PCM data, several PCM data are put together to constitute a frame, and the PCM data are divided into Tr tracks (Tr is an integer), wherein ratio of the TA to TB is represented by a simple integer assuming that k quantization bit numbers are represented by Bi (i=1, . . . , k), and the recording is conducted with making TA the same through all the quantization bit numbers as a bit nunber of one frame.

Herein,

n: integer,

m: an additional number of bits such as for a synchronous signal,

LCM (Bi(i=1, . . . , k): a least common multiple of the Bi(i=1, . . . k), and

S: the number of samples constituting a frame.

FIG. 1, consisting of (a) and (b), is a diagram showing a frame/block construction in a case where the quantization bit number is 16 in a conventional PCM recording and reproducing apparatus;

FIG. 2 is a block diagram showing a clock generator of the conventional device;

FIG. 3 is a block diagram showing a multi track PCM recording and reproducing apparatus;

FIG. 4, consisting of (a) and (b), is a diagram showing a frame/block construction in a case where the quantization bit number is 20 in a PCM recording and reproducing apparatus;

FIG. 5 is a block diagram showing a clock generator for realizing both of the frame/block constructions of FIG. 1 and FIG. 4;

FIG. 6, consisting of (a) and (b), is a diagram showing a frame/block construction of the PCM recording and reproducing apparatus as a first embodiment of the present invention;

FIG. 7 is a block diagram showing a clock generator of the above-described embodiment;

FIG. 8 is a diagram showing a data arrangement on the recording and reproducing material in the conventional device;

FIG. 9 is a diagram showing the concept of the encoding and data interleaving sequence of the conventional device;

FIG. 10 is a block diagram showing an encoder circuit of a PCM recording and reproducing apparatus which conducts the recording and reproduction utilizing such a data arrangement;

FIG. 11, (A)-(C), is a diagram showing the concept of the reproduced signal at a hand cut edition;

FIG. 12 is a diagram showing a data arrangement on the recording and reproducing material of a PCM recording and reproducing apparatus as a second embodiment of the present invention;

FIG. 13 is a diagram showing the concept of the encoding and data interleaving sequence of the second embodiment;

FIG. 14 is a diagram showing the concept of the frame and block construction in view of the relationship between the symbol and the word of a conventional device;

FIG. 15 is a diagram showing an encoder circuit equivalent to the circuit of FIG. 10;

FIG. 16 is a circuit diagram showing a data division circuit which produces the relationship between the symbol and the word of FIG. 14 in a case where Q=16 bits;

FIG. 17 is a circuit diagram showing a data division circuit corresponding to the circuit of FIG. 16 in a case where Q=20 bits;

FIG. 18 is a diagram showing the concept of the relationship between the word and the symbol in a third embodiment of the present invention;

FIG. 19 is a circuit diagram showing a data division circuit of the third embodiment of the present invention;

FIG. 20 is a diagram showing a concept illustrating the relationship between the word and the symbol in a fourth embodiment of the present invention; and

FIG. 21 is a circuit diagram showing a data division circuit of the fourth embodiment of the present invention.

In order to explain the present invention in detail reference will be particularly made to FIG. 6.

FIG. 6(a) shows a frame construction and 6(b) shows a block construction of a PCM recording and reproducing apparatus as a first embodiment of the present invention. This frame construction comprises a total of 360 bits including 16 bits of a synchronous signal, 8 bits of a control signal, 320 bits of PCM data or C.sub.2 inspection data, and 16 bits of C.sub.1 inspection data. This frame construction is determined from the following.

If it is assumed that the channel number N=2, the sharing track number of PCM data Tr=6, and the two quantization bit numbers B.sub.1 =16, B.sub.2 =20, then the LCM (least common multiple) (B.sub.1, B.sub.2) represented by the formula (1) becomes 80. The quotient of this LCM 80 by the one word bit number 16 is 5, but this is desired to be an even number in a case of two channels. Table 1 and Table 2 show the results obtained by calculating the formulae (1) and (2) using 80.times.2=160 bits instead of 80 and selecting the cases where the ratio of T.sub.A to T.sub.B is a simple integer. Table 1 shows a case where a quantization bit number B.sub.1 =16, and Table 2 shows a case where the quantization bit number B.sub.2 =20.

Herein, P:Q represents the ratio of T.sub.A to T.sub.B and those having Q less than 10 are listed in these tables. F.sub.M is a master clock frequency. An even number from 24 to 48 bits is adopted as in because the system includes a synchronous signal, a control signal, and C.sub.1 inspection data. The frame/block construction of FIG. 6 having T.sub.A =360 bits is obtained by selecting a value of T.sub.A which is present in both of the Tables 1 and 2.

The main portion of a clock generator realizing such a frame/block construction is shown in FIG. 7. In FIG. 7, the reference numeral 51 designates a master clock oscillator, the reference numeral 52 designates a .div.5 frequency divider, the reference numeral 53 designates a .div.30 frequency divider, the reference numeral 54 designates a .div.4 frequency divider, the reference numeral 55 designates a .div.60 frequency divider, the reference numeral designates a .div.48 frequency divider, the reference numeral 57 designates a switch, the reference numeral 58 designates a 360 counter, and the reference numerals 59 to 64 designate output terminals.

As is apparent from Tables 1 and 2, the master clock oscillator 51 generates a clock of 1.44 MHz, and this is sent to the .div.5 frequency divider 52, the .div.30 frequency divider 53, and the .div.4 frequency divider 54. The output of the .div.5 frequency divider 52 becomes a frequency F.sub.Cl =288 kHz which corresponds to the quantization bit number B.sub.1 =16, and this is sent to the output terminal 59. The output of the .div.4 frequency divider 54 becomes a frequency F.sub.C2 =360 kHz which corresponds to the quantization bit number B.sub.2 =20, and is sent to the output terminal 63. The output of the .div.30 frequency divider 53 becomes a frequency of F.sub.S =48 kHz, and this is sent to the .div.60 frequency divider 55, the .div.48 frequency divider 56, and the output terminal 61. The output F.sub.B1 =0.8 kHz of the .div.60 frequency divider 55 and the output F.sub.B2 =1 KHz of the .div.48 frequency divider 56 are sent to the output terminals 60 and 62, respectively. The switch 57 outputs the output of the .div.5 frequency divider 52 when the quantization bit number B.sub.1 =16, and the output of the .div. 4 frequency divider 54 when the quantization bit number B.sub.2 =20.

In this first embodiment the same number of bits per frame is used for more than two quantization bit numbers, thereby enabling the hardware of the recording and reproducing apparatus to be simplified and the frequency of the master clock to be lowered.

In the above-illustrated first embodiment the channel number N=2 and the track number Tr=6, but it is obvious that the frame bit number can be determined in accordance with the formulae (1) and (2) also in other cases having different channel numbers and different track numbers.

Furthermore, the illustrated embodiment has two quantization bit numbers (B.sub.1 =16, B.sub.2 =20), but it is obvious that the device may have more than two quantization bit numbers, and the formulae (1) and (2) are also effective in that case.

Furthermore, a multi-track recording and reproducing apparatus of Tr=6 is described in the illustrated embodiment, but the present invention is also applicable to a case where the recording and reproducing are conducted successively by one transmission line in the order of the track 1, track 2, . . . , track 6, track 7, track 8, track 1, . . . .

In the above-described first embodiment, however, the A/D converted PCM data are not frame constituted in the order of appearance, but frame constituted by being interleaved so as to diversify burst errors which occur due to dropouts at the reproduction, and putting together the PCM data which is delayed for a predetermined time.

FIG. 8 shows the manner in which the PCM data are interleaved on the recording and reproducing material in a conventional device. The A/D converted PCM data are generated in the order of W.sub.0, W.sub.1, W.sub.2, . . . . Herein, W designates one word of the PCM data sampled at one time, and this is data of 32 bit=2 channels.times.16 bits. Furthermore, the PCM data such as W.sub.1 ', W.sub.3 ', . . . , W.sub.11 ' are delayed odd number PCM data which are delayed by a delay time d.sub.1 relative to the odd number PCM data W.sub.1, W.sub.3, . . . , W.sub.11 among the PCM data W.sub.0 to W.sub.11. The C.sub.0, C.sub.1, C.sub.2, and C.sub.3 are C.sub.2 inspection data generated for the even number PCM data and the delayed odd number PCM data W.sub.0, W.sub.1 ', W.sub.2, W.sub.3 ', . . . among the above-described PCM data.

FIG. 9 shows a data interleaving sequence for arranging the even number PCM data, the odd number PCM data, the delayed odd number PCM data, and the C.sub.2 inspection data which are shown in FIG. 8. The interleaving operation will be described with reference to FIG. 9.

First of all, the A/D converted PCM data are separated into even number PCM data W.sub.12i, W.sub.12i+2, . . . and odd number PCM data W.sub.12i+1, and W.sub.12i+3, . . . , and the odd number PCM data is delayed by d.sub.1. Next, C.sub.2 encoding is conducted against the even number PCM data and the d.sub.1 delayed odd number PCM data, thereby generating n=4 words of C.sub.2 inspection data as C.sub.4i+3, C.sub.4i+2, C.sub.4i+1, and C.sub.4i+0. Subsequently, the delayed odd number PCM data and the 2 (=n-n.sub.1) words of C.sub.2 inspection data C.sub.4i+3 and C.sub.4i+1 are delayed by d.sub.2, and furthermore delays of d.sub.3 to 7d.sub.3 are given to each data as shown in FIG. 9. Herein, i of the W.sub.12i+1 is an integer, and the pattern of data interleaving is repeated at every 12 data. Furthermore, in the example of FIG. 8, d.sub.1 =20T], d.sub.2 =160[T], and d.sub.3 =20[T], where the delay in one block is 5[T].

In this way, each data is arranged as shown in FIG. 8. That is, the even number PCM data and the odd number PCM data are arranged apart from each other, thereby enabling the conducting of a correction by using a mean value interleaving with the use of the previous and the following value even when a burst error arises. Furthermore, the odd number PCM data having different delays are providing so as to enable the preventing of abnormal sounds caused by correcting the even number PCM data by the inspection data for the odd number PCM data W.sub.1, W.sub.3, . . . and the PCM data are successively corrected in such a case where the encoded data cannot be corrected by the C.sub.2 inspection data and are judged to be perfectly errors.

FIG. 10 shows a block diagram of the encoder circuit 11 of a PCM recording and reproducing apparatus which conducts recording and reproduction utilizing such a data arrangement. The reference numeral 65 designates a memory, the reference numeral 66 designates a memory control circuit, the reference numeral 67 designates a C.sub.1 encoder, and the reference numeral 68 designates a C.sub.2 encoder. In order to simplify the memory control circuit 66, it is desirable that the capacity of the memory is divided into 61 block portions and that the PCM data from the A/D converter 10 are successively recorded at the positions of W.sub.0, W.sub.1, W.sub.2, . . . as shown in FIG. 8. In this system, the C.sub.2 encoding is then conducted by taking out the PCM data in the order of W.sub.0, W.sub.1 ', W.sub.2, . . . from the memory 65 thereby to conduct C.sub.2 encoding, and the C.sub.2 inspection data is stored in the memory 65. Thus, the C.sub.2 encoded data is stored by more than one frame, and C.sub.1 encoding is conducted by the C.sub. 1 encoder 67, thereby to generate C.sub.1 inspection data. The encoded data in this way is sent to the track sharing circuit 12.

This conventional PCM recording and reproducing apparatus with such a construction has a property described below. As apparent from FIG. 8, the C.sub.2 encoded data is diversified to 61 blocks at equal intervals at every 4 blocks, and the error correction ability when an error is generated at every block becomes that of 16 blocks because four errors can be corrected in a case where the error is detected by the C.sub.1 code and corrected by the C.sub.2 code, for example, in such a case where a Reed Solomon code on a Galois field (2.sup.8) dealing with 8 bits as a unit (1 symbol) is used as the C.sub.2 error correction code.

On the other hand, there may be a case where a hand cut edition is conducted by such PCM recording and reproducing apparatus. FIG. 11 shows the concept of this hand cut edition. Now suppose that two recording materials to which the recordings are conducted separately are connected with each other at a connecting point. As the signals are recorded separately into materials 1 and 2, when the reproduction is conducted from the left side, signals are reproduced in the order from the usual reproduction section A, the error correction section B, and the error correction section C in the material 1. To the contrary, the signal in the material 2 is reproduced in the order reverse to the above-mentioned one, that is, from the error correction section C, the error correction section B, and the usual reproduction section A. Herein, the error correction section B is a section where the original signal can be recovered by conducting an error correction by the C.sub.1 and C.sub.2 code, and the error correction section C is a section where an error can be interpolated one after another sample with the even number PCM data or the odd number PCM data being reproduced correctly regardless of the fact that the error correction can not be conducted. The signals of the materials 1 and 2 are reproduced in this way, and the signals of the error interpolating section C overlap with each other as shown in FIG. 11. By conducting a fade-out of the signal of the material 1 and a fade-in of the signal of the material 2, and adding both signals (hereinafter referred to as "cross-fading"), the reproduced signal at the hand cut edition point can be made smooth. The section in which this cross-fading can be conducted is determined in accordance with the data arrangement of FIG. 8, as there are twelve blocks between the last word W.sub.10 of the even number PCM data and the first word W.sub.1 of the odd number PCM data.

Next is a consideration with raising concrete values. If it is supposed that the sampling frequency F.sub.S is 48 kHz, then one frame is constituted by 10 pieces of 2 channel data, PCM data is arranged on 6 tracks, and the frequency of one block becomes 48/(10.times.6)=0.8 KHz. Accordingly, the time period of the 12 block cross-fading section becomes 12/0.8 KHz=15 msec. Actually errors are generated at the neighborhood of the hand cut edition point, and this time period is further shortened. Furthermore, the above-described example is a case where the quantization bit number is 16, and the cross-fading time is also shortened in a case where the quantization bit number is 20.

In the conventional PCM recording and reproducing apparatus with such a construction, only 12 blocks can be used as the cross-fading section at the hand cut edition, and it cannot correspond to a case where a long cross-fading time is required.

A second embodiment of the present invention will be described.

FIG. 12 shows an arrangement of the PCM data on a recording and reproducing medium in a second embodiment of the present invention. The A/D converted PCM data are generated in the order of W.sub.0, W.sub.1, W.sub.2, . . . . W.sub.0, W.sub.2, W.sub.4, . . . are even number PCM data, W.sub.1, W.sub.3, W.sub.5, . . . are odd number PCM data, and W.sub.1 ', W.sub.3 ', W.sub.5 ' are delayed odd number PCM data. The reference characters C.sub.3, C.sub.2, C.sub.1, C.sub.0 designate inspection data of the C.sub.2 code, and they are generated from the even number PCM data and the delayed odd number PCM data. The inspection data C.sub.3 and C.sub.1 are arranged subsequent to the even number PCM data and the inspection data C.sub.2 and C.sub.0 are arranged subsequent to the delayed odd number PCM data. Each PCM data is arranged apart from each other by 4 blocks.

The method of generating the data arrangement of FIG. 12 will be described with reference to FIG. 13 which shows the encoding and the data interleaving sequence of this second embodiment.

Among the A/D converted PCM data odd number PCM data W.sub.12i+1, W.sub.12i+3, . . . are delayed by d.sub.1. Next, C.sub.2 encoding is conducted from the even number PCM data and the delayed odd number PCM data, and n=4 words of C.sub.2 inspection data are generated as C.sub.4i+3, C.sub.4i+2, C.sub.4i+1, C.sub.4i+0. Subsequently thereto, a delay d.sub.2 is given to the delayed odd number PCM data and to the (n-n.sub.1)=2 words of C.sub.2 inspection data C.sub.4i+2, C.sub.4i+0, and delays d.sub.3 to 7d.sub.3 are given to the respective data as shown in FIG. 13. In this way a data arrangement shown in FIG. 12 is obtained. Herein, i of the W.sub.12i+1 is an integer, and the pattern of data interleaving is repeated at every 12 data words. Suppose that one word comprises 2 channels of 16 bits, the C.sub.1 inspection data is generated by the C.sub.1 encoding for each track after the sequence of FIG. 13 is repeated 5=320/(2.times.16.times.2) times from the frame construction of FIG. 6 because the W.sub.12i and the W.sub.12i+7 are arranged at the same track. The d.sub.1 =40[T], d.sub.2 =160[T], and d.sub.3 =20[T], where the delay in one block is 5[T].

The encoder circuit for obtaining such a data arrangement is obtained by only changing the memory control circuit 66 of the encoder circuit 3 shown in FIG. 10 so that it complies with the delays of FIG. 13, and the memory capacity may be a capacity corresponding to 61 blocks similarly as the conventional device. Furthermore, the decoder circuit 34 can be easily obtained by constituting a sequence reverse to that shown in FIG. 13.

The PCM recording and reproducing apparatus of this second embodment has the following properties. That is, the burst error correction ability amounts to 16 block errors in a case where errors are generated at each block because 4 errors can be corrected by C.sub.2 code, for example, in a case where a Reed Solomon code on a Galois field (2.sup.8) dealing with 8 bits as a unit (a symbol) is used as the C.sub.2 correction code, similarly as the conventional device. Next, the cross-fade period at the connecting point in conducting a hand cut edition becomes 20 blocks between the last data W.sub.10 of the even number PCM data and the first data W.sub.1 of the odd number PCM data, showing an improvement. This is 25 msec when the Fs is 48 KHz, and this is 1.7 times as that of the conventional device.

As is evident from the foregoing description, according to the second embodiment, the C.sub.2 inspection data are separately arranged at equal intervals subsequent to the even number PCM data and to the delayed odd number PCM data which constitutes a C.sub.2 code together, and the odd number PCM data is spaced apart from the even number PCM data as much as possible, whereby an apparatus which has a constant memory capacity and is capable of obtaining the highest burst error correction ability and of increasing the cross-fade period of the hand cut edition is obtained.

In the above-illustrated second embodiment, the number of C.sub.2 inspection data arranged subsequent to the even number PCM data and that arranged subsequent to the delayed odd number PCM data are made equal to each other, and d.sub.1 is made equal to (n-n.sub.1).times.d.sub.3, but even in a case where n.sub.1 .noteq.n.sub.2 the same effects can be obtained. Furthermore, the biggest effects are obtained when d.sub.1 =(n-n.sub.1).times.d.sub.3, but d.sub.1 may not be equal to n.sub.2 .times.d.sub.2.

By the way, as the C.sub.2 error correction code a Reed Solomon code on a Galois field (2.sup.8) dealing with 8 bits as a unit (a symbol) is used. The codes which are adopted in such as CD players or DAT (digital audio tape) decks are equivalent ones to this Reed Solomon code. When the number of bits of one symbol is increased the signal processing ability of the error correction encoder and decoder are enhanced, but to the contrary the size of the hardware is enlarged. When GF (2.sup.10) is used instead of GF (2.sup.8) the size of the hardware becomes about 4 times, and this is not practical. Accordingly, usually a code of 8 bits per symbol is used. However, code interleaving must be conducted at a word unit as described above, and the relationship between the word and the symbol should be considered in conducting the interleaving.

FIG. 14 shows a word construction. One word comprises a total of 32 bits including 16 bits of the channel 1 (CH 1) and 16 bits of the channel 2 (CH2). The 16 bits of each channel is divided into an upper 8 bits and a lower 8 bits, the upper 8 bits of the channel 1 (CH1) is made a first symbol, the lower 8 bits of the channel 1 (CH2) is made a second symbol, the upper 8 bits of the channel 2 is made a third symbol, and the lower 8 bits of the channel 2 is made a fourth symbol. Thus, one word comprises 4 symbols. The encoding is conducted to obtain C.sub.0, . . . , C.sub.3 by generating an inspection word from the first symbol of each word of W.sub.0, W.sub.1 ', W.sub.2, W.sub.3 ', . . . , W.sub.11 '. The similar encodings are also applied to the 2nd, 3rd, and 4th symbol. Herein, it is fundamental that data of one channel is represented by 2 symbols.

The circuit of FIG. 10 which is an encoder circuit of a PCM recording and reproducing apparatus shown in FIG. 3 having such a frame construction can be represented as shown in the circuit of FIG. 15. In FIG. 15, the reference numeral 69 designates a data division circuit, the numeral 70 designates an interleaving circuit, and the numeral 71 designates an error correction encoder circuit. The data division circuit 69 has the function described with reference to FIG. 14, and the PCM data of 32 bits of the channel 1 and the channel 2 from the A/D converter 2 is made one word, and this is divided into 4 symbols to be transferred to the interleaving circuit 70. In the interleaving circuit 70 an interleaving described with reference to FIG. 13 is conducted, and the encoded data is sent to the track sharing circuit 12. The error correction encoder circuit 71 takes a predetermined data from the interleaving circuit 70 (W.sub.0, W.sub.1 ', W.sub.2, W.sub.3 ', . . . in FIG. 13) to conduct an encoding, and the generated inspection data are written into a predetermined position (C.sub.0, C.sub.1, . . . in FIG. 13).

The data division circuit 69 is realized by the circuit of FIG. 16. The reference numerals 72 and 73 designate a data latch circuit, and the reference numeral 74 designates a selector circuit. In the data latch circuits 72 and 73 two channel PCM data of 32 bits sent from the A/D converter 2 is taken in at each pulse of sampling frequency fs, and it is held until the next data is input thereto. The selector circuit 74 selects successively the upper 8 bits of the data latch 72, the lower 8 bits of the data latch 72, the upper 8 bits of the data latch 73, and the lower 8 bits of the data latch 73 to output a, b, c, d by the select signal, and they are sent to the interleaving circuit 70 at every 8 bits (a symbol).

The conventional PCM recording and reproducing apparatus is constructed in such a manner, and when the number of bits of the A/D converter is changed the bit number of one symbol of the data division circuit 69 need be changed similarly. For example, in a case of 2 channels and a quantization bit number of 20 bits the circuit becomes one shown in FIG. 17, and 1 symbol must comprise 10 bits. Herein, the reference numerals 75 and 76 designate data latches of 20 bits, and the reference numeral 77 designates a selector circuit of 10 bits. However, as described above, an error correction circuit in a case where 1 symbol comprises 10 bits (an encoder of an error correction code on a GF (2.sup.10)) becomes to have a large sized hardware, and this is not practical. Furthermore, although only the encoder is described above, the decoder also becomes have a large sized hardware because a procedure reverse to that of the encoding procedure must be conducted in the decoder.

As described above in the conventional device the 1 symbol bit number of the error correction encoder and decoder need be changed in accordance with the quantization bit number of the PCM data, thereby resulting in an increased circuit size. Furthermore, it cannot accommodate a case where the same error correction encoder and decoder are used and only the quantization bit number is changed.

The third embodiment of the present invention will be described in the following.

This embodiment is an example in a case where Q=20, N=2, and l=8 which satisfies the formula (1). FIG. 18 shows a word construction in a case where the quantization bit number is 20. 1 word comprises a total of 40 bits including 20 bits of the first channel CH1 and 20 bits of the second channel CH2. The 20 bits of the first channel CH1 is divided into an upper 8 bits, a middle 8 bits, and a lower 4 bits, and the 20 bits of the second channel CH2 is divided into an upper 4 bits, a middle 8 bits, and a lower 8 bits. The upper 8 bits of the first channel CH1 and the middle 8 bits of the first channel CH1 are made a first symbol and a second symbol, respectively, and the 8 bits comprising the lower 4 bits of the first channel CH1 and the upper 4 bits of the second channel CH2 is made a third symbol, the middle 8 bits and the lower 8 bits of the second channel CH2 are made a fourth symbol and a fifth symbol, respectively. Thus, one word comprises 5 symbols. The error correction encoding is conducted by C.sub.2 encoding collecting 1 symbol from each word of the code interleaving similarly as the conventional device.

The data division circuit 69 of this case is realized by the circuit of FIG. 19. In the data latch circuits 75 and 76 the two channels of PCM data 40 bits sent from the A/D converter 10 are taken in at each pulse of sampling frequency fs, and it is held until the next data is input thereto. The selector circuit 78 selects the upper 8 bits of the data latch 75, the middle 8 bits of the data latch 75, the lower 4 bits of the data latch 75 and the upper 4 bits of the data latch 76, the middle 8 bits of the data latch 76, and the lower 8 bits of the data latch 76 as a, b, c, d, and e by a select signal during a time period of 1/fs while the data latch holds the data, and sends the same to the interleaving circuit 70 at every 8 bits (1 symbol).

By conducting the division of the word symbol at a word unit and symbolizing the same over a plurality of channels as described above, it is possible to accommodate the quantization bit number 16 (FIG. 18, FIG. 15, and FIG. 16) and 20 by the same error correction encoder (l=8). Accordingly, in the device of this third embodiment, the same error correction encoder can be used corresponding to a case where the quantization bit number is changed, and thus the hardware is simplified.

A fourth embodiment of the present invention in a case where the quantization bit number Q=20 is shown in FIG. 20. In this fourth embodiment the upper 8 bits of the channel 1, the middle 8 bits of the channel 1, the upper 8 bits of the channel 2, the middle 8 bits of the channel 2, and the sum of the lower 4 bits of the channel 1 and the lower 4 bits of the channel 2 are made a first symbol, a second symbol, a third symbol, a fourth symbol, and a fifth symbol, respectively. The data division circuit 69 in this case can be realized by the circuit of FIG. 21. The circuit operation is the same as that of FIG. 17, and only the connection from the data latches 75 and 76 to the selector circuit 78 is different. The upper 8 bits of the data latch 75, the middle 8 bits of the data latch 75, the upper 8 bits of the data latch 76, the middle 8 bits of the data latch 76, and the sum of the lower 4 bits of the data latch 75 and the lower 4 bits of the data latch 76 are selected as a, b, c, d, and e by a select signal, respectively, and they are sent to the interleaving circuit 11 by 1 symbol. Also in this embodiment the same error correction encoder can be used corresponding to the quantization bit numbers 16 and 20.

As is evident from the foregoing description, according to the third and fourth embodiments, the word division is conducted at a word unit in conducting the error correction encoding, and the encoding is conducted by dividing 1 word into m for a quantization bit number Q which complies with Q.times.N/l=m, whereby the same encoder and decoder can be used for different quantization bit numbers, thereby simplifying the hardware of the PCM recording and reproducing apparatus.

In the above-illustrated third and fourth embodiments the examples in which Q=16, 20, N=3, l=8 are described, but there of course exists various kinds of combinations of the quantization bit number, channel number, and 1 symbol bit number other than above on a condition that the formula (1) is complied with.

In the above-illustrated third and fourth embodiment only the encoder circuit is described, but also in the decoder circuit the same error correction decoder can be used corresponding to different quantization bit numbers similarly as above because a procedure reverse to the encoding procedure is conducted in the decoder circuit.