US 4,879,690 AGrant
Static Random Access Memory With Reduced Soft Error Rate
Issue Date:1989-11-07
•22 Claims
•9 Drawing Sheets
Abstract
A storage node in each of memory cells in a static RAM is connected to a bit line through an accessing MOSFET. The accessing MOSFET has its gate connected to a word line. A word line driver comprising a level shifting N channel MOSFET and a CMOS inverter is connected to the word line. At the time of selecting the word line, a potential which is lower, by a threshold voltage of the MOSFET, than a power-supply potential is applied to the word line. Thus, a sub-threshold current flowing in the MOSFET connected between the storage node for storing data at a high level and the bit line to which data of a high level is read out becomes substantially small, so that a potential of the storage node for storing data of a high level is not lowered.
Metadata
Assignee
- Mitsubishi Denki Kabushiki Kaisha
Inventors
- Kenji Anami
- Katsuki Ichinose
- Tomohisa Wada
Application Information
Application Number:US 2310635
Filing Date:1988-08-11
Priority Date:1987-09-07
Art Unit:233
Classifications
IPC:
G11C 1300
Field of Search:
36537153;182;189;190;201;203;202;20621;38;51
Patent Drawings (9 sheets)
Description
Background of the Invention
1. Field of the Invention
The present invention relates to static random access memories and more particularly, to static random access memories having a reduced soft error rate.
2. Description of the Prior Art
FIG. 1 is a block diagram showing an example of structure of a static random access memory (referred to as a static RAM hereinafter).
In FIG. 1, a plurality of word lines and a plurality of bit line pairs are arranged intersecting with each other in a memory cell array 50, memory cells being provided at intersections of the word lines and the bit line pairs, respectively. The word lines in the memory cell array 50 are connected to an X decoder 51. X address signals are applied to the X decoder 51 through an X address buffer 52. In addition, the bit line pairs in the memory cell array 50 are connected to a Y decoder 54 through a transfer gate 53. Y address signals are applied to the Y decoder 54 through a Y address buffer 55.
One of the word lines in the memory cell array 50 is selected by the X address decoder 51 in response to the X address signals and one set of the bit line pairs in the memory cell array 50 is selected by the Y address decoder 54 in response to the Y address signals, so that a memory cell provided at an intersection of the selected word line and the selected bit line pair is selected. Data is written into the selected memory cell or data stored in the memory cell is read out. Writing or reading of data is selected by a read/write control signal R/W applied to a read/write control circuit 56. At the time of writing data, input data D.sub.in is inputted to the selected memory cell through a data input buffer 57. In addition, at the time of reading out data, data stored in the selected memory cell is extracted to the exterior through a sense amplifier 58 and a data output buffer 59.
FIG. 2 is a circuit diagram of a memory cell portion in a conventional static RAM which is disclosed in, for example, Japanese Patent Publication No. 18997/1987.
In FIG. 2, a plurality of memory cells 1a to 1n are connected between bit lines 14 and 15. Each of the memory cells 1a to 1n comprises two inverter constituting MOS field effect transistors (referred to as MOSFETs hereinafter) 2 and 3 of enhancement type, two load resistances 4 and 5 each having a high resistance value and two accessing MOSFETs 6 and 7. The MOSFETs 2 and 3 have respective their drains D connected to respective one ends of the resistances 4 and 5 at nodes 8 and 9, respectively, the respective other ends of the resistances 4 and 5 being connected to power supply terminals 10 and 11, respectively. In addition, each of the MOSFETs 2 and 3 has its source S connected to a ground terminal. Furthermore, the MOSFET 2 has its gate G connected to the node 9 and the MOSFET 3 has its gate G connected to the node 8. Information is stored in a parasitic capacitance 12 which exists between the node 8 and the ground terminal and a parasitic capacitance 13 which exists between the node 9 and the ground terminal. The node 8 is connected to the bit line 14 through the accessing MOSFET 6. The MOSFET 6 has its gate connected to a corresponding one of word lines 16a to 16n. The node 9 is connected to the bit line 15 through the accessing MOSFET 7. The MOSFET 7 has its gate connected to a corresponding one of the word lines 16a to 16n.
The bit lines 14 and 15 are connected to I/O lines 19 and 20 through MOSFETs 17 and 18, respectively. Each of the MOSFETs 17 and 18 has its gate connected to an input terminal 21 receiving a column selecting signal by a Y decoder. In addition, the bit lines 14 and 15 are connected to power supply terminals 24 and 25 through bit line load constituting MOSFETs 22 and 23 which have a diode-connection, respectively. The MOSFETs 22 and 23 precharge the bit lines 14 and 15, respectively. A power-supply voltage V.sub.CC is applied to the power supply terminals 10, 11, 24 and 25.
A threshold voltage V.sub.THD of the inverter constituting MOSFETs 2 and 3 is set to be higher than a threshold voltage V.sub.TH of the other MOSFETs in the memory circuit. In addition, assuming that an on-resistance at the operating time of the MOSFETs 2 and 3 is represented by R.sub.DON, an on-resistance at the operating time of the MOSFETs 6 and 7 is represented by R.sub.TON and an on-resistance at the operating time of the MOSFETs 22 and 23 is represented by R.sub.LON, the threshold voltage V.sub.THD of the inverter constituting MOSFETs 2 and 3 is set as follows: ##EQU1## Where V.sub.RL represents a potential of the node 8 or 9 which stores data at a low level at the time of selecting the word lines.
Operation of the memory cell is now described.
It is assumed that data stored in the memory cell 1a is read out with the potential of the node 8 in the memory cell 1a being at a low level and the potential of the node 9 therein being at a high level. In this case, a potential on the word line 16a changes from 0V or a potential close to 0V at the time of non-selecting a word line to the power-supply potential V.sub.CC or a potential close to V.sub.CC at the time of selecting a word line. As a result, a current flows from the power supply terminal 24 to the ground terminal through the bit line load constituting MOSFET 22, the accessing MOSFET 6 and the inverter constituting MOSFET 2. However, since the inverter constituting MOSFET 3 is turned off, no current flows from the power supply terminal 25 to the ground terminal through the bit line load constituting MOSFET 23, the accessing MOSFET 7 and the inverter constituting MOSFET 3. Thus, a potential on the bit line 14 is set to a potential determined by the ratio of the on-resistances of the MOSFET 22, the MOSFET 6 and the MOSFET 2, while a potential on the bit line 15 is set to a potential which is lower, by the threshold voltage V.sub.TH of the bit line load constituting MOSFET 23, than the power-supply potential V.sub.CC.
In the above described conventional static RAM, since at the time of reading out data, the potential on the word line 16a is the power-supply potential V.sub.CC and the potential on the bit line 15 is lower, by the threshold voltage V.sub.TH of the MOSFET 23, than the power-supply potential V.sub.CC, a voltage between a gate and a source (which is connected to a bit line) of the accessing MOSFET 7 almost equals the absolute value of the threshold voltage V.sub.TH of the accessing MOSFET 7. Therefore, a sub-threshold current I.sub.subA flows in the accessing MOSFET 7, so that charges flow to the bit line 15 from the node 9 having the power-supply potential V.sub.CC stored therein. Thus, in the conventional static RAM, the potential at the time of storing data of a high level is lowered, so that soft errors are liable to occur.
Description is now made on soft errors in the RAM. Soft errors mean that information stored in a memory cell is lost by disturbance such as noise so that information "1" is inverted into information "0" or information "0" is inverted into information "1". Namely, soft errors mean that information is only inverted. More specifically, soft errors do not mean that structure of the memory cell is destroyed physically but that the state of a flip-flop in the memory cell only changes. Thus, when correct information is written to the memory cell, the correct information is stored therein. On the other hand, hard errors mean that a memory cell is destroyed physically so that information can not be stored therein any longer.
The problem to be considered in the present invention is soft errors generated by alpha particles, of soft errors. FIG. 3 is a cross sectional view showing a single storage node of the memory cell. In FIG. 3, upon incidence of alpha particles on an n.sup.+ layer 101 serving as a storage node of the memory cell or the vicinity thereof from exterior, electron and hole pairs are generated in a semiconductor substrate (P-well 102 herein) by energy thereof. Electrons, of the electron and hole pairs are attracted to the n.sup.+ layer 101 serving as a storage node. As a result, a potential of the storage node is lowered. When information at a high level is stored in the storage node, the information stored therein is inverted if the potential thereof is too lowered. Consequently, soft errors occur. Thus, when a potential of a node which stores information at a high level is lowered to some degree, soft errors are liable to occur.
Various research papers concerning soft errors in a static RAM have been presented. For example, an article in Japanese Journal of Applied Physics, Vol. 22, Supplement 22-1, 1983, pp. 69-73 shows that a soft error rate of an SRAM depends on a selected time interval of a memory cell. An article in IEEE Journal of Solid-State Circuits, Vol. SC-22, No. 3, June 1987, pp. 430-436 shows that since a memory cell in an SRAM requires several 10 .mu.s until a potential of a node of a high level is recovered after data is read out from the memory cell, a soft error rate is increased if the memory cell is operated in a cycle of several 10 .mu.s or less.
Summary of the Invention
An object of the present invention is to provide a static RAM which is immune to soft errors.
Another object of the present invention is to prevent the decrease in potential of a node which stores data at a high level in a static RAM.
Still another object of the present invention is to reduce a soft error rate in a static RAM without increasing an areas of a memory cell.
Yet still another object of the present invention is to reduce a soft error rate in a static RAM without increasing complexing.
In order to attain the above described objects, the static RAM according to the present invention comprises a plurality of word lines, a plurality of pairs of bit lines arranged intersecting with the plurality of word lines, a plurality of memory cells each connected to an intersection of each of the word lines and each of the bit line pairs, a potential source for generating a power-supply potential and a ground potential, and word line selecting means for selecting a single word line of the plurality of word lines and applying a predetermined potential to the word line. Each of the memory cells comprising a first load element, a second load element, a first information storing transistor element, a second information storing transistor element, a third accessing transistor element, and a fourth accessing transistor element. The first load element has one terminal coupled to the power-supply potential and another terminal in which information of a low or high level is stored. The second load element has one terminal coupled to the power-supply potential and another terminal in which information of a high or low level is stored. The first information storing transistor element is connected between the other terminal of the first load element and the ground potential and has a control terminal connected to the other terminal of the second load element. The second information storing transistor element is connected between the other terminal of the second load element and the ground potential and has a control terminal connected to the other terminal of the first load element. The third accessing transistor element is connected between one of each of the bit line pairs and the other terminal of the first load element and has a control terminal connected to the word line. The fourth accessing transistor element is connected between the other of each of the bit line pairs and the other terminal of the second load element and has a control terminal connected to the word line. The third and fourth accessing transistor elements have a first threshold voltage. The difference between the predetermined potential applied by the word line selecting means and a potential on the bit line to which information at a high level is read out at the time of selecting the word line being smaller than a first threshold voltage of the third or fourth transistor element.
In the static RAM according to the present invention, since the difference between the potential on the word line and the potential on the bit line to which information of a high level is read out becomes smaller than the threshold voltage of the third or fourth transistor element, a sub-threshold current flowing in the third or fourth transistor element becomes substantially small.
In accordance with another aspect of the present invention, the first transistor element and the second transistor element have a second threshold voltage which is larger than a voltage between a potential of the other terminal of the first or second load element having information at a low level stored therein at the time of selecting the word line and the ground potential. Therefore, at the time of selecting the word line, a sub-threshold current flowing in the first or second transistor element having information at a high level stored therein becomes substantially small. Thus, the decrease in potential of a node having information of a high level stored therein is prevented, so that a static RAM which is immune to soft errors is obtained with high reliability.
These objects and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
Brief Description of the Drawings
FIG. 1 is a block diagram showing entire structure of a static RAM;
FIG. 2 is a circuit diagram showing a memory cell portion of a conventional static RAM;
FIG. 3 is a diagram for explaining a mechanism of soft errors;
FIG. 4 is a circuit diagram showing a memory cell portion of a static RAM according to an embodiment of the present invention;
FIG. 5 is a circuit diagram showing a memory cell portion of a static RAM according to another embodiment of the present invention;
FIG. 6 is a circuit diagram showing a memory cell portion of a static RAM according to still another embodiment of the present invention; and
FIG. 7 is a waveform diagram showing operation of the static RAM shown in FIG. 6;
FIG. 8 is a circuit diagram for explaining the decrease in potential of a node in a memory cell, by a sub-threshold current;
FIG. 9 comprised of parts (a) and (b) is a timing chart showing the decrease in potential in a memory cell, by a sub-threshold current;
FIG. 10 is a diagram showing the relation between the sub-threshold current and potential of the node; and
FIG. 11 is a diagram showing the concept of the relation between the ratio I.sub.L /I.sub.sub of a load current to the sub-threshold current and a soft error rate.
Description of the Preferred Embodiments
FIG. 4 is a circuit diagram showing a memory cell portion of a static RAM according to an embodiment of the present invention.
In FIG. 4, a plurality of memory cells 1a to 1n are connected between a pair of bit lines 14 and 15. Each of the memory cells 1a to 1n comprises two inverter constituting MOSFETs 2 and 3 of an enhancement type, two load resistances 4 and 5 each having a high resistance value and two accessing MOSFETs 6 and 7. The MOSFETs 2 and 3 have respective drains D connected to respective one ends of the resistances 4 and 5 at nodes 8 and 9, respectively, respective other ends of the resistances 4 and 5 being connected to power supply terminals 10 and 11. In addition, each of the MOSFETs 2 and 3 has its source S connected to a ground terminal. Furthermore, the MOSFET 2 has its gate G connected to the node 9, and the MOSFET 3 has its gate G connected to the node 8. Information is stored in a parasitic capacitance 12 which exists between the node 8 and the ground terminal and a parasitic capacitance 13 which exists between the node 9 and the ground terminal. The node 8 is connected to the bit line 14 through the accessing MOSFET 6. The MOSFET 6 has its gate connected to a corresponding one of the word lines 16a to 16n. The node 9 is connected to the bit line 15 through the accessing MOSFET 7. The MOSFET 7 has its gate connected to a corresponding one of the word lines 16a to 16n.
The bit lines 14 and 15 are connected to I/O lines 19 and 20 through MOSFETs 17 and 18, respectively. Each of the MOSFETs 17 and 18 has its gate connected to an input terminal 21 receiving a column selecting signal. In addition, the bit lines 14 and 15 are connected to power supply terminals 24 and 25 through bit line load constituting MOSFETs 22 and 23 which have a diode-connection, respectively. The MOSFETs 22 and 23 precharge the bit lines 14 and 15, respectively. A power-supply voltage V.sub.CC is applied to the power supply terminals 10, 11, 24 and 25.
A threshold voltage V.sub.THD of the inverter constituting MOSFETs 2 and 3 is set to be higher than a threshold voltage V.sub.TH of the other MOSFETs in the memory circuit. In addition, assuming that an on-resistance at the operating time of the MOSFETs 2 and 3 is represented by R.sub.DON, an on-resistance at the operating time of the MOSFETs 6 and 7 is represented by R.sub.TON and an on-resistance at the operating time of the MOSFETs 22 and 23 is represented by R.sub.LON, the threshold voltage V.sub.THD of the inverter constituting MOSFETs 2 and 3 is set as follows: ##EQU2## where V.sub.RL represents a potential of the node 8 or 9 which stores data at a low level at the time of selecting the word lines.
Word line drivers 30a to 30n are connected to the word lines 16a to 16n, respectively. Each of the word line drivers 30a to 30n comprises a level shifting N channel MOSFET 31, a P channel MOSFET 32 and an N channel MOSFET 33. The MOSFET 31 has its drain and its gate connected to a power supply terminal 34 receiving the power-supply potential V.sub.CC, and a source connected to a source of the MOSFET 32. The MOSFET 32 has a drain connected to a drain of the MOSFET 33. The MOSFET 33 has its source connected to the ground terminal. Each of the MOSFETs 32 and 33 has its gate receiving a word line selecting signal. A node of the drains of the MOSFETs 32 and 33 is connected to a corresponding one of the word lines 16a to 16n. The MOSFETs 32 and 33 constitute a CMOS inverter.
Operation of the memory cell is now described.
It is assumed that data stored in the memory cell 1a is read out when the node 8 in the memory cell 1a stores data at a low level and the node 9 stores data at a high level. When the word line selecting signal changes from an "H" level to an "L" level, a potential on the word line 16a becomes lower, by the threshold voltage V.sub.THW of the MOSFET 31, than the power-supply potential V.sub.CC. As a result, the accessing MOSFET 6 is turned on, so that a current flows from the power supply terminal 24 to the ground terminal through the bit line load constituting MOSFET 22, the accessing MOSFET 6 and the inverter constituting MOSFET 2. At that time, a potential of the node 8 is V.sub.RL as shown in the equation (2). Since the threshold voltage V.sub.THD of the MOSFET 3 satisfies the relation V.sub.RL .ltoreq.V.sub.THD the MOSFET 3 is not rendered conductive. As a result, no current flows from the power supply terminal 25 to the ground terminal through the bit line load constituting MOSFET 23, the accessing MOSFET 7 and the inverter constituting MOSFET 3, and a potential of the node 9 is not lowered from the power-supply potential V.sub.CC.
Thus, a potential on the bit line 14 is set to a potential determined by the ratio of the on-resistances of the MOSFET 22, the MOSFET 6 and the MOSFET 2. A potential on the bit line 15 is set to a potential V.sub.BH which is lower, by the threshold voltage V.sub.TH of the bit line load constituting MOSFET 23, than the power-supply potential V.sub.CC.
Furthermore, since the potential V.sub.WH on the word line 16a equals V.sub.CC -V.sub.THW and the potential V.sub.BH on the bit line 15 equals V.sub.CC -V.sub.TH, a voltage between a gate and a source of the accessing MOSFET 7 becomes substantially small such as .vertline.V.sub.THW -V.sub.TH .vertline.. Therefore, the sum I.sub.sub of a sub-threshold current I.sub.subA flowing in the accessing MOSFET 7 and a sub-threshold current I.sub.subB flowing in the inverter constituting MOSFET 3 is sufficiently smaller than current ability I.sub.L supplied by the memory cell (I.sub.sub <<I.sub.L). Thus, the potential of the node 9 is not lowered by the sub-threshold current I.sub.sub.
On the other hand, it is assumed that data stored in the memory cell 1a is read out when the node 9 in the memory cell 1a stores data of a low level and the node 8 therein stores data of a high level. In this case, in the same manner, the potential on the bit line 14 is set to be lower, by the threshold voltage V.sub.TH of the bit line load constituting MOSFET 22, than the power-supply potential V.sub.CC. In addition, the potential on the bit line 15 is set to a potential determined by the ratio of the on-resistances of the MOSFET 23, the MOSFET 7 and the MOSFET 3.
In this case, since V.sub.THD which is a threshold value of the MOSFET 2 satisfies the relation V.sub.RL .ltoreq.V.sub.THD the MOSFET 2 is not rendered conductive. In addition, since the potential difference between a gate and a source of the accessing MOSFET 6 becomes substantially small, the sum I.sub.sub of the sub-threshold current I.sub.subA flowing in the MOSFET 6 and a sub-threshold current I.sub.subB flowing in the MOSFET 2 becomes sufficiently small. Thus, the potential of the node 8 is not lowered.
Thus, at the time of reading out data, since a potential of the storage node having data of a high level stored therein is not lowered from the power-supply potential V.sub.CC, the static RAM is immune to soft errors.
Meanwhile, a threshold voltage of the MOSFET 31 is set by ion implantation, selection of the concentration of a substrate or the like in consideration of the value of a load resistance in a memory cell, so that the potential level at the time of selecting the word lines 16a to 16n can be freely set.
Although in the embodiment shown in FIG. 4, the level shifting MOSFET 31 is provided for every of the word line drivers 30a to 30n, a common level shifting MOSFET may be provided outside the word line drivers 30a to 30n.
Furthermore, although in the embodiment shown in FIG. 4, the MOSFET 31 which has a diode-connection is used for level shifting, a pn diode may be used, to obtain the same effect.
Additionally, although in the embodiment shown in FIG. 4, the gate of the level shifting MOSFET 31 is connected to the power-supply potential V.sub.CC, the gate thereof may be connected to the other potentials which are set to a potential satisfying the relation I.sub.sub <<I.sub.L at the same time of selecting a word line.
FIG. 5 is a circuit diagram showing a memory cell portion of a static RAM according to another embodiment of the present invention.
In FIG. 5, structure of memory cells 1a to 1n is the same as that of the memory cells 1a to 1n shown in FIG. 4, while structure of word line drivers 40a to 40n is different from that shown in FIG. 4.
Each of the word line drivers 40a to 40n comprises an N channel MOSFET 41, an N channel MOSFET 42 and an inverter 43. The MOSFET 41 has its drain connected to a power supply terminal 44 receiving a power-supply potential V.sub.CC, and a source connected to a drain of the MOSFET 42. The MOSFET 42 has its source connected to a ground terminal. The MOSFETs 41 and 42 constitute a CMOS inverter. The MOSFET 42 has its gate receiving a word line selecting signal. The MOSFET 41 has its gate receiving a signal obtained by inverting the word line selecting signal by the inverter 43. A node of the source of the MOSFET 41 and the drain of the MOSFET 42 is connected to a corresponding one of word lines 16a to 16n.
According to the present embodiment, a potential at the time of selecting a word line is lower, by a threshold voltage of the MOSFET 41, than a potential V.sub.G of a gate of the MOSFET 41. More specifically, a potential of a high level on the word line can be freely set by selecting a threshold voltage of the inverter 43.
Thus, when the potential of a high level on the word line is selected such that the difference between a potential on a bit line to which data at a high level is read out at the time of reading out data and a potential on the word line is sufficiently small, a sub-threshold current flowing in an accessing MOSFET becomes sufficiently small. As a result, in the present embodiment, the static RAM is immune to soft errors, as in the embodiment shown in FIG. 4.
Additionally, means for reducing the potential at the time of selecting a word line is not limited to the means in the above described embodiment. Another means may be used in which the condition I.sub.sub <<I.sub.L is satisfied.
FIG. 6 is a circuit diagram showing a memory cell portion of a static RAM according to still another embodiment of the present invention.
Instead of reducing the potential at the time of selecting a word line as shown in FIGS. 4 and 5, in the present embodiment, MOSFETs 60 and 70 each having a high threshold voltage V.sub.THA are used as an accessing transistor connected between a node 8 and a bit line 14 and between a node 9 and a bit line 15.
For example, when a threshold voltage V.sub.THB of bit line load constituting MOSFETs 22 and 23 is 1.5V, a threshold voltage V.sub.THA of the accessing MOSFETs 60 and 70 is set to 2 V. In this case, assuming that a power-supply voltage V.sub.CC is 5 V, a potential on the bit line to which data of a high level is read out is 5=1.5=3.5 V. Thus, a voltage between a gate and a source of each of the accessing MOSFETs 60 and 70 is 5-3.5+1.5 V, which is lower than the threshold voltage V.sub.THA (=2 V) of the accessing MOSFETs 60 and 70.
FIG. 7 illustrates a waveform of operation according to the present embodiment. Referring to FIG. 7, when an address input is applied, one of word lines 16a to 16n (for example, 16a) is selected in response to the address input, so that a potential on the selected word line 16a rises from 0 V to 5 V. Thus, data stored in the nodes 8 and 9 in the memory cell 1a connected to the word line 16a are read out to the bit lines 14 and 15, respectively. As a result, the potential difference occurs between the bit lines 14 and 15. The potential difference is amplified by a sense amplifier, so that a data output of 0V or 5V is obtained.
According to the present embodiment, since the threshold voltage V.sub.THA of the accessing MOSFETs 60 and 70 is larger than the difference between the potential on the bit line to which data of a high level is read out and the potential on the word line, the sum I.sub.sub of a sub-threshold current I.sub.subA flowing in the accessing MOSFETs 60 or 70 and a sub-threshold current I.sub.subB flowing in the inverter constituting MOSFET 2 or 3 becomes sufficiently smaller than current ability I.sub.L supplied by the memory cell (I.sub.sub <<I.sub.L). Thus, a potential of a node having high-level data stored therein is not decreased by the sub-threshold current I.sub.sub.
The threshold voltage of the accessing MOSFETs 60 and 70 can be freely set by ion implantation, selection of the concentration of a substrate, or the like in consideration of the value of a load resistance in the memory cell. If the threshold voltage of the accessing MOSFETs 60 and 70 is increased, the resistance value at the time of conduction of the MOSFETs 60 and 70 is increased, so that the access time may be increased. However, this can be avoided by increasing the channel width.
Additionally, instead of increasing the threshold voltage of the accessing transistors as shown in the above described embodiment, the threshold voltage of the bit line load constituting MOSFETs 22 and 23 may be decreased. In this case, since a potential on the bit line to which a high-level data is read out at the time of selecting a word line is increased, the difference between the potential on the word line and the potential on the bit line becomes smaller than the threshold voltage of the accessing transistors, so that a sub-threshold current flowing in the accessing transistors becomes substantially small. Means for increasing the potential on the bit line is not limited to the above described means. Another means may be used, to obtain the same effect. For example, if a bit line load comprises a resistance or a depletion transistor, the potential on the bit line is charged to be the power-supply potential. In addition, the threshold voltage of the accessing transistors may be set high separately from that of the inverter constituting transistor or set to be the same value as that of the inverter constituting transistor. The static RAM has the advantage of providing greater freedom in design if the threshold voltages are set to different values and of the reduced number of processes if the threshold voltages are set to the same value.
Description is now made on the relation between a sub-threshold current and the decrease in potential of a node using specific numerical values.
In FIG. 8, it is assumed that information of a high level is stored in a node N.sub.H and information of a low level is stored in a node N.sub.L. In addition, it is assumed that the resistance value of a load resistance R is 500 G.OMEGA. (5.times.10.sup.11 .OMEGA.) and a power-supply potential V.sub.CC is 5 V. When a potential on a word line WL is at a low level, MOSFETs Q.sub.A1 and Q.sub.A2 are completely off, so that sub-threshold currents I.sub.subA and I.sub.subB have substantially small values (I.sub.subA +I.sub.subB =10.sup.-13 A or less). Furthermore, a load current I.sub.L flowing in the load resistance R has the same value. Thus, a potential V.sub.NH of the node N.sub.H is as follows:
Namely, the potential V.sub.NH becomes a value substantially close to the power-supply potential V.sub.CC.
When the potential on the word line WL attains a high level, the sub-threshold current I.sub.sub (=I.sub.subA +I.sub.subB) flowing in the MOSFETs Q.sub.A1 and Q.sub.D1 is increased by several figures, in the case of the conventional example shown in FIG. 2. For example, the sub-threshold current I.sub.sub is approximately as follows:
Since the load current I.sub.L equals the sub-threshold current I.sub.sub, the potential V.sub.NH of the node N.sub.H attempts to be lowered by R.I.sub.L (=5.times.10.sup.11 .times.1.times.10.sup.-9). In this case, however, since a potential on a bit line BL is held at a potential which is lower, by a threshold voltage V.sub.TH of an MOSFET Q.sub.B, than the power-supply potential V.sub.CC, the potential V.sub.NH of the node N.sub.H equals the potential on the bit line BL. For example, when the threshold voltage V.sub.TH of the MOSFET Q.sub.B is 1.5 V, the potential V.sub.NH of the node N.sub.H is lowered to 5-1.5=3.5 V. When the potential on the word line WL attains a low level, the potential V.sub.NH is charged again by the load resistance R, to be restored to a potential almost close to V.sub.CC with a long time constant (approximately 10 ms). However, as shown in FIG. 9(a), when the word line WL is selected until the potential V.sub.NH of the node N.sub.H rises to the power-supply potential V.sub.CC, the soft error rate is increased.
Thus, in order to improve soft error immunity, it is necessary that the potential V.sub.NH of the node N.sub.H is not so lowered at the time of selecting the word line WL (at the time of a high level). In order to lower the potential V.sub.NH by approximately 0.1 V at that time of selecting the word line WL, the current I.sub.L must have the following value:
Thus, the sub-threshold current I.sub.sub (=I.sub.subA +I.sub.subB) must be made 2.times.10.sup.-13 A or less. Since the sub-threshold current I.sub.subA is decreased by approximately one figure when the threshold voltages of the MOSFETs Q.sub.A1 and Q.sub.A2 are raised by 0.1 V, the amount of the rise in the threshold voltages can be estimated. If I.sub.sub .perspectiveto.10.sup.-9 A, then I.sub.sub .perspectiveto.10.sup.-13 A when the threshold voltages of the MOSFETs Q.sub.A1 and Q.sub.A2 are raised by 0.4 V. As a result, the amount of the decrease in potential of the node N.sub.H becomes 0.1V at the time of selecting the word line WL, so that the soft error rate is improved by approximately one figure or more. FIG. 10 is a diagram showing the concept of the relation between the sub-threshold current I.sub.sub and the potential V.sub.NH of the node N.sub.H at the time of selecting the word line WL. This diagram shows that the potential V.sub.NH of the node N.sub.H is lowered as the sub-threshold current I.sub.sub increases.
Description is now made on the transient change of the sub-threshold current I.sub.sub and the load current I.sub.L at the time of selecting the word line WL. Let's consider the case in which the potential on the word line WL rises to a high level so that the potential of the node N.sub.H is lowered to 4.5 V. When the potential on the word line WL attains a high level, the sub-threshold current I.sub.sub first increases. As a result, the sub-threshold current I.sub.sub and the load current I.sub.L have the relation I.sub.sub >I.sub.L. Thus, the load current I.sub.L also increases, so that the potential V.sub.NH of the node N.sub.H is lowered with increasing the load current I.sub.L. When the potential V.sub.NH is lowered to 4.5 V, the sub-threshold current I.sub.sub and the load current I.sub.L become equal, so that the potential V.sub.NH is not lowered any more. More specifically, so long as the relation I.sub.sub >I.sub.L holds, the potential V.sub.NH of the node N.sub.H continues to be lowered.
Let's consider the case in which the potential V.sub.NH of the node N.sub.H is stabilized at 4.9 V when the potential on the word line WL rises to a high level. When the potential on the word line WL attains a high level, the sub-threshold current I.sub.sub first increases, so that the relation I.sub.sub >I.sub.L holds. Correspondingly, the load current I.sub.L increases, so that the potential V.sub.NH is lowered to 4.9 V. At this time point, if the relation I.sub.sub =I.sub.L holds, the potential V.sub.NH is now lowered any more. If the relation I.sub.sub <I.sub.L is satisfied when the potential V.sub.NH of the node N.sub.H becomes lower than 4.9 V for some reason, the load current I.sub.L is decreased to be equal to the sub-threshold current I.sub.sub. As a result, the potential V.sub.NH of the node N.sub.H is raised to 4.9 V. Thus, the potential V.sub.NH of the node N.sub.H is stabilized at 4.9 V.
As described in the foregoing, if the relation I.sub.sub >I.sub.L holds at the time of selecting a word line, the potential V.sub.NH of the node N.sub.H continues to be lowered. On the other hand, if the relation I.sub.sub <I.sub.L holds, the potential V.sub.NH of the node N.sub.H is not decreased any more. More specifically, it is assumed that the soft error rate is improved if the amount of the decrease in potential of the node N.sub.H at the time of selecting the word line is .DELTA.V or less. In this case, if the relation I.sub.sub <I.sub.L holds at the time point at which the potential V.sub.NH of the node N.sub.H is V.sub.CC -.DELTA.V, the potential V.sub.NH is now lower than V.sub.CC -.DELTA.V.
FIG. 11 is a diagram showing the relation between I.sub.L /I.sub.sub and the soft error rate at the time point at which the potential V.sub.NH of the node N.sub.H is V.sub.CC -.DELTA.V. As shown in FIG. 10, if the relation I.sub.L /I.sub.sub <1 holds, the potential V.sub.NH of the node N.sub.H becomes lower than V.sub.CC -.DELTA.V, so that the soft error rate is increased. On the other hand, if the relation I.sub.L /I.sub.sub >1 holds, the potential V.sub.NH of the node N.sub.H becomes higher than V.sub.CC -.DELTA.V, so that the soft error rate is decreased. Thus, if a potential at the time of selecting a word line, a potential on a bit line or a threshold voltage of an MOSFET is set in the above described embodiment such that the relation I.sub.L /I.sub.sub >holds at the time point at which the potential V.sub.NH of the node N.sub.H is lowered to V.sub.CC -.DELTA.V, the soft error rate can be significantly improved.
More specifically, the threshold voltages of the MOSFETs or the value of the load resistances are set such that not only the accessing MOSFET and the inverter constituting MOSFET connected to the node V.sub.NH are turned off in a usual sense, but also a potential of the node N.sub.H is stabilized at a potential sufficiently higher than a potential of a potential on the word line minus the threshold voltage of the accessing MOSFET, at the time of reading out data.
In order to stabilize a potential of the node N.sub.H as described above, one or some of the following adjustment .circle.1 .about. .circle.1 are made; .circle.1 an adjustment of the threshold voltage V.sub.THW of the MOSFET 31 in the word line driver; .circle.2 an adjustment of the threshold voltage of the inverter 43 in the word line driver; .circle.3 an adjustment of the threshold voltage V.sub.THA of the accessing MOSFETs 60 and 70; .circle.4 an adjustment of the threshold voltage V.sub.THD of the inverter constituting MOSFETs 2 and 3; .circle.5 an adjustment of the bit line load constituting MOSFETs 17 and 18; .circle.6 an adjustment of the value of the load resistances 4 and 5.
Additionally, decrease in potential of a node N.sub.H can be prevented by increasing the ratio of a gate width of the accessing MOSFETs 60 and 70 to a gate width of the inverter constituting MOSFETs 2 and 3 so that a potential of a node in which an information of a low level is stored is made to be decreased.
Meanwhile, in the case of adjusting the value R of the load resistances 4 and 5, the value R is set to be sufficiently smaller than (the power supply potential V.sub.CC - the threshold voltage V.sub.TH of the accessing MOSFET)/I.sub.leak : where I.sub.leak represents the sum of the leak currents which flow to the bit line and to the ground terminal from a node in which information of a high level is stored when the power supply potential V.sub.CC is applied to the node.
Furthermore, consider the case where the threshold voltage V.sub.TH of the bit line load constituting MOSFETs 17 and 18 is set to be smaller than the threshold voltage of the MOSFETs in the memory cell. In this case, if threshold voltages of MOSFETs in a peripheral circuit are set to more than two values, one threshold voltage of the MOSFETs may be set to the same threshold voltage as the bit line load constituting MOSFETs 17 and 18 and the other one threshold voltage of the MOSFETs may be set to the same threshold voltage as the MOSFETs in the memory cell. As a result, the number of processing can be reduced.
More specifically, in the case of setting the threshold voltage of the accessing MOSFETs and the inverter constituting MOSFETs to be higher, a junction capacitance is increased so that immunity to soft errors can be strengthened since P-type impurities are implanted under a channel of each MOSFET.
Additionally, in the case of setting a potential on the word line at the time of selecting to be lower than the supply potential V.sub.CC, amplitude of the potential on the word line becomes smaller. Thus, switching among the word lines can be made faster, so that access time can be shortened.
Although the present invention has been described and illustrate in detail, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the spirit and scope of the present invention being limited only by the terms of the appended claims.
Claims
What is claimed is:
1. A static random access memory having a reduced soft error rate, comprising: a plurality of word lines, a plurality of bit line pairs arranged intersecting with said plurality of word lines, a plurality of memory cells each connected to an intersection of each of said word lines and each of said bit line pairs, a potential source for generating a power-supply potential and a ground potential, and word line selecting means for selecting a single word line from among said plurality of word lines and applying a predetermined potential to the word line, each of said memory cells comprising a first load element having one terminal coupled to said power-supply potential and another terminal in which information of a low or high level is stored, a second load element having one terminal coupled to said power-supply potential and another terminal in which information of a high or low level is stored, a first information storing transistor element connected between the other terminal of said first load element and said ground potential and having a control terminal connected to the other terminal of said second load element, a second information storing transistor element connected between the other terminal of said second load element and said ground potential and having a control terminal connected to the other terminal of said first load element, a third accessing transistor element connected between one of each of said bit line pairs and the other terminal of said first load element and having a control terminal connected to a corresponding one of said word lines, and a fourth accessing transistor element connected between the other of each of said bit line pairs and the other terminal of said second load element and having a control terminal connected to a corresponding one of said word lines, said third and fourth accessing transistor elements having a first threshold voltage, and potential establishing means for setting the potential difference between a potential on the word line selected by said word line selecting means and a potential on a bit line to which information of a high level is read out at the time of selecting the word line to be smaller than said first threshold voltage of said third and fourth transistor elements so that soft errors are reduced.
2. A static random access memory having a reduced soft error rate, comprising: a plurality of word line, a plurality of bit line pairs arranged intersecting with said plurality of word lines, a plurality of memory cells each connected to an intersection of each of said word lines and each of said bit line pairs, a potential source for generating a power-supply potential and a ground potential, and word line selecting means for selecting a single word line from among said plurality of word lines and applying a predetermined potential to the word line, each of said memory cells comprising a first load element having one terminal coupled to said power-supply potential and another terminal in which information of a low or high level is stored, a second load element having one terminal coupled to said power-supply potential and another terminal in which information of a high or low level is stored, a first information storing transistor element connected between the other terminal of said first load element and said ground potential and having a control terminal connected to the other terminal of said second load element, a second information storing transistor element connected between the other terminal of said second load element and said ground potential and having a control terminal connected to the other terminal of said first load element, a third accessing transistor element connected between one of each of said bit line pairs and the other terminal of said first load element and having a control terminal connected to a corresponding one of said word lines, and a fourth accessing transistor element connected between the other of each of said bit line pairs and the other terminal of said second load element and having a control terminal connected to a corresponding one of said word lines, said third and fourth transistor elements having a first threshold voltage, said first transistor element and said second transistor element having a second threshold voltage larger than the potential difference between a potential of said other terminal of said first or second load element having said information of a low level stored therein at a time of selecting the word line and said ground potential, and potential establishing means for setting the potential difference between a potential on the word line selected by said word line selecting means and a potential on a bit line to which information of a high level is read out at the time of selecting the word line to be smaller than said first threshold voltage of said third and fourth transistor elements so that soft errors are reduced.
3. A static random access memory according to claim 1, wherein said potential establishing means comprises means for adjusting said predetermined potential on the selected word line.
4. A static random access memory according to claim 2, wherein said potential establishing means comprises means for adjusting said predetermined potential on the selected word line.
5. A static random access memory according to claim 4, wherein said word line selecting means comprises an address decoder responsive to an address signal for applying a selecting signal to one of said word lines, and said potential establishing means comprises potential setting means for setting a potential of said selecting signal to a predetermined potential.
6. A static random access memory according to claim 5, wherein said potential setting means comprises a CMOS inverter comprising an input terminal receiving said selecting signal, an output terminal connected to a corresponding one of said word lines, a first supply terminal, and a second supply terminal receiving said ground potential, and voltage dropping means connected between said power-supply potential and said first supply terminal in said CMOS inverter.
7. A static random access memory according to claim 6, wherein said CMOS inverter comprises a first P channel MOS field effect transistor comprising a gate terminal receiving said selecting signal, one conduction terminal, and another conduction terminal connected to a corresponding one of said word lines, and a second N channel MOS field effect transistor comprising a gate terminal receiving said selecting signal, one conduction terminal receiving said ground potential, and another conduction terminal connected to a corresponding one of said word lines, said voltage dropping means comprises a third N channel MOS field effect transistor comprising a gate terminal connected to said power-supply potential, one conduction terminal connected to said one conduction terminal of said first MOS field effect transistor, and another conduction terminal connected to said power-supply potential.
8. A static random access memory according to claim 6, wherein said potential setting means comprises a first MOS field effect element of a first conductivity channel type comprising a gate terminal receiving said selecting signal, one conduction terminal receiving said ground potential, and another conduction terminal connected to a corresponding one of said word lines, inverter means comprising an input terminal receiving said selecting signal and an output terminal responsive to said selecting signal for outputting a predetermined potential lower than said power-supply potential, and a second MOS field effect element of the first conductivity channel type comprising a gate terminal connected to the output terminal of said inverter means, one conduction terminal connected to a corresponding one of said word lines, and another conduction terminal receiving said power-supply potential.
9. A static random access memory according to claim 1, wherein said potential establishing means comprises means for adjusting said first threshold voltage of said third and fourth transistor elements.
10. A static random access memory according to claim 2, wherein said potential establishing means comprises means for adjusting said first threshold voltage of said third and fourth transistor elements.
11. A static random access memory according to claim 10, which further comprises bit line load constituting elements each connected between each of said bit lines and said power-supply potential and having a third threshold voltage, said first threshold voltage of said third and fourth transistor elements being larger than said third threshold voltage of said bit line load constituting elements.
12. A static random access memory according to claim 1, wherein said first, second, third and fourth transistor elements comprise an MOS field effect transistor.
13. A static random access memory according to claim 2, wherein said first, second, third and fourth transistor elements comprise an MOS field effect transistor.
14. A static random access memory according to claim 11, wherein said bit line load constituting elements comprise an MOS field effect element.
15. A static random access memory according to claim 14, wherein said MOS field effect element comprises an MOS field effect transistor.
16. A static random access memory according to claim 1, wherein a load current I.sub.L flowing in said first or second load element and the sum I.sub.sub of a sub-threshold current flowing in said first or second transistor element connected to the load element and a sub-threshold current flowing in said third or fourth transistor element connected to the load element satisfy the relation I.sub.L >I.sub.sub when a potential of said other terminal of said first or second load element in which said information of a high level is stored is a predetermined potential having a reduced soft error rate in the memory cell connected to the selected word line at the time of selecting said word lines.
17. A static random access memory according to claim 2, wherein a load current I.sub.L flowing in said first or second load element and the sum I.sub.sub of a sub-threshold current flowing in said first or second transistor element connected to the load element and a sub-threshold current flowing in said third or fourth transistor element connected to the load element satisfy the relation I.sub.L >I.sub.sub when a potential of said other terminal of said first or second load element in which said information of a high level is stored is a predetermined potential having a reduced soft error rate in the memory cell connected to the selected word line at the time of selecting said word lines.
18. A static random access memory according to claim 1, wherein said potential establishing means sets the potential difference between a potential on the selected word line and a potential on a bit line to which information of a high level is read out such that a potential of said another terminal in which information of a high level is stored is stabilized at a potential higher than a potential which is lower than the potential on the selected word line by said first threshold voltage of said third and fourth accessing transistor elements.
19. A static random access memory according to claim 2, wherein said second threshold voltage is set such that a potential of said another terminal in which information of a high level is stored is stabilized at a potential higher than a potential which is lower than the potential on the selected word line by said first threshold voltage of said third and fourth accessing transistor elements.
20. A static random access memory according to claim 5, wherein said potential setting means sets the potential of said selecting signal such that a potential of said another terminal in which information of a high level is stored is stabilized at a potential higher than a potential which is lower than the potential on the selected word line by said first threshold voltage of said third and fourth accessing transistor elements.
21. A static random access memory according to claim 10, wherein said first threshold voltage of said third and fourth transistor elements is set such that a potential of said another terminal in which information of a high level is stored is stabilized at a potential higher than a potential which is lower than the potential on the selected word line by said first threshold voltage of said third and fourth accessing transistor elements.
22. A static random access memory according to claim 1, wherein said first and second load elements have resistance value which is set such that a potential of said another terminal in which information of a high level is stored is stabilized at a potential higher than a potential which is lower than the potential on the selected word line by said first threshold voltage of said third and fourth accessing transistor elements.
Patent Citations (2)
| Patent | Date | Inventor | Cited By |
|---|---|---|---|
| US4811294 | 1989-03-01 | Kobayashi et al. | |
| JPX18997 | 1987-04-01 |
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