Semiconductor Component

The present invention relates to a high voltage transistor.

It is known from an article by T. Matsushita, et al, "Highly Reliable High-Voltage Transistors by Use of the SIPOS Process" the "IEEE Transactions on Electron Devices", Volume Ed-23, No. 8, August 1976, pages 826-830, to apply to the semiconductor surface of a high-voltage transistor a so-called SIPOS (semi-insulating polycrystalline silicon) layer consisting of polycrystalline silicon which is doped with oxygen or with nitrogen.

Glass passivated high-voltage transistors without SIPOS covering have the disadvantage that in the event of thermal and/or electrical load, U.sub.(BR)CBO, I.sub.CES and I.sub.B drifts may occur.

The object of the invention is to provide a semiconductor component, in particular, a high-voltage transistor, wherein this disadvantage does not occur, and wherein reverse voltage and I.sub.B drifts are at least minimized.

The above object is basically achieved in that in a semiconductor component with an oxygen doped or nitrogen doped silicon layer on its surface, a glass layer is provided, in accordance with the invention, between the doped silicon layer and the semiconductor surface. The silicon layer is preferably polycrystalline and the glass layer preferably consists of a lead-boron-aluminosilicate glass. Moreover, in a high voltage semiconductor transistor, the doped silicon layer is connected at one of its ends to the bsse electrode and at its other end to the collector electrode.

The invention will now be below in greater detail, by way of examples, with reference to the drawing, in which the Figure shows a high-voltage transistor.

The high-voltage transistor illustrated in the FIGURE has a collector zone comprised of a low-resistance substrate 1 of the first conduction type and a higher-resistance semiconductor layer 2 of the same conduction type. In the embodiment, the semiconductor substrate 1 and the higher-resistance epitaxial or zone-pulled, single-crystal layer 2 have, for example, the n-conduction type. Arranged above the higher-resistance semiconductor layer 2 is the base zone 3 which is produced, for example, by diffusion into the epitaxial layer 2 or by epitaxy. The conduction type of the base zone is the opposite of the conduction type of the collector zone. In the embodiment, the base zone 3 has the p-conduction type. The pn-junction 4 formed by the semiconductor zone 2 and the base zone 3 extends over the entire cross-section of the semiconductor member and thus to the lateral surface of the semiconductor member.

The emitter zone 5 is located in the base zone 3. The emitter zone 5 is produced, for example, by prediffusion and/or ion implantation with subsequent diffusion. A diffusion mask is used in the production of the emitter zone by diffusion. To produce the diffusion mask, the SiO.sub.2 i.e., quartz-glass, layer 6 is produced on the semiconductor surface, and this layer is provided with an emitter diffusion window through which the emitter zone 5 is diffused into the base zone 3. The SiO.sub.2 layer is produced, for example, by thermal oxidation.

During or after the emitter diffusion, the semiconductor surface is oxidized again, in the course of which the emitter diffusion window is closed and the existing SiO.sub.2 layer is reinforced. During this oxidation, the SiO.sub.2 or quartz-glass layer 7 is produced. A polycrystalline silicon layer 8 which is doped with oxygen or with nitrogen is applied to the SiO.sub.2 layer 7. The doped polycrystalline silicon layer 8 is produced, for example, by deposition in an oven of 600.degree.-650.degree. C. by supplying laughing gas (N.sub.2 O) and silane. The polycrystalline silicon layer 8 has the advantage that it makes the glass-silicon-boundary located thereunder more stabile and protects it against environmental influences.

After layers 7 and 8 have been produced, contacting holes are made in these two layers and the thereby exposed semiconductor zones are provided with electrodes. This results in base electrode 9 and emitter electrode 10. The collector zone is contacted on the semiconductor member side located opposite to the emitter zone.

As can be seen from the FIGURE, a portion of the upper surface of the semiconductor body or member adjacent the base zone 2 is recessed and the edge of the collector-base pnjunction 4 extends to the upper surface within the recess. This recess is covered with a passivation glass layer 12 which in turn is covered with the oxygen or nitrogen doped polycrystalline silicon layer 8. Preferably, as shown, the glass layer 12 is not a quartz-glass layer, but rather consists of a commercially available passivation glass, preferably a lead-boron-alumosilicate glass.

As is apparent from the FIGURE, the doped silicon layer 8 is electrically connected to both the base electrode 9 and the collector electrode 11. If the doped silicon layer 8 is of weak conductivity, the potential difference between the base electrode and the collector electrode prevents ionic charging of the surface and, consequently, unstable behavior of the collector base diode and also the emitter base diode of the transistor. The SIPOS layer 8 of weak conductivity also prevents charge accumulations in the isolating layer if the layer 8 is connected via electrodes to the collector and the base of the transistor.