Anti-Parallel Capacitor

The invention relates in general to an improved capacitor for use in integrated circuits and in particular to an improved thin-film capacitor with an extremely low voltage coefficient which is desirable in integrated circuit design.

There are two basic groups of capacitor structures available for use in integrated circuit design: junction and thin-film capacitors. This invention is concerned with the thin-film capacitor which is a direct miniaturization of the conventional parallel-plate capacitor.

The thin-film capacitor is composed of two conductive layers separated by a dielectric layer. Thin-film capacitors may be constructed using one of two processes: (a) MOS process using a metal-oxide semiconductor structure; or (b) using a thin-dielectric film between two conductive metal layers. The MOS structure is the most common thin-film capacitor in monolithic circuits because it is readily compatible with the conventional processing technology and does not require multiple metalization layers and is the process by which the capacitor is used in the present invention or fabricated. The capacitance output per unit area of a thin-film capacitor is equal to the ratio of the permittivity (.epsilon..sub.x) to the thickness T.sub.x of a dielectric layer. An MOS capacitor has either silicon dioxide (SiO.sub.2) or silicon nitride (Si.sub.3 N.sub.4) which can be used as the dielectric layer. Although silicon dioxide is more readily available, silicon nitride is preferred whenever the extra processing steps can be justified, since it also has a high dielectric constant.

However, for a capacito to be viable in any environment, particularly the integrated circuit environment, it must have a voltage coefficient in the range of .+-.20 ppm across the voltage range of .+-.20 V with the reference capacitance being evaluated at 0 V with a dc bias. The voltage cofficient of a capacitor is the amount of change of capacitance for a given change in voltage. It is desirable that the voltage coefficient be constant at all times and be as close to 0 as possible; however, a coefficient in the range of .+-.20 ppm is a remarkable improvement over what was discovered to be the variable voltage coefficient for a standard poly-metal thin-film capacitor of the prior art.

It will be subsequently pointed out the voltage coefficient of the prior art standard poly-metal capacitors varied over a range of .+-.350 ppm when biased with a voltage over a range of .+-.20 V. This wide range of variability of the voltage coefficient is undesirable and unacceptable in the fabrication of integrated circuits.

In view of the current state of the MOS thin-film capacitor art problems still exist in trying to decrease the voltage coefficient of a capacitor and maintain it at a constant low voltage coefficient. It is evident that there is a need in the industry for a new and improved MOS thin-film capacitor which has a constant low voltage coefficient and which is in a range so close to zero that the effect of any variation in the voltage coefficient, if any, is negligible. Accordingly, the present invention comprises a new and improved thin-film capacitor which is fabricated using industry sandard MOS processing techniques and which results in a capacitor having an extremely low voltage coefficient which is constant across a range of .+-.20 V. This invention includes a capacitor which is comprised of two MOS type thin-film capacitors similarly constructed by which are electrically connected to each other in an anti-parallel fashion, i.e., the polarity of one capacitor is connected to the reverse polarity of the other capacitor.

Prior to realizing the effect of connecting two MOS-type capacitors in an anti-parallel fashion, it was determined that the rate of change of the voltage coefficient per volt of a single capacitor was approximately constant over the voltage range of .+-.20 V and that the voltage coefficient varied linearly with the increase in voltage over the relevant range.

By connecting two similar capacitors in an anti-parallel fashion, it was surprisingly realized that the change in capacitance of each capacitor as the applied dc bias is increased or decreased exactly cancels out the linear variation in the capacitance of each individual capacitor due to the reverse polarity of the applied voltage across the two capacitors. The voltage coefficient of such an anti-parallel capacitor pair is zero over the .+-.20 V range.

Additional benefits, advantages and characteristic features of my invention will become more apparent when the following figures are considered together with the detailed desccription of my invention wherein like reference numerals refer to like parts throughout the drawings.

FIG. 1 is a partially schematic diagram of a thin-film capacitor of the type used in the present invention;

FIG. 2 is another schematic illustration of the thin-film capacitor of FIG. 1 illustrating the two conductive plates only;

FIG. 3 is a graphic illustration plotting the change in capacitance over the change in voltage (dC/dV) against the dc voltage (V) over a range of .+-.20 V to illustrate the variation in the voltage coefficient of a single standard MOS capacitor with the construction of FIG. 1;

FIG. 4 is another graphic illustration of the same data generated from the same capacitor of FIG. 3 but plotting the capacitance (C) against the voltage (V) within the range of .+-.20 V;

FIG. 5 is a schematic diagram of the invention illustrating two identical capacitors with the structure illustrated in FIG. 1 and which capacitors are connected in an anti-parallel fashion;

FIG. 6 is a partially schematic illustration of the two thin-film capacitors of FIG. 5 but illustrating only the two conductive plates of each capacitor and the anti-parallel connection of the two capacitors;

FIG. 7 is a graphic illustration of the change in capacitance over the change in voltage plotted against the voltage being applied to the capacitor structure of FIG. 5 and illustrating the constant voltage coefficient of the capacitor constructed in accordance with the invention; and

FIG. 8 is another graphic illustration of the capacitor illustrated in FIG. 5 plotting the capacitance against the voltage over a range of .+-.20 V.

FIG. 1 illustrates the structure of each of the single capacitors 1 which are combined in an anti-parallel or reverse polarity fashion (see discussion of FIG. 5 and FIG. 6 below) to accomplish the remarkable results of the invention. Capacitor 1 is fabricated with two condctive plates 4 and 10 being successively deposited onto substrate 2 and with a dielectric layer comprised of layers 6 and 8 deposited between conductive plates 10 and 4. Here, the dielectric layer is comprised of a layer of silicon dioxide (SiO.sub.2) and silicon nitride (SiN.sub.3) but it may be comprised of either SiO.sub.2 or SiN.sub.3 alone. In composition, the dielectric layer comprises approximately 1000 .ANG. of sioicon dioxide and approximately 1000 .ANG. in this embodiment is comprised of approximately 1% silicon.

The capacitor 1 of FIG. 1 is fabricated in the standard MOS process with each of the successive layers being deposited onto the substrate 2 and with each of the successive layers being etched and patterned accordingly.

FIG. 2 is a further schematic illustration of the top and bottom conductive plates of capacitor 1 in FIG. 1. The bottom electrode 4 and the top electrode 10 are illustratd with the dielectric layer being omitted in this illustration. As previously pointed out, the dielectric layer which is illustrated in FIG. 1 as layers 6 and 8 and which will be between plates 4 and 10 of FIG. 2 when the capacitor is fabricated may be a single insulated layer such as silicon dioxide or silicon nitride or may be combination of the two layers as is illustrated in FIG. 1. The capacitors illustrated in FIG. 1 and 2 are the standard form poly-metal capacitors.

When capacitor 1 was biased with a dc voltage over a range of -20 V to +20 V and with the reference capacitors being evaluated at 0 V, it was determined that the voltage coefficient of the capacitor varied linearly as a voltage within the relevant range was being applied to the capacitor 1. That is, it was observed that the rate of change of the voltage coefficient per volt had an approximately constant variaility over the voltage range of .+-.20 V. for example, the following data was derived when a dc voltage between -20 V to +20 V was applied to the capacitor of FIG. 1:

FIG. 3 illustrates that based on the above data derived from applying a voltage in the range of .+-.20 V to the capacitor of FIG. 1, the ratio of the change in capacitance to the change in voltage being applied was constant. That is, the change of the voltage coefficient of the capacitance 1 in FIG. 1 was constant although it varied substantially from 0 ppm.

The FIG. 4 graph illustrates how the capacitance varies linearly to the voltage being applied across the capacitor of FIG. 1. The data to derive this graph was taken from Table 1.

Upon realizing that the ratio of the change in the capacitance over the change in the voltage of capacitor 1 is constant over a voltage range of .+-.20 V (dc), and that the capacitance varies linearly with the voltage being applied to capacitor 1, it was determined that the capacitor in FIG. 1 could be incorporated into an embodiment which could possibly result in a capacitor with an extremely low voltage coefficient which would be very close to the range of 0 over a dc bias of .+-.20 V.

FIG. 5 illustrates one embodiment of the invention in which two capacitors 16 and 18, fabricated in the same manner as capacitor 1 of FIG. 1, are connected to each other in an anti-parallel fashion. That is, electrical contact 20 of capacitor 16 is connected to contact 26 of capacitor 18 and electrical contact 22 of capacitor 16 is connected to contact 24 of capacitor 18.

In order to illustrate that capacitor 16 and 18 of FIG. 5 are fabricated in the same manner as capacitor 1 of FIG. 1, the respective layers of capacitors 16 and 18have been given the same reference numeral designations as in FIG. 1 but with subscripts a and b.

FIG. 6 is a further schematic illustration of how capacitors 16 and 18 of FIG. 5 are electrically connected in order to result in a capacitor with a low voltage coefficient which is in the range of 0 ppm.

When the capacitor illustrated in FIG. 5 was tested to determine the voltage coefficient over a range of .+-.20 V (dc bias) being applied across the capacitor, the resulting data indicated that the voltage coefficient was close to 0 (FIG. 8) and that the ratio of the change in the capacitance over the change in the voltage being applied was thus close to 0. The following table illustrates the remarkable results of this experiment.

When the data resulting from Table 2 was plotted to determine the voltage coefficient of the capacitor in FIG. 5, it was determined that the voltage coefficient was not only constant but was close to 0. This result is illustrated in FIG. 7 and 8. The graphs of FIG. 7 and 8 were generated from the data in Table 2.

This invention has been described with respect to specific embodiments, such as whether dielectric layers comprise of two layers of silicon dioxide and silicon nitrite, but it must be understood that this invention is intended to cover any and all embodiments and equivalents which are within the scope of the appended claims. This invention is therefore limited only by the appended claims.