Two Transistor Full Wave Rectifier

This invention relates to integrated circuit type electronic devices and more particularly to the implementation of a full wave rectifier using two field effect transistors and selective substrate contacts.

According to a preferred embodiment, the two field effect transistors (FETs) are formed in a commonly doped region of a substrate, the FETs share a source/drain region which is connected to one side of the load, and the FETs use a substrate contact for connecting to the other side of the load. The remaining two source/drain regions of each transistor are connected to their respective gate electrodes, which commonly formed nodes are then individually connected to the two sides of an AC voltage source.

The two transistor configuration provides a full wave rectified output which can, with a supplemental capacitive filtering and voltage regulation, serve as a DC power source for integrated circuit devices. The present rectifier circuit is particularly useful for circuit applications where all functions are to be integrated on a common chip fabricated with CMOS field effect transistors operated by DC voltage yet powered from an AC source. A representative and preferred application would be one in which the power is transmitted to the chip from an electrical source by electromagnetic or capacitive coupling. Exemplary applications include pacemakers and "smart " credit cards or electronic keys.

These and other beneficial uses of the invention and its practice will be more clearly understood and appreciated upon considering the detailed description which follows.

FIG. 1 is a schematic of a p-channel embodiment of the invention.

FIG. 2 is a diagram schematically depicting a cross section of a representative p-channel embodiment interconnected to provide full wave rectification.

FIG. 3 is a schematic of an n-channel embodiment of the invention.

The prevalence of integrated circuit devices fabricated with CMOS technology has provided the opportunity to develop products which can perform relatively complex electronic functions yet operate with minimum power requirements. Similarly, the present trend is away from using electrochemical power sources, batteries, and toward system product designs which are powered by energy transmitted without wires, e.g., solar power calculators. In view of the low power requirements of many new integrated circuit designs, it is now also feasible to electromagnetically or capacitively couple, through an intervening dielectric, sufficient energy to power an integrated circuit chip for time coincident operation or extended operation where the coupled energy is stored by capacitive or rechargeable electrochemical means. One specific example might be a pacemaker which is recharged daily by electromagnetic coupling, while another might be a "smart " credit card or electronic key which is powered by insertion into a mechanism which electromagnetically couples both power and data to and from the chip, thereby substantially negating the problems associated with electrical contacts. Consequently, there exists the need for an electronic circuit which can be fabricated on a CMOS chip and can efficiently convert AC energy to the DC form suitable for time coincident use or extended storage.

The present two field effect transistor implementation of a full wave rectifier provides the requisite features, in that the structure involves the use of a standard integrated circuit arrangement of minimal complexity, can be configured to avoid latchup parasitic bipolar transistors often encountered in CMOS circuits, can be implemented using either a p-well or n-well CMOS fabrication processes, does not unduly dissipate power under normal operating conditions, and can be readily interconnected to other integrated circuit elements to provide filtering or regulation of the rectified DC voltage.

These features are in contrast to designs such as that disclosed in U.S. Pat. No. 4,276,592, which reference teaches an implementation for a rectifier which is half wave and requires a current limiting, power consuming, resistor to avoid short circuit conditions. A design which is functionally more similar, but structurally distinguishable, is described in recently published U.S. Statutory Invention Registration No. H64. That particular structural arrangement requires electrical isolation of the implementing field effect transistors, by placement in separate wells, and the use of numerous, physically dispursed diffusions and contacts to establish the necessary p-n junction rectification.

One preferred embodiment of the present invention is depicted schematically in FIG. 1 of the drawings. A cross section of a p-well CMOS integrated circuit implementation of the schematic is depicted in FIG. 2 of the drawings, retaining for purposes of clarity schematic representations of the electrical connections, AC input, and equivalent DC load.

Referring to FIG. 1, AC power is furnished by AC input voltage supply 1 at nodes 2 and 3, which nodes are respectively connected to gate electrode 4 and drain electrode 6 of p-channel field effect transistor 7, and connected to gate electrode 8 and drain electrode 9 of p-channel field effect transistor 11. Both field effect transistors are enhancement type devices. The source electrodes, 5 and 10 (doped region 18 in FIG. 2), of respective transistors 7 and 11 are commonly connected to node 12, which node is connected to ground potential and also serves as one connection to equivalent resistive load 13. The other side of the equivalent resistive load 13 is connected to the node 14, the substrate (doped contact regions 19 and 21 in FIG. 2)

The presence of an AC voltage between nodes 2 and 3 produces a plus DC voltage having a full wave rectified waveform on node 14 with respect to ground node 12. The shape of DC voltage on node 14 is influenced by the shape of the AC input, the threshold voltages of transistor 7 and 11, including any back bias effects on these transistors, and a diode voltage drop. Distributed capacitance filtering effects are also present. For example, the DC voltage on node 14 can range from a slightly clipped full wave rectified sinusoidal pattern to a near DC level for a square wave AC input.

FIG. 2 illustrates by way of schematic cross section a preferred embodiment of the invention in the context of a p-well CMOS integrated circuit. This embodiment should not be construed as a limitation, in that the invention is fully subject to practice in devices fabricated with an n-well CMOS processes as well as with individual NMOS or PMOS fabrication processes. Likewise, the configuration is amenable to epitaxial structures in lieu of wells. However, in all cases care must be exercised to avoid structures which are susceptible to latch-up.

The embodiment depicted in FIG. 2 is formed in an n.sup.- substrate 16, and includes an optional well 17 of p.sup.- impurity. As shown, the structure is comprised of p-channel field effect transistors 7 and 11, individually responsive to respective gate electrodes 4 and 8 situated between p.sup.+ source/drain regions 6, 9 and 18, the latter being shared by both transistors. The shared source/drain region 18 is connected to ground node 12 and one side of equivalent load 13. Source/drain region 6 of transistor 7 is connected in common with gate electrode 4 to node 2, which node itself is connected to one side of AC input 1. Similarly, source/drain region 9 is connected in common with gate electrode 8 of transistor 11 to node 3, which node is connected to the other side of AC input 1. The plus DC voltage appears on node 14, which is connected to the other side of equivalent load 13 and to n.sup.+ diffusions 19 and 21 in substrate 16. The use of multiple n.sup.+ diffusions, in contrast to the minimum requirement of a single substrate surface contact, as well as the creation of n.sup.+ channel stops 22, 23, 24 and 26 under a field oxide regions 27, 28, 29 and 31, implements known carrier trapping techniques in view of the charge injected into substrate 16. Charge is injected into substrate 16 when the p-n junctions 6 to 16 or 9 to 16 are forward biased. Note further that layout density and charge injection benefits may accrue by deleting field oxide regions 28 and 29, so as to place p.sup.+ diffusions 6 and 9 into immediate contact with respective n.sup.+ contact diffusions 19 and 21, forming the requisite diode therebetween.

To understand the operation of the circuit as structurally depicted in FIG. 2 consider a situation in which AC input 1 is a sinusodial voltage source, having peak values of +7 and -7 volts, and field effect transistors 7 and 11 have nominal threshold voltages of -0.9 volts. During that instant of time when AC input 1 is generating a voltage of +7 volts at node 3 with respect to node 2, the junction between p.sup.+ region 9 and composite substrate 16/n.sup.+ contact region 21 is positively biased, providing the +7 volts less the p-n junction diode drop to node 14 of equivalent load 13. The other side of equivalent load 13 is connected to AC input 1 through field effect transistor 7, which is conductively biased whenever the instantaneous AC input voltage is greater than the combination of the p-n drop and the threshold voltage of transistor 7, approximately 1.6 volts. The end effect is that load 13 experiences a rectified voltage having a 5.4 volt peak. When the AC input voltage reverses, conventional current conduction is from node 2, through p.sup.+ region 6, to n.sup.+ region 19 (and 21), through load 13, to node 12, and through forward biased field effect transistor 11 to node 3.

Unfiltered full wave rectified DC voltage is in most cases unacceptable for operating an integrated circuit. However, when the power demands are minimal, such as is common for many CMOS integrated circuits, on-chip capacitive filtering is feasible. With limited power demands, sufficient filtering can often be obtained from the parasitic capacitive effects of n-channel device diffusions in p-wells. If such distributed capacitance proves to be inadequate for effective filtering, it is also feasible to add capacitive structures. For instance, in the context of FIG. 2, there is shown the possibility of forming a junction capacitor between n.sup.+ region 32 and p-well 17, which can then be connected by line 33 to filter the DC voltage on node 14. As is no doubt understood, though equivalent load 13 represents functional electronic devices on the same substrate 16, it may, if the occasion arises, include elements external to the integrated circuit chip represented by substrate 16.

Consideration of the circuit and structure depicted in FIG. 2 will disclose the presence of a number of unique features. First, although the structure is preferably used in conjunction with a CMOS integrated circuit, the underlying concepts are similarly applicable to NMOS and PMOS processed devices. Secondly, the circuit depicted in FIG. 2 does not have local latch-up susceptibility, in that a parasitic bipolar transistor structure is not created. The absence of latch-up susceptibility is valid for p-channel devices formed in an n-type substrate, or in the complementary n-well fabrication process, when n-channel transistors are formed in a p-type substrate. Any attempt to place p-channel transistors in an n-well of a p-type substrate, or an attempt to place n-channel transistors in a p-well of an n-type substrate will create a parasitic vertical bipolar transistor structure susceptible to latch-up.

The complement to the circuit schematically depicted in FIG. 1, and shown by way of cross section in FIG. 2, is schematically depicted in FIG. 3. As depicted, AC input 1 at nodes 2 and 3 drives n-channel transistors 34 and 36 to provide a full wave rectified DC voltage across load 13, the load voltage polarity now being opposite that previously generated with respect to the substrate. Again, field effect transistors 34 and 36 are enhancement mode types, here preferably configured to have a threshold voltage of approximately +0.7 volts. The cross sectional schematic depicted in FIG. 2 would be equally applicable to the arrangement in FIG. 3, with an interchange of the impurity types for the various regions and a reversal of the ground and DC voltage connections to equivalent load 13.

The establishment of the threshold voltages for p-channel transistors such as 7 and 11 in FIG. 2 must take into account the back bias effects associated with the injection of charge into substrate 16 from diffusions 6 and 9. Note that in the case of the n-channel transistor design schematically depicted in FIG. 3 the substrate is at ground and back bias effects are absent.