Current Generating Circuit

1. Field of the Invention

This invention relates generally to a current generating (dynamic element matching) circuit, and more particularly to such a current generating circuit which is suitable for use in current switching for a digital-to-analog (D/A) converter.

2. Description of the Prior Art

First, a previously proposed current generating circuit 4, disclosed in Japanese Patent Publication No. 54-24098, will hereinafter be explained with reference to FIG. 1.

The current generating circuit 4 comprises a current dividing circuit 3 in a current mirror configuration which is formed of transistors Q.sub.1 and Q.sub.2. Currents I.sub.1 and I.sub.2 passing through the transistors Q.sub.1 and Q.sub.2 are respectively obtained by dividing a current 2I substantially by two, so that the currents I.sub.1 and I.sub.2 are substantially equal to each other. A pair of differential switching circuits 1a and 1b, which form a current change-over circuit 2, respectively switch and deliver the currents I.sub.1 and I.sub.2 alternately to a pair of output terminals T.sub.3 and T.sub.4. The differential switching circuit 1a is formed of a pair of transistors Q.sub.3 and Q.sub.4 which have their emitters connected with each other, and their connecting point is connected with the collector and the base of the transistor Q.sub.1. The other differential switching circuit lb is formed of a pair of transistors Q.sub.5 and Q.sub.6 which have their emitters connected with each other, and their connecting point is connected with the collector of the transistor Q.sub.2.

The collectors of the transistors Q.sub.3 and Q.sub.5 are connected to the output terminal T.sub.3 in common, while the collectors of the transistors Q.sub.4 and Q.sub.6 are to the other output terminal T.sub.4 in common. The output terminals T.sub.3 and T.sub.4 are grounded respectively through capacitors Cx and Cy constituting low pass filters.

The input terminals T.sub.1 and T.sub.2, for switching, are fed with a pair of opposite-phased switching signals E.sub.1 and E.sub.2 with a predetermined frequency. The switching input terminal T.sub.1 is connected to the bases of the transistors Q.sub.3 and Q.sub.6 in common, while the other switching input terminal T.sub.2 is connected to the bases of the transistors Q.sub.4 and Q.sub.5 in common.

Next, the operation of the current generating circuit 4 will be explained. When the switching signal E.sub.1 supplied to the input terminal T.sub.1 is at a high level, the switching signal E.sub.2 supplied to the input terminal T.sub.2 is at a low level, so that the transistors Q.sub.3 and Q.sub.6 are turned on while the transistors Q.sub.4 and Q.sub.5 are turned off. Therefore, the current I.sub.1 from the current dividing circuit 3 is delivered to the terminal T.sub.3 and the current I.sub.2 is delivered to the terminal T.sub.4, respectively.

When the switching signal E.sub.2 supplied to the switching input terminal T.sub.2 is at the high level, the switching signal E.sub.1 supplied to the input terminal T.sub.1 is at the low level, so that the transistors Q.sub.4 and Q.sub.5 are turned on while the transistors Q.sub.3 and Q.sub.6 are turned off. Therefore, the current I.sub.1 from the current dividing circuit 3 is delivered to the terminal T.sub.4 and the current I.sub.2 is delivered to the terminal T.sub.3, respectively.

Thus, the output terminal T.sub.3 is alternately fed with the currents I.sub.1 and I.sub.2, while the output terminal T.sub.4 is alternately fed with the currents I.sub.2 and I.sub.1. These currents I.sub.2 and I.sub.1 are averaged by the capacitors Cx and Cy constituting the low pass filters, so that both of the output terminals T.sub.3 and T4 are equally fed with a current I (I=(I.sub.1 +I.sub.2)/2), as a result. In other words, the current generating circuit 4 can provide at its two output terminals the output current I which is derived by accurately dividing the input current 2I supplied thereto by two.

Let it now be assumed that the current generating circuits 4a, 4b and 4c, each being explained with reference to FIG. 1 as disclosed in Japanese Patent Publication No. 54-24098, are connected upward in a piling manner as shown in FIG. 2. The current generating circuit 4a at the first stage is disposed to divide the input current 2I by two to obtain the two output currents, I and I, one of which is delivered to the output terminal T.sub.4, and the other of which is supplied to one input terminal of the current generating circuit 4b at the next stage.

Then, the current generating circuit 4b is disposed to divide the input current I by two to obtain two output currents I/2 and I/2 , one of which is outputted to an output terminal T.sub.5, and the other of which is supplied to one input terminal of the current generating circuit 4c at the third stage.

By repeating the above operation, the current generating circuit 4c at the third stage derives a current I/4 at its output terminal T.sub.6. Incidentally, reference letters T.sub.3, T.sub.3 ' and T.sub.3 " designate the other output terminals of the current generating circuits 4a, 4b and 4c, respectively.

If each of the output currents delivered to the output terminals T.sub.4, T.sub.5 and T.sub.6 are controlled independently by different switches which are turned on and off in accordance with binary combinations of a 3-bit digital signal, a current generator type D/A converter can be formed.

The current generating circuit 4 shown in FIG. 1 can derive the substantially equal current at the output terminals T.sub.3 and T.sub.4 by averaging the input currents I.sub.1 and I.sub.2 supplied to the differential type switching circuits 1a and lb. However, if the current generating circuits are arranged in multi-stage as shown in FIG. 2, to form e.g. an n-bit D/A converter, the total number of the transistors Q.sub.3 and Q.sub.4, for example, in the differential switching circuit la is increased by n times, so that the voltage necessary to operate all these transistors Q.sub.3 and Q.sub.4 or the like becomes higher as the bit number of the D/A converter is increased.

To solve the above-mentioned problem, Japanese Patent Publication No. 57-31809 discloses to derive from the single current generating circuit 4 the output currents I, I/2, I/4 . . . which have been delivered one by one from the current generating circuits 4a, 4b, 4c . . . That is, the single current generating circuit provided with a plurality of output terminals for deriving a plurality of output currents, for example I and I/2, is disclosed. The construction shown in this document can reduce the number of the current generating circuits 4a, 4b, 4c . . . which are piled by connecting in multiple stages, as shown in FIG. 2, thereby making it possible to reduce the source voltage.

A single-stage current generating circuit equivalent to the above-mentioned two-stage current generating circuit and the operating waveforms thereof is explained below with reference to FIGS. 3 and 4, by using the principle of Japanese Patent Publication No. 57-31809.

In FIG. 3, reference numeral 4 designates an overall current generating circuit in which an input terminal T.sub.15 is connected e.g. to a current generating circuit for the upper digit, and an output terminal T.sub.14 to a current generating circuit for the lower digit, in a manner that they are piled in multiple stages, similarly to FIG. 2. The current dividing circuit 3 is formed of a current-mirror circuit comprising transistors Q.sub.11, Q.sub.12, Q.sub.13 and Q.sub.14, for dividing an input current I supplied to the input terminal T.sub.15 substantially equally by four. That is, the input current is divided into 2.sup.n (n=2, 3, 4 . . .). The collectors of the transistors Q.sub.11 to Q.sub.14 are connected to switching circuits 11, 12, 13 and 14, respectively, while the bases and the emitters thereof are respectively connected in common. The base of the transistor Q.sub.11 is connected to the collector of the same. The switching circuits 11, 12, 13 and 14 are respectively formed of switching transistors Q.sub.15 to Q.sub.18, Q.sub.19 to Q.sub.22, Q.sub.23 to Q.sub.26 and Q.sub.27 to Q.sub.30. The emitters of the transistors Q.sub.15 to Q.sub.18, Q.sub.19 to Q.sub.22, Q.sub.23 to Q.sub.26 and Q.sub.27 to Q.sub.30 comprised in the switching circuits 11, 12, 13 and 14 are respectively connected in common. A control terminal T.sub.10 is connected to the respective bases of the transistors Q.sub.15, Q.sub.19, Q.sub.23 and Q.sub.27, while a control terminal T.sub.11 is connected to the respective bases of the transistors Q.sub.16, Q.sub.20, Q.sub.24 and Q.sub.28. Further, a control terminal T.sub.12 is connected to the respective bases of the transistors Q.sub.17, Q.sub.21, Q.sub.25 and Q.sub.29, while a control terminal T.sub.13 is connected to the respective bases of the transistors Q.sub.18, Q.sub.22, Q.sub.26 and Q.sub.30. The collectors of the transistors Q.sub.15, Q.sub.20, Q.sub.25 and Q.sub.30 arranged in the switching circuits 11 to 14 are connected in common to a first output terminal T.sub.16. A capacitor C.sub.1 forming a low pass filter is interposed between the first output terminal T.sub.16 and ground. In the same manner, the collectors of the transistors Q.sub.16, Q.sub.21, Q.sub.26, Q.sub.27 and Q.sub.30 are connected in common to the output terminal T.sub.16. Further, the collectors of the transistors Q.sub.17, Q.sub.22, Q.sub.23 and Q.sub.28 are connected in common to a second output terminal T.sub.17. A capacitor C.sub.2 forming a low pass filter is interposed between the second output terminal T.sub.17 and ground. Further in the same manner, the collectors of the transistors Q.sub.18, Q.sub.19, Q.sub.24 and Q.sub.29 are connected in common to the output terminal T.sub.14 `which leads to the current generating circuit for the lower digit. A capacitor C.sub.3 forming a low pass filter is interposed between the output terminal T.sub.14 and ground.

In the construction shown in FIG. 3, the control terminals T.sub.10 to T.sub.13 are respectively supplied with control pulses A.sub.1 to A.sub.4 as shown in FIG. 4. For example, when the control terminal T.sub.10 is supplied with the pulse A.sub.1, the transistors Q.sub.15, Q.sub.19, Q.sub.23 and Q.sub.27 are turned on and maintain the "on" condition as long as the pulse A.sub.1 is at the high level, so that a current flows in the direction indicated by the arrow. The same operation is carried out with the pulses A.sub.2 to A.sub.4. When the current I is fed to the input terminal T.sub.15, the current I/2 is derived at the first output terminal T.sub.16 and the current I/4 is derived at the second output terminal T.sub.17 and the terminal T.sub.14.

With the circuit construction of FIG. 3 as described above, while the control terminals T.sub.10 to T.sub.13 are respectively applied with the pulsed A.sub.1 to A.sub.4 for one cyclic period thereof, the switching circuit 11 has the transistors Q.sub.15 and Q.sub.16, connected to the output terminal T.sub.16 in common, turned on to flow the current to the transistor Q.sub.11 arranged in the current dividing circuit 3. The switching circuit 12, in the same manner, has the transistors Q.sub.20 and Q.sub.21 turned on to flow the current to the transistor Q.sub.12 in the current dividing circuit 3, the switching circuit 13 also has the transistor Q.sub.25 and Q.sub.26 turned on to flow the current to the transistor Q.sub.13 in the current dividing circuit 3, and the switching circuit 14 has the transistors Q.sub.27 and Q.sub.30 turned on to flow the current to the transistor Q.sub.14 of the current dividing circuit 3. Thus, if the number of the transistors arranged in the current dividing circuit 3 (the current source are increased to 2, 4, 8, 16 . . . 2.sub.n, or if the number of the processed bits (output derived at the output terminals T.sub.16 and T.sub.17) taken out from each of the current generating circuits 4a, 4b . . . connected in the piling manner as shown in FIG. 2 are increased to 1, 2, 3 ... n, the number of transistors in the switching circuits 11 to 14 for turning on and off each of the transistors in the current dividing circuit 3 is correspondingly increased to 2, 4, 8 . . .2.sub.n. Particularly, for realizing a highly accurate D/A converter the number of necessary transistors becomes inacceptably immense.

Further, the current change-over circuit 2 formed of the differential switches 1a and 1b shown in FIG. 1 presents another disadvantage in that the emitter currents of the respective transistors Q.sub.3 to Q.sub.6 thereof do not wholly flow to their collectors but the collector current is only, .beta./(1+.beta.), a portion of the emitter current and the rest, 1/(1+.beta.), of the same flows to the base. In other words, the output currents delivered to the output terminals T.sub.3 and T.sub.4 are reduced by 1/(1+.beta.) from (I.sub.1 +I.sub.2)/2. Accordingly, if the current generating circuits of FIG. 1 are connected in multiple stages as shown in FIG. 2, the error in the output current becomes larger in further succeeding stages, so that if it is used as the aforementioned current source type D/A converter, there will be produced a large conversion error.

This problem can be solved by constructing the transistors Q.sub.3 to Q.sub.6 of the differential switching circuits la and lb in the current change-over circuit 2 shown in FIG. 1 in a Darlington configuration to thereby make the .beta. factor substantially large.

FIG. 5 illustrates a circuit in which the differential switching circuit la, for example, of the current change-over circuit 2 in FIG. 1 is formed in a Darlington configuration. In this example, the transistor circuit Q.sub.3 is formed of a pair of Darlington-connected transistors Q.sub.3a and Q.sub.3b, and the transistor circuit Q.sub.4 is formed of a pair of Darlington-connected transistors Q.sub.4a and Q.sub.4b. Specifically, the emitter of the transistor Q.sub.3b is connected to the base of the transistor Q.sub.3a, while the collector of the transistor Q.sub.3a is connected to the collector of the transistor Q.sub.3b. The emitter of the transistor Q.sub.4b is connected to the base of the transistor Q.sub.4a, while the collector of the transistor Q.sub.4a is connected to the collector of the transistor Q.sub.4b.

Assuming that the factors .beta. of the transistors Q.sub.3a to Q.sub.4b are equal, the current flowing to the bases of the respective transistors Q.sub.3b and Q.sub.4b is represented by I.sub.1 /(1+.beta.).sup.2. It is therefore understood that the accuracy of the output current for the input current is improved.

However, such a configuration causes a minimal operating voltage at the output terminals T.sub.3 and T.sub.4, on the basis of the common emitter of the transistors Q.sub.3a and Q.sub.4a, to be twice the base-emitter voltage V.sub.BE of the transistors Q.sub.3a to Q.sub.4b, that is, 2V.sub.BE. Therefore, if the current generating circuits are connected in multiple stages as shown in FIG. 2, the minimal operating voltage for the current generating circuit at the highest stage will be four times the value 2V.sub.BE. Thus, as the number of stages is increased, the minimal operating voltage thereof is largely elevated.

In view of the inconvenience mentioned above, it is an object of the present invention to provide a current generating circuit which is capable of reducing the number of transistors arranged in switching circuits thereof.

It is another object of the present invention to provide a current generating circuit which is capable of reducing the error occurring in the output currents with respect to the input current as well as preventing elevation of the minimal operating voltage when the current generating circuits are connected in multiple stages.

According to a first aspect of the present invention, there is provided a current generating circuit for generating a plurality of currents accurately in a predetermined integer ratio, comprising:

(a) a current dividing circuit for dividing an input current into 2.sup.n (n is a positive integer);

(b) a plurality of current change-over circuits for dividing respective output currents from said current dividing circuit in a predetermined ratio by supplying to input terminals thereof a predetermined number of change-over clock signals in one cyclic period; and

(c) a current synthesizing circuit for synthesizing the output currents from said respective current change-over circuits and generating currents in a predetermined ratio.

According to a second aspect of the present invention, there is provided a current generating circuit for generating a plurality of currents accurately in a predetermined integer ratio, comprising:

(a) at least two sets of first and second current dividing devices each comprising a current dividing circuit for dividing an input current into 2.sup.n (n is a positive integer), a plurality of current change-over circuits for dividing respective output currents from said current dividing circuit in a predetermined ratio and a current synthesizing circuit for synthesizing the output currents from said respective current change-over circuits and generating currents in a predetermined ratio; and

(b) a voltage compensating circuit connected between an output terminal of said second current generating circuit and an output terminal of said first current generating circuit for shifting the voltage level of a first input voltage.

These and other objects, features and advantages of the present invention will become apparent from the following detailed description of the preferred embodiments taken in conjunction with the accompanying drawings, throughout which like reference numerals designate like elements and parts .

FIG. 1 is a schematic circuit diagram showing a previously proposed current generating circuit;

FIG. 2 is a block circuit diagram showing a previously proposed current generating circuit;

FIG. 3 is a schematic circuit diagram showing another previously proposed current generating circuit;

FIG. 4 is timing charts showing the waveforms of control pulses which are applied to the current generating circuit of FIG. 3;

FIG. 5 is a schematic circuit diagram showing a previously proposed differential switching circuit;

FIG. 6 is a schematic circuit diagram showing an embodiment of a current generating circuit according to the present invention;

FIG. 7 is timing charts showing the waveforms of control pulses which are applied to the current generating circuit of FIG. 6;

FIG. 8 is a schematic circuit diagram showing an embodiment of a differential switching circuit according to the present invention;

FIG. 9 is a schematic circuit diagram showing another embodiment of a differential switching circuit according to the present invention; and

FIG. 10 is a schematic circuit diagram showing a further embodiment of the present invention.

Now, a first embodiment of a current generating circuit according to the present invention will hereinafter be described with reference to FIGS. 6 and 7.

FIG. 6 is a circuit diagram showing the first embodiment of the current generating circuit 4 according to the present invention, and FIG. 7 shows waveform charts of respective control signals supplied to control terminals shown in FIG. 6, wherein the parts corresponding to those in FIG. 3 are designated the same reference numerals and a repeated explanation thereof will be omitted.

In FIG. 6, the transistors Q.sub.11, Q.sub.12, Q.sub.13 and Q.sub.14 arranged in the current dividing circuit 3 of the current generating circuit 4 are constructed in the same manner as those in FIG. 3. Switching circuits 15, 16, 17 and 18 are respectively formed of three sets of switching transistors Q.sub.18, Q.sub.17 and Q.sub.31 ; Q.sub.19, Q.sub.22 and Q.sub.32 ; Q.sub.24, Q.sub.23 and Q.sub.33 ; and Q.sub.29, Q.sub.28 and Q.sub.34, among which the transistors Q.sub.31, Q.sub.32, Q.sub.33 and Q.sub.34 are switching transistors performing also the functions of the transistors Q.sub.15 and Q.sub.16 ; Q.sub.20 and Q.sub.21 ; Q.sub.25 and Q.sub.26 ; and Q.sub.27 and Q.sub.30, as shown in FIG. 3, respectively.

The respective sets of the three transistors Q.sub.18, Q.sub.17 and Q.sub.31 ; Q.sub.19, Q.sub.22 and Q.sub.32 ; Q.sub.24, Q.sub.23 and Q.sub.33 ; and Q.sub.29, Q.sub.28 and Q.sub.34 respectively constituting the four switching circuits 15, 16, 17 and 18 have their emitters commonly connected to the respective collectors of the transistors Q.sub.11, Q.sub.12, Q.sub.13 and Q.sub.14 in the current dividing circuit 3. The collectors of the respective transistors Q.sub.31, Q.sub.32, Q.sub.33 and Q.sub.34 in the switching circuits 15 to 18 are connected in common to the first output terminal T.sub.16 for the upper digit, while the bases of the transistors and Q.sub.33 and Q.sub.33 are connected together to a control terminal T.sub.19 which is supplied with a control pulse B.sub.1 shown in FIG. 7. The bases of the transistors Q.sub.32 and Q.sub.34 are connected together to a control terminal T.sub.18 which is supplied to a control pulse B.sub.2 (with the opposite-phased pulse with respect to the control pulse B.sub.1) as shown in FIG. 7.

The collectors of the transistors Q.sub.17, Q.sub.22, Q.sub.23 and Q.sub.28 are connected in common to form a current synthesizing circuit, the output terminal of which is connected to a second output terminal T.sub.17 for the second most significant bit. The base of the transistor Q.sub.17 is connected to a control terminal T.sub.22 which is supplied with the control pulse A.sub.3 shown in FIG. 7, while the base of the transistor Q.sub.22 is connected to a control terminal T.sub.23 which is supplied with the control pulse A.sub.4 shown in FIG. 7. Further, the base of the transistor Q.sub.23 is connected to a control terminal T.sub.20 which is supplied with the control pulse A.sub.1 shown in FIG. 7, while the base of the transistor Q.sub.28 is connected to a control terminal T.sub.21 which is supplied with the control pulse A.sub.2 shown in FIG. 7. The control pulses A.sub.1 to A.sub.4 are four-phase pulses synchronized with the control pulses B.sub.1 and B.sub. 2.

The collectors of the transistors Q.sub.18, Q.sub.19, Q.sub.24 and Q.sub.29 form a current synthesizing circuit the output terminal of which is connected to the output terminal T.sub.14 which leads to the current generating circuit for the lower digit (not shown). The base of the transistor Q.sub.18 is connected to the terminal T.sub.20 which is supplied with the control pulse A.sub.1 shown in FIG. 7. Likewise, the base of the transistor Q.sub.19 is connected to the terminal T.sub.21, the base of the transistor Q.sub.24 to the control terminal T.sub.22, and the base of the transistor Q.sub.29 to the control terminal T.sub.23, while these control terminals T.sub.20, T.sub.21, T.sub.22 and T.sub.23 are supplied with the control pulses A.sub.1, A.sub.2, A.sub.3 and A.sub.4 shown in FIG. 7, respectively.

The transistors Q.sub.18 Q.sub.19, Q.sub.24 and Q.sub.29 in the switching circuits 15 to 18 or the current synthesizing circuit formed by connecting their collectors makes the output current, obtained by dividing the input current I by four, pass therethrough for a quarter of one cyclic period T when the respective control pulses A.sub.1 to A.sub.4 are at the high level and delivers the same to the output of the current synthesizing circuit. The transistors Q.sub.17, Q.sub.22, Q.sub.23 and Q.sub.28 in the switching circuits 15 to 18 or the current synthesizing circuit formed by connecting their collectors makes the output current I/4, obtained by dividing the input current by four, pass therethrough for a quarter of one cyclic period T when the respective control pulses A.sub.3, A.sub.4, A.sub.1 and A.sub.2 are at the high level and delivers the same to the output of the current synthesizing circuit. Further, the two transistors Q.sub.31 and Q.sub.33 among the transistors Q.sub.31 to Q.sub.34, each of which takes the place of two switching transistors in the switching circuits 11-14 in FIG. 3, make the output current I/2 obtained by dividing the input current I by two pass therethrough for half the period T when the control pulse B.sub.1 is at the high level. The high level period of the control pulse B.sub.1 is coincident with the on-period or high level period of the control pulses A.sub.2 and A.sub.4.

In the same manner, the transistors Q.sub.32 and Q.sub.34 make the output current I/2 obtained by dividing the input current I by two pass therethrough for half the cyclic period T in which the control pulse B.sub.2 is at the high level. The control pulse B.sub.2 goes high in level in synchronism with the high level periods of the control pulses A.sub.1 and A.sub.3. Thus, the switching circuits 15 to 18 can constitute current synthesizing circuits which generate a first output current obtained by dividing the input current I by 2.sup.n and a second output current obtained by dividing the input current I by 2.sup.m (m=1, 2, 3 . . . and m<n).

The above-mentioned embodiment was given to the case of the 2-bit current generating circuit 4 in which the switching transistors Q.sub.31 to Q.sub.34 are turned on twice by the control pulses B.sub.1 and B.sub.2 for one cyclic period T in which the control pulses A.sub.1 to A.sub.4 sequentially become the high level. If a 3-bit current generating circuit is concerned, for example, the second bit is applied with a control pulse which turns on the switching transistors twice within one cyclic period of the control pulse for the lower digit bit 20 corresponding to the control pulses A.sub.1 to A.sub.4 and the most significant bit is applied with a control pulse which turns on the switching transistors four times within the cyclic period T. The same can be adapted to the case of an n-bit current generating circuit.

In the above embodiment, the time period is weighted by the number of the control pulses A.sub.1 to A.sub.4. Alternatively, the weighting of the time may be effected by changing the pulse width of the control pulses.

Next, an embodiment of a current change-over circuit according to the present invention will hereinafter be explained with reference to FIG. 8 in which the present invention is adapted to the current dividing circuit 3 to form the current generating circuit 4. The parts in FIG. 8 corresponding to those in FIG. 6 are designated the same reference numerals and a repeated explanation thereof will be omitted. Also, capacitors constituting low pass filters are not illustrated in FIG. 8.

The transistor circuits Q.sub.3, Q.sub.4, Q.sub.5 and Q.sub.6 of the differential switching circuits la and lb in the current change-over circuit 2 are respectively formed of transistors Q.sub.3a and Q.sub.3b ; Q.sub.4b and Q.sub.4b ; Q.sub.5a and Q.sub.5b ; and Q.sub.6a and Q.sub.6b, each being connected in a Darlington configuration.

The emitters of the transistors Q.sub.3b, Q.sub.4b, Q.sub.5b and Q.sub.6b are respectively connected to the bases of the transistor Q.sub.3a, Q.sub.4a, Q.sub.5a and Q.sub.6a. The emitters of the transistors Q.sub.3a and Q.sub.4a are connected in common to a current source IS.sub.1, while the emitters of the transistors Q.sub.5a and Q.sub.6a are connected in common to a current source IS.sub.2. Further, the input terminal T.sub.1 which is applied with the switching signal (refer to FIG. 1) is connected to the bases of the transistors Q.sub.3b and Q.sub.6b in common, while the input terminal T.sub.2 which is applied with another switching signal is connected to the bases of the transistors Q.sub.4b and Q.sub.5b in common.

The collectors of the transistors Q.sub.3a and Q.sub.5a are connected with each other, and the potential V.sub.BE at the connecting point therebetween becomes the minimal operating voltage for the emitter voltage (hereinafter referred to as "reference potential") of the transistors Q.sub.3a and Q.sub.5a. The collectors of the transistors Q.sub.4a and Q.sub.6a are connected to each other, and the minimal operating voltage at the connecting point therebetween with respect to the reference potential is V.sub.BE. Therefore, if these connecting points are connected to the current dividing circuit in the next stage, the elevation of the minimal operating voltage due to the multi-state connection can be suppressed.

Since the minimal operating voltage with respect to the reference potential of each collector of the transistors Q.sub.3b to Q.sub.6b is 2V.sub.BE, these collectors are connected to a high voltage level (2V.sub.BE) in the next stage.

Next, an example of connecting the current generating circuit 4 formed of the current dividing circuit 3 and the current change-over circuit 2 shown in FIG. 8 in two stages is explained with reference to FIG. 9. In this example, reference numeral 4 designates a current generating circuit in the first stage to which a current dividing circuit 4' in the next stage is connected. In the next stage, only a current dividing circuit 3' is illustrated.

The collectors of the transistors Q.sub.3a and Q.sub.5a arranged in the current change-over circuit 2 in the first stage current generating circuit 4 are connected to the output terminal T.sub.3, and further to the emitters of the transistors Q'.sub.1 and Q'.sub.2 of the current dividing circuit 3' in the next stage in common. The collectors of the transistors Q.sub.4a, Q.sub.4b, Q.sub.6a and Q.sub.6b are connected in common to the output terminal T.sub.4 as well as to ground through a capacitor Cy constituting a low pass filter. Further, the collector of the transistor Q.sub.3b is connected to the base of the transistor Q'.sub.1 output terminal T.sub.5, while the collector of the transistor Q.sub.5b is connected to the collector of the transistor Q'.sub.2 through the output terminal T.sub.6.

Since the minimal operating voltage of the collectors of the transistors Q.sub.3a and Q.sub.5a with respect to the reference voltage is V.sub.BE, these collectors are respectively connected to the emitters of the transistors Q'.sub.1 and Q'.sub.2 in the current dividing circuit 3'. Meanwhile, since the minimal operating voltage of the collectors of the transistors Q.sub.3b and Q.sub.5b with respect to the reference potential is 2V.sub.BE, these collectors are respectively connected to the collectors of the transitors Q'.sub.1 and Q'.sub.2.

In this construction, the output current delivered to the output terminal T.sub.3 (called "the main current") is represented I.sub.0 ', and the output current delivered to the output terminal T.sub.4 by I.sub.01. The collector current of the transistor Q.sub.3b (called "the correcting current") is represented by I.sub.5, the collector current of the transistor Q.sub.5b (also called "the correcting current") by I.sub.9. The collector currents of the transistors Q'.sub.1 and Q'.sub.2 of the current dividing circuit 3' are represented by I.sub.1 ' and I.sub.2 ', respectively.

Now, if the difference between the currents I.sub.1, I.sub.2 and I.sub.0 /2 (I.sub.0 is an input current) is represented by .+-..DELTA..sub.1, and the difference between the currents I'.sub.1, I'.sub.2 and I.sub.0 '/2 by .+-..DELTA..sub.2, the currents I.sub.1, I.sub.2, I'.sub.1 and I'.sub.2 are expressed by the following equations: ##EQU1## where .beta..sub.3a, .beta..sub.3b, .beta..sub.5a and .beta..sub.5b are the factors .beta. of the respective transistors Q.sub.3a, Q.sub.3b, Q.sub.5a and Q.sub.5b.

It is understood from the equations (1) to (4) that even without connecting the collectors of the transistors Q.sub.3a and Q.sub.3b, and those of the transistors Q.sub.5a and Q.sub.5b connected in Darlington configuration for forming the transistor circuits Q.sub.3 and Q.sub.5, the respective emitters, bases and collectors thereof have the same current relationship as in the case where the collectors are connected to each other, and accordingly the factors .beta. thereof can be made larger.

Next, a further embodiment of the present invention will be explained with reference to FIG. 10. This embodiment is such that the current generating circuit 4 at the first stage is connected to a current generating circuit 4' at the next stage, wherein transistor circuits Q.sub.3 to Q.sub.6 and Q'.sub.3 to Q'.sub.6 of their current change-over circuits 2 and 2' are respectively formed of Darlington-connected three-stage transistors Q.sub.3a, Q.sub.3b, and Q.sub.3c to Q.sub.6a, Q.sub.6b, and Q.sub.6c, and Q'.sub.3a, Q'.sub.3b, and Q'.sub.3c to Q'.sub.6a, Q'.sub.6b, and Q'.sub.6c .

Since there are provided the Darlington-connected three-stage transistors, the accuracy of the output current with respect to the input current can be correspondingly improved. However, the three stage configuration causes the minimal operating voltage of the collector to be increased to 3V.sub.BE with respect to the reference potential, so that a voltage compensating circuit 46 is required between the current change-over circuits 2 and 2'.

This voltage compensating circuit 46 will hereinafter be explained.

The voltage compensating circuit 46 comprises a pair of differential switching circuits 35 and 36 which are formed of transistors 37 and 38, and 39 and 40, respectively. The emitters of the transitors 37 and 38 are connected in common, and the connecting point thereof is grounded through a capacitor 42 constituting a low pass filter. In the same manner, the emitters of the transistors 39 and 40 are connected in common, and the connecting point thereof is grounded through a capacitor 43 constituting a low pass filter.

Input terminals 44 and 45, which correspond to the input terminals T.sub.1 and T.sub.2 through which the switching signals E.sub.1 and E.sub.2 are supplied to the current generating circuit 4 at the first stage, are fed with the same switching signals E.sub.1 and E.sub.2, respectively. The switching signal input terminal 44 is connected in common to the bases of the transistors 37 and 40, while the switching signal input terminal 45 is connected in common to the bases of the transistors 38 and 39.

In the current change-over circuit 2 in the current generating circuit 4 a the first stage, the collectors of the transitors Q.sub.3a and Q.sub.5a are connected in common, and the connecting point thereof is connected through the output terminal T.sub.3 to the emitters of the the transistors Q'.sub.1 and Q'.sub.2 of the current dividing circuit 3' in the current generating circuit 4' at the next stage. The collectors of the transitors Q.sub.4a, Q.sub.4b, Q.sub.4c, Q.sub.6a, Q.sub.6b and Q.sub.6c are connected in common to the output terminal T.sub.4. The collector of the transistor Q.sub.3b is connected through the output terminal T.sub.5 to the collector of the transistor Q'.sub.1 of the current dividing circuit 3'. The collector of the transistor Q.sub.5b is connected through the output terminal T.sub.6 to the collector of the transistor Q'.sub.2 of the current dividing circuit 3'. The collector of the transistor Q.sub.3c is connected to the emitters of the respective transistors 37 and 38 of the voltage compensating circuit 46, while the collector of the transistor Q.sub.5c is connected to the emitters of the respective transistors 39 and 40 thereof.

The current change-over circuit 2' in the current generating circuit 4' at the next stage has the collectors of the transistors Q'.sub.3a and Q'.sub.5a connected with each other, and the connecting point thereof is connected, through an output terminal T'.sub.3, commonly to the emitters of the transitors of a current dividing circuit in a current generating circuit (not shown) at the third stage. The collectors of the transistors Q'.sub.4a, Q'.sub.4b, Q'.sub.4c, Q'.sub.6a, Q'.sub.6b and Q'.sub.6c are connected in common to an output terminal T'.sub.4 as well as to the collectors of the transistors 38 and 40 of the voltage compensating circuit 46 through the anode-cathode path of a diode 41. The collector of the transistor Q'.sub.3b is connected to the base of the transistor of the current dividing circuit in the current generating circuit at the third stage through an output terminal T'.sub.5 as well as to the collector of the transistor 37 of the voltage compensating circuit 46. The collector f the transitor Q'.sub.5b is connected through an output terminal T'.sub.6 to the collector of the transistor of the current dividing circuit in the current generating circuit at the third stage as well as to the collector of the transistor 39 of the voltage compensating circuit 46.

Incidentally, the voltage compensating circuit 46 also has a function of averaging currents Ia and Ib which are applied respectively to the collectors of the transistors Q.sub.3c and Q.sub.5c of the current change-over circuit 2 in the current generating circuit 4 at the first stage.

Particularly in the present embodiment, the collector of the transistor Q.sub.3c, the minimal operating voltage of which is 3V.sub.BE with respect to the reference potential, in the current change-over circuit 2 in the current generating circuit 4 at the first stage, is connected to the collector of the transistor Q'.sub.3b of the current change-over circuit 2' in the current generating circuit 4' at the next stage through the emitter-to-collector path of the transistor 37 as well as to the collector of the transistor Q'.sub.4a of the current change-over circuit 2' through the emitter-to-collector path of the transistor 38 and the diode 41. Similarly, the collector of the transistor Q.sub.5c, the minimal operating voltage of which is 3V.sub.BE with respect to the reference potential, constituting the current change-over circuit 2 in the current generating circuit 4 at the first stage, is connected to the collector of the transitor Q'.sub.5b of the current change-over circuit 2' in the current generating circuit 4' at the next stage through the emitter-to-collector path of the transistor 39 in the voltage compensating circuit 46 as well as to the collector of the transistor Q'.sub.4a of the current change-over circuit 2' through the emitter-to-collector path of the transistor 40 and the diode 41.

The rest of the present embodiment is constructed in the same manner as the construction shown in FIG. 9, so that the repeated explanation thereof will be omitted.

According to the construction of the change-over circuit of the present invention as set forth above, as the number of processing bits is increased, the number of transistors which are used to turn on the single current dividing circuit can be further reduced. Accordingly, assuming that the number of processing bits is n, the number of transistors necessary to turn on each of the transistors constituting the current dividing circuit can be reduced from 2.sup.n to n+1, which is greatly effective in constructing a current generating circuit for a highly accurate D/A converter or the like.

Also, since the current generating circuit of the present invention is provided with output terminals arranged in parallel corresponding to the number of the processing bits by connecting a plurality of current generating circuits in a piling manner, the number of the processing bits can be increased in a predetermined stage, thereby making it possible to largely reduce the number of piled stages, the number of elements in the change-over circuit and the operating source voltage.

Particularly, since the current dividing circuit in Darlington configuration according to the present invention can suppress errors in the output current with respect to the input current as well as divide the input current with high accuracy, it is possible to prevent the elevation of the minimal operating voltage when the current dividing circuits are connected in multiple stages.

The above description is given on preferred embodiments of the invention but it will be apparent that many modifications and variations could be effected by one skilled in the art without departing from the spirit or scope of the novel concepts of the invention.