Etching Method for Generating Apertured Openings or Trenches in Layers or Substrates Composed of N-Doped Silicon

The present invention relates generally to the manufacture of semiconductor components. More particularly, the present invention is directed to a method for generating apertured openings or trenches in layers or substrates composed of n-silicon as used in the manufacture of semiconductor components, particularly LSI semiconductor circuits, through masked etching.

One of the most important materials in the creation of microelectronic components is silicon. As such, silicon requires more and more designational and specific methods for surface structuring. One of the more technically difficult areas in the manufacture of semiconductor components is the generation of trenches, or, respectively, holes in the silicon surface.

Heretofore, chemical etching methods or plasma etching methods were typically used for generating, in the silicon surface, hole-shaped or trench-shaped structures. When these methods are utilized, the following difficulties arise:

(a) using isotropic chemical etching (acidic) results in under-etchings that greatly limit the possible etching geometries - this is illustrated in FIG. 1, the under etchings being represented by 10;

(b) when anisotropic chemical etching (alkaline) is used, the plurality of realizable etching geometries is highly limited by the crystal faces - see FIG. 2, wherein the crystal faces are represented by 100 and 111; and

(c) in plasma etching, as may be derived, for example, from a report by Morie et al in IEEE Electron Device Letters, Volume EDL-4, No. 11 (November 1983), pages 411 through 414, for the creation of the trench cells of Mbit memories dimensions below 1 um as well as depth-to-width ratios T/B greater than 10 in holes can only be achieved with great difficulty (see FIG. 3). The rectangular cross-section in Morie is highly dependent on the gas pressure of the reaction gas (tri-fluoro bromomethane).

Accordingly, there is a need for an improved method for generating openings or trenches in silicon surfaces to manufacture semiconductor components.

The present invention provides an improved method for generating holes and trenches in silicon substrates for the manufacture of semiconductor components. To this end, the present invention provides a method that manufactures hole geometries and trenches in a controlled manner with a simple etching method wherein both holes and trenches in silicon are generated with arbitrary cross-sections for microelectronics (diameter less than 1 um and a depth of 10 um) as well as for power component electronics. Further, pursuant to the method of the present invention, it should also be possible to generate fine trenches (perforations) for receiving dopants in the silicon.

As stated above, the present invention provides a method for generating apertured openings or trenches in layers or substrates of n-silicon, as used in the manufacture of semiconductor components through mask etching. To this end, the etching is carried out through an electrolytic etching in an electrolyte containing hydrofluoric acid upon application of a potential that is either constant or chronologically varying. The layer or the substrate composed of silicon is connected as a positively polarized electrode of an electrolysis cell.

In an embodiment, the electrolysis is injected by illuminating the silicon member proceeding from its back side. In a further embodiment, the illumination is maintained in a constant or chronologically varied manner in order to control the etching current on the basis of the formation of minority charge carriers.

In an embodiment, a chemical etching is also performed before and/or after the electrolytic etching. The chemical etching is preferably performed in a caustic potash solution. In an embodiment, a wetting agent is added. In an embodiment, the wetting agent is formaldahyde.

In an embodiment, in addition to the electrolyte contact to be etched, the silicon member can also additionally include an ohmic contact or a further electrolyte contact (contact for the majority charge carriers).

Additional features and advantages of the present invention are described in, and will be apparent from, the detailed description of the presently preferred embodiments and from the drawings.

FIG. 1 illustrates a substrate that has been isotropically etched.

FIG. 2 illustrates a substrate that has been anistropically etched.

FIG. 3 illustrates a substrate that has been etched through plasma etching.

FIG. 4 illustrates the I-V characteristics of a hydrofluoric acid electrolyte n-silicon contact.

FIG. 5 illustrates a schematic of the etching of a hole in the substrate.

FIG. 6 illustrates schematically the etching process in an electrolysis cell.

FIGS. 7-11 illustrate cross-sections of the structure obtained after the etching.

The present invention provides a method for generating apertured openings or trenches in layers or substrates composed of n-silicon, as used in the manufacture of semiconductor components. The method proceeds on the basis of an electrolytic etching carried out in an electrolyte containing hydrofluoric acid, upon the application of a constant or chronologically varying potential. The layer or substrate composed of silicon is connected as a positively polarized electrode of an electrolysis cell. By way of example, the method of the present invention shall be set forth in more detail with reference to the electrolytic etching of a hole in an n-doped silicon.

Referring to FIG. 4, the fundamental I-U characteristic of a hydrofluoric acid electrolyte n-silicon contact is illustrated. Proceeding in the shaded area as an anodic electrode reaction is the divalent dissolving (I<I.sub.PSL) (as used herein, PSL means porous silicon layer; this layer is formed in the anodic region in hydrofluoric acid on p-silicon and n-silicon) of the silicon without formation of an electropolishing surface layer as occurs in the tetravalent dissolution region (I>I.sub.PSL), i.e. the entire, applied voltage drops off over the space charge zone (RLZ). However, an electrical current only flows when minority charge carriers (holes h.sup.+) are present. These can be generated by illumination; the current is thus a function of the incident light.

These specific properties of the nSi electrode, given current densities that are not too great, leads to the build up of small deviations from the ideally smooth surface build up, i.e. a minimal hole or, respectively, an etched trench, that bends the electrical field of the space charge zone in precisely such a fashion that all near h.sup.+ are collected by the hole. Accordingly, the etching is intensified at the floor of the hole. As can be seen from FIG. 5, the hole having a width D collects charge carriers from the region D+2d. After a given time, a system of fine, tightly adjacent holes forms on the basis of the described process. This microscopic honeycomb surface absorbs light to an extremely high degree, i.e., it is macroscopically intense black.

The small deviations can be prescribed by a suitable mask and a pre-etching with, for example, caustic potash solution and, thus, the holes can be localized. Due to the specific shape of the space charge zone, an individual hole will branch out and thus form a tree-like hole structure, whereas a uniform pattern of holes leads to a strictly vertical growth direction due to mutual influencing. The shape and dimension of the holes is highly variable and is dependent on the following parameters:

1. Because of its influence on the space charge zone, the hole arrangement mask has a highly defining effect on the geometry of the holes - branching or linear.

2. The pre-etching with caustic potash solution only improves the small deviations from the ideally smooth surface (nucleus) prescribed by the mask and thus acts only on the shape of the upper edge of the hole.

3. The potential applied between the silicon and reference electrode (voltage) determines the electrical field in the space charge zone and, thus, the wall roughness of the holes (given voltages in the region of the punch-through field strength, the holes are pointed and narrow and the whole wall is greatly disrupted by fine channels (point discharges)).

4. The etching current through the specimen surface is a function of the incident light; it determines the hole width and also influences the punch-through mechanism.

5. The hole depth is approximately proportional to the etching duration.

6. The doping of the substrate determines the expanse and the field in the space charge zone. Generally, it can be said as a scaling rule that the geometrical dimensions of the holes are enlarged by a factor of 2 given a quadrupling of the doping.

7. The influences of the hydrofluoric concentration and of the temperature, although they have not yet been studied in depth, are estimated to be rather slight.

8. An after-etching, for example in caustic potash solution, serves, first, to remove the porous silicon layer (PSL in FIG. 4) forming process-conditioned or, second, in order to connect finely structured channels to form rougher structures, for example, trenches.

Referring to FIG. 6, a schematic of the etching process in an electrolysis cell wherein a specimen holder for implementation of the electrolysis etching is illustrated in cross-section. A silicon crystal wafer 1, composed of n-doped silicon, in whose surface provided with a masking layer the structures (holes or trenches) are to be generated is clamped in a specimen holder 2. The specimen holder 2 is constructed from Teflon that is constructed so that it contains the electrolyte 3 composed of a hydrofluoric acid solution securely in its interior. The silicon crystal wafer 1 is connected to a positive pole 5 of a voltage source (not shown) via an ohmic contact 4. The cooperating electrode 6 (negative pole 7=cathode) is composed of a material that is resistant to hydrofluoric acid, for example platinum.

In order to achieve the required current density, the silicon crystal wafer 1 is illuminated with light of a suitable intensity (see wavy arrow 8) proceeding from the backside. Under these conditions, anodic dissolution at the surface of the silicon crystal wafer 1 not covered with the masking layer (not shown) proceeds given an applied voltage. The depth of the etched trenches or holes is predominately controlled by the etching time.

By way of example, and not limitation, examples of embodiments of the method of the present invention will now be given.

In this example, the method produces holes in memory modules such as, for example, trench cells (see FIG. 7).

Holes having a diameter of 1 um and a depth of 10 um are produced in n-silicon pursuant to the method of the present invention. These holes function to accept the varactor or the varactor and selection transistor of a DRAM (dynamic random access memory). To create the holes, a mask composed, for example, of silicon nitride is applied in conventional technique to an n-doped silicon crystal wafer in a first step. The arrangement of the holes established by the mask is pre-etched for 10 minutes with an alkaline etchant, for example 10% caustic potash solution (see FIG. 2). The silicon crystal wafer is then clamped in an arrangement shown in FIG. 6 or in an arrangement modified for production purposes.

Electrolytic etching in a hydrofluoric acid solution (2.5% by weight) that is laced with a wetting agent based on a formaldehyde (Mirsaol.sup.R, 3 drops per liter) then proceeds under the following parameters (the parameters cited in the following exemplary embodiments are only rough guidelines that must be optimized and chronologically varied dependent upon the application):

The potential between reference electrode and ohmic specimen contact is set at U=1V (positive pole at specimen).

The etching current per hole is 0.1 nA set by illuminating the backside with light, for example, light having a wavelength of 800 nm (current I is chronologically constant or decreasing dependent on the hole shape to be produced).

The duration of the etching t is 20 minutes. The ndoped substrate comprises a doping N.sub.n of 1 Ohm cm and an orientation in (100) - direction.

The etching proceeds at room temperature.

An after-etching for 10 minutes in 1% caustic potash solution proceeds as the last step for removing the porous silicon layer (referenced PSL in FIG. 4) that forms during etching.

Pursuant to the method of this example, deep, vertical dopings (potentially through the entire thickness of the silicon crystal wafer) are produced given a slight horizontal doping depth (see FIG. 8), as well as the manufacture of large-area capacitors or pn-junctions (for example, for controllable, high capacitance capacitors (Varicaps)) in small volumes.

The pre-treatment and after-treatment in caustic potash solution ensues as set forth in the first exemplary embodiment; analogous values apply for the concentration of the electrolyte and for the illumination.

The potential between reference electrode and ohmic specimen contact is set at U=2V, the etching current I is set at 1nA, the etching time t is set at 100 minutes, and the doping is set at a range from approximately 0.1 to about 1 Ohm cm.

The subsequent doping (see dot-dash line in FIG. 8) proceeds via conventional technique.

Pursuant to the method of this example, deep, narrow trenches for electrical insulation of regions A and B (see FIG. 9) in a silicon substrate are produced.

The same parameters as set forth in exemplary embodiments 1 and 2 are used, with the exception that:

The potential between the reference electrode and ohmic specimen contact is set at U=20V, the etching current I is set at 1 nA, and the etching time t is set at 100 minutes. The doping N.sub.n lies between approximately 1 to about 100 Ohm cm.

The after-etching in caustic potash solution is intensified in order to connect the individual holes prescribed by the mask to form a closed trench. This proceeds either on the basis of a longer etching time and/or on the basis of higher concentrations and/or on the basis of a higher temperature of the KOH solution.

Pursuant to the method of the present invention, in this example, contacting of more deeply disposed layers is created. For example, for the fast elimination of charge carriers in disconnectable (GTO=gate turn off) thyristors (see FIG. 10).

The same parameters as set forth in the exemplary embodiments 1 through 3 are utilized except that:

The potential between the reference electrode and ohmic specimen contact is set at U=2V, the etching current I is set at approximately 1 to about 100 nA, and the etching time t is set at 100 minutes. The doping N.sub.n lies between approximately 1 to about 100 Ohm cm. Minority charge carriers present in the pregion are removed by the etched and potentially metallized channels.

The letters A, K, and G indicate the anode, cathode, and the gate of the thyristors, respectively.

In the method of this example, voltage-controlled thyristors (see FIG. 11) are produced.

The same parameters as set forth in exemplary embodiments 1 through 4 were utilized with the exception that: the potential between the reference electrode and ohmic contact is set at U=2V, the etching time is set at 100 minutes, and the doping N.sub.n is set between approximately 10 to about 100 Ohm cm. After two/thirds of the etching time, a boost of the etching current I in the range of from 1 to about 100 nA proceeds by a factor of 2 through 10, whereby hole widening is achieved.

The current between the anode A and cathode K of the component is controlled by the voltage-dependent enlargement of the space charge zone around the holes. G references the gate terminals.

It should be understood that various changes and modifications to the presently preferred embodiments described herein will be apparent to those skilled in the art. Such changes and modifications can be made without departing from the spirit and scope of the present invention and without diminishing its attendant advantages. It is therefore intended that such changes and modifications be covered by the appended claims.