Apparatus for Playback of Magnetically Recorded Data Having a Variable Input Rate

FIG. 1 is a simplified block diagram of the preferred embodiment of the invention.

FIG. 2 is a block diagram of a phase locked loop utilized in the playback synchronizing generator circuit in accordance with the preferred embodiment.

FIGS. 3A to 3C are consecutive portions of a detailed schematic circuit diagram depicting the playback synchronizing generator of FIG. 1.

FIGS. 4A to 4C are consecutive portions of a detailed schematic circuit diagram corresponding to the write control and data output memory circuits of FIG. 1.

FIG. 5 is a detailed schematic circuit diagram showing the read control circuit of FIG. 1.

Throughout the description and in all drawing figures like reference numerals are utilized to designate like circuit elements to facilitate comparison.

FIG. 1 shows a simplified block diagram of the preferred embodiment of the invention, which will be described below. In the preferred embodiment a conventional helical scan playback device is utilized, having a rotating scanner drum 10, which may have mounted thereon one or more equally spaced rotating playback transducers, of which only one transducer 12 is shown for simplicity. The playback data from transducer 12 is received in the form of data blocks. The length of the data blocks is equal and fixed for all recording operations and independent of the input data rate. In the preferred embodiment each block contains 6 kilobytes of data. The input data rate prior to recording may vary in a range of 1:100 or more. However, during each particular recording operation the input data rate remains constant. With respect to the variable input data rate, at lower data rates, for example 1 MHz, the spacing between adjacent data blocks is relatively large comparing to high data rates, for example 100 MHz, when the blocks are spaced much closer together. To maintain synchronization of data during the recording and playback operation, preferably zero bits are inserted between consecutive data blocks prior to recording, utilizing well known bit stuffing techniques. The number of inserted bits depends on the actual rate at which the input data has been received. In accordance with the system of the invention, during a particular playback operation the output data rate remains constant and substantially corresponds to the original input data rate, so that the output data flow can be maintained uninterrupted, as it will follow from further description.

Prior to recording of data, a synchronozing word, further referred to as beginning of data (BOD) marker, is attached immediately preceding the beginning of each data block. There is also a marker at the end of each data block. In the preferred embodiment the BOD marker is 24 bytes long, where all the bits in a particular byte are of the same kind, that is, all ones or all zeroes.

With further reference to FIG. 1, the playback signal from the transducer 12 is applied to a playback amplifier 13, and the amplified signal therefrom to a time base correction (TBC) circuit 14. The time base corrected signal on line 16 is applied to an error correction circuit (ECC) 18. Because the circuits 13, 14 and 18 are of conventional design and well known in the art, a detailed description thereof will not be provided. The corrected signal on line 19 is applied in the form of parallel data bytes to a beginning of data (BOD) correlator 20. The correlator, which may be of a conventional design, operates as follows. It compares sequentially the consecutive bytes of data received on line 19 with the known 24-bit pattern of the BOD marker. The correlation is a sum corresponding to the number of matching data bytes with the BOD pattern. The thusly obtained sum is compared with a predetermined threshold number. When the sum is equal to or exceeds the threshold number, it is an indication that a valid BOD marker has been detected, and thus the beginning of a data block. Simultaneously with the detection, the BOD correlator 20 applies a control signal on line 30 to a memory write control circuit 34. In response to the control signal on line 30, the write control 34 applies via line 42 a series of write clock signals to a playback data output memory 36, whereby the following data block is sequentially written into the memory via line 19 at a write clock rate which is determined by the data transfer clock rate on line 28, as it will follow from further description. In addition, at the occurrence of the control signal on line 30 the memory write control 34 starts to count the number of data bytes written to the memory. When the count reaches 6000, indicating that a full data block has been written into the memory, the write control 34 stops generating write clocks.

In the preferred embodiment the memory 36 is implemented as a first-in, first-out (FIFO) type of memory. The memory write control 34 receives the internal data transfer clock on line 28, provided by a playback synchronizing (sync) system generator 45. In the preferred embodiment the clock on line 28 has a nominal frequency of 13.6 MHz. The previously indicated signal for controlling the rotational speed of the scanner 10 is derived from the internal clock as follows. That clock is divided by a frequency divider within the generator 45, which divider which in the preferred embodiment has a fixed dividing ratio of 1863. The resulting frequency divided signal on line 57 has a nominal frequency of 7300 Hz, and is applied on line 57 to a conventional servo circuit (not shown) for controlling the rotational speed of the scanner. Upon receiving the control signal on line 30 indicating presence of a BOD marker in the playback signal, the data is written into the memory 36 via line 19 at the write clock rate which is equal to the internal clock rate 13.6 MHz on line 28. In the preferred embodiment the FIFO memory 36 has a capacity of 12 kilobytes, and it is 9 bits wide. The data is written into the memory byte-wise via line 19, and it is being simultaneously and sequentially read out byte-wise on 8 parallel lines 38 at a constant read clock rate. Timing of the data output from the FIFO memory 36 is controlled via line 39 by a read control circuit 40, as it will be described below. To prevent overflow or underflow of the memory 36, while utilizing a constant data output clock rate, the average rate of data in and out of memory 36 must be the same. Consequently, the average amount of data written into the memory and read therefrom must be equal. Therefore, data from a following data block must be clocked into the memory, while the previous data block is clocked out therefrom. In the preferred embodiment by the time half of a particular data block has been taken out from the memory 36, the next block must be present and ready to be entered therein.

In the embodiment of FIG. 1 the memory 36 is maintained on the average at a half full level as follows. It is noted that in the preferred embodiment by "half-full" level an average amount of 3000 bytes of data in the memory is understood. That amount corresponds to one half of the size of a data block, which in this example is equal to 6000 bytes. Simultaneously with providing the memory write clocks for the 3000-th byte of a data block, the write control 34 inserts a middle of data (MOD) marker as a control bit via line 35 into the memory 36, as the 9-th bit of that byte. The 3000-th byte is thereby flagged as the middle of the data block, when that byte is written in the memory. When that same byte is read out from the memory 36, it applies the previously described memory status signal in the form of the MOD status on line 41 to the write control 34. The write control 34 provides a time comparison between the respective occurrences of the BOD marker and MOD status signals. In an ideal situation, when the memory 36 is precisely at a half full level, both control signals on lines 30 and 41 coincide. However, when the MOD status occurs before the BOD marker, it indicates that the data on line 19 is received at a slower than optimum rate, with reference to the output data rate, and if the situation remains uncorrected, the memory 36 will be allowed to gradually become empty. Consequently, the output data flow on line 38 would be interrupted. In another situation when the BOD marker occurs before the MOD status, it indicates that the data on line 19 is received at a faster than optimum rate. In this case, when the BOD marker occurs on line 30, the memory did not yet output the first half of the previous data block when the following data block is ready to be written into the memory. When this situation is not corrected, the memory contents will gradually overflow and data will be lost. The system in accordance with the present invention responds to either situation by slightly increasing or decreasing the internal data transfer clock rate, and synchronously therewith the rotational speed of the scanner drum during playback, thereby accelerating or decelerating the rate of receiving the off-tape playback data on line 19. The foregoing is obtained by utilizing a self-adjusting phase locked loop in the playback synchronizing generator circuit 45. That playback loop increases or decreases the frequency of the internal system clock on line 28, and thereby also the frequency of the control signal-on line 57, which is applied to the scanner servo (not shown) to control the rotational speed of the scanner 10. The phase locked loop circuit will be described in more detail with reference to FIG. 2.

Now the manner of providing the output clock signal on line 59 will be described. With further reference to FIG. 1, the previously mentioned input data rate, which has been measured, encoded and recorded on tape is played back and decoded in a conventional manner. That decoded data rate is applied by the TBC circuit on line 58 to a commercially available microprocessor 60, for example type Z80A, manufactured by Zilog Corporation. The microprocessor receives that signal and programs the frequency synthesizer 64 via line 62 to provide the previously described output clock signal on line 59, having a frequency equal to the original input data rate. As it is well known, the frequency synthesizer is a stable, programmable clock signal source. The frequency synthesizer utilized in the preferred embodiment is a commercial device, for example type VDS-1700-8, manufactured by Scitel Corporation. To assure that the rotational speed of the scanner is tightly controlled within limits which do not differ substantially from its nominal speed, the output clock rate on line 59 is programmed to be within 0.06 percent or less of the original input data rate.

The signal on line 59 is applied to the read control circuit 40, which in response thereto applies on line 39 a read clock signal to the memory 36, synchronously with the signal on line 59. Once the frequency of the clock signal on line 59 is determined for a particular playback operation, it is set and maintained constant and stable until the next playback operation, when a different frequency may be determined. In the preferred embodiment the frequency synthesizer may be programmed to vary the output clock rate within the previously described wide range of frequencies 1:100. It follows from the foregoing description that the data is clocked out from the memory 36 on line 38 at a rate determined by the read clock signal on line 39 in synchronism with the output clock rate on line 59. To start the data readout from memory 36, the write control 34 enables the read control circuit 40 via line 172 when a sufficient amount of valid data is present in the memory.

The playback sync generator 45 comprises a self-adjusting phase locked loop (PLL) for adjusting the internal data transfer clock on line 28, and thereby also the memory write clock on line 35, as well as the rotational speed of the scanner 10, in turn preventing the memory 36 from overflow or underflow. The PLL in accordance with the preferred embodiment of the invention is shown in FIG. 2 and will be now described.

As it has been previously indicated, and with further reference to FIG. 2, the playback sync generator 45 generates the internal data transfer clock on line 28 from which there is derived the scanner rotation control signal on line 57, synchronous therewith. The self-adjusting phase locked loop of FIG. 2 comprises a fixed frequency oscillator 37, which in the preferred embodiment generates a 13.6 MHz stable reference signal on line 43, corresponding to the nominal data transfer rate. The signal on line 43 is divided by a first frequency divider by N 46, which in the preferred embodiment is set to a nominal N=1863. The signal on line 44 from the divider 46 is applied to one input of a phase comparator 47. An output signal from the phase comparator 47 is applied via line 53 to an amplifier 50, and the amplified signal therefrom is applied on line 51 to control an output signal frequency from a voltage controlled oscillator (VCO) 48, applied on line 54. In the preferred embodiment the nominal output voltage frequency from VCO 48 is 27.2 MHz. That signal is further frequency divided by 2 in divider 55, and the resulting 13.6 MHz nominal frequency signal on line 28 is the previously described clock signal generated by the playback sync generator 45.

The signal on line 28 is also frequency divided by a second frequency divider by M 49. In the embodiment of FIG. 2 the dividing ratio is fixed and is M=1863. The thusly frequency divided signal on line 52 is applied to a second input of the phase comparator 47. The phase comparator compares the respective phases of the signals on lines 44 and 52, and the previously described output signal therefrom corresponds to the resulting phase difference, which in turn is applied to increase or decrease the output signal frequency from VCO 48 on line 54. The frequency divided signal on line 52 is buffered by a buffer 25 and the output signal there from on line 57 is applied to control the scanner rotation as it has been previously described with reference to FIG. 1.

In accordance with the invention, the dividing ratio N of divider 46 is adjustable by a control signal on line 56, applied from the write control 34 of FIG. 1, which signal corresponds to the time difference between the respective occurrences of the BOD marker and MOD status control signals on lines 30 and 41, respectively, as it has been described previously with reference to FIG. 1. Consequently, when the timing error signal on line 56 indicates that the MOD status signal occurred before the BOD signal, the signal on line 56 will decrease the dividing ratio N. As a result, the signal on line 53 from the phase comparator will slightly increase the output frequency of the VCO 48, and the internal transfer clock rate will increase, causing the scanner to accelerate, in turn increasing the rate of the data written into the memory 36 via line 19 of FIG. 1. In an opposite situation when the MOD status occurs after the BOD marker, the control signal on line 56 will increase N and the output signal frequency from VCO 48 will slightly decrease. Consequently, the internal data transfer clock rate will decrease, and the scanner rotation will decelerate, in turn resulting in a lower playback data rate on line 19 of FIG. 1. In the preferred embodiment the value of N changes only slightly by integers +1, -1, +2, or -2, that is between values 1861 and 1865, and only for a predetermined time period, to prevent abrupt changes in the data transfer rate in either direction.

A more detailed description of the preferred embodiment follow with reference to the schematic circuit diagram of FIGS. 3A to 3C, 4A to 4C, and 5, corresponding to portions of the above-described block diagram of FIG. 1. To provide a more complete disclosure, the integrated and other circuit components shown in the detailed diagram are designated by part numbers commonly used by manufacturers.

FIGS. 3A to 3C show a detailed circuit diagram corresponding to the previously described phase locked loop of FIG. 2. As it is seen from these Figures, the frequency dividers 46, 49, are preferably implemented by three 4-bit counters each.

FIGS. 4A and 4B show the write control circuit 34, which in the preferred embodiment is implemented by programmable array logic (PLA) circuits 110 to 113, D-type flip-flops 114, 115, and up/down counter 116. PLA circuits 110 to 112 are interconnected with each-other and operate as a single unit, as it will be described below. The PLA circuits receive on line 124 from the TBC circuit 14 of FIG. 1 a signal indicating that the TBC circuit is in locked condition and thus it supplies valid data. That signal is clocked into PLA's at a data byte transfer clock frequency equal to 13.6 MHz. During start-up, PLA circuits 110 to 112 receive on line 133 a control signal from the microprocessor 60 of FIG. 1, indicating that the frequency synthesizer 64 shown in FIG. 1 has been programmed via line 62 to a desired output clock frequency on line 59.

On line 125 a high threshold (HT) BOD marker, and on line 126 a low threshold (LT) BOD marker are applied to the PLA circuits 110 to 112 from the BOD correlator 20 of FIG. 1, where lines 125, 126 correspond to line 30 of FIG. 1. In the preferred embodiment during start-up of the playback operation, that is for example when the write control circuit is reset via line 119, shown in FIG. 4C, it is necessary that a BOD marker which has no errors therein is first detected by the correlator 20. For that purpose the correlator utilizes a so called high threshold for the correlation, which does not allow for any bit errors, to assure that the beginning of the data block has been accurately detected. However once a high threshold BOD marker has been found, the correlator 20 utilizes thereafter a low threshold which allows for some bit errors in the BOD marker, so that data blocks will not be missed during normal operation when errors in the marker may occur. In case error correction is not utilized, there is a possibility that the BOD marker may be not found due to a high number of bit errors, even when the low threshold is utilized. To prevent the memory from becoming empty, the PLA circuits 110 to 112 are programmed to predict occurrence of a BOD marker as follows. An outside counter (not shown), connected via line 127 counts a predetermined number of clock cycles. In the preferred embodiment it counts to a terminal count selected greater than 6000. The counter is normally reset at the occurrence of the BOD marker. When the BOD marker does not occur during that count, the terminal count is applied as an alternate (ALT) BOD marker on line 131 and applied to the PLA circuits.

Upon receiving a control signal on one of the lines 125, 126 or 127, indicating beginning of a data block, the PLA circuits 110 to 112 start to count the number of data bytes entering the FIFO memory 36 on line 19, as it is shown in FIG. 4C. Simultaneously, the PLA circuits provide the previously described write clocks on line 42 to the FIFO memory 36 of FIG. 4C, thereby enabling to store consecutive data blocks in the memory. Line 130 is an internal connection between the PLA's 110 to 112 carrying the byte count. At a count corresponding to one half of the data block, that is at 3000, the previously described MOD marker is written into the memory 36 via line 35 as the ninth bit attached to the byte occurring in the middle of the data block, that is at the 3000 count. When that MOD marker is read out from the memory 36 on line 41, it is delayed by the flip-flops 114, 115, shown in FIG. 4B, and thereafter applied to PLA 113 via line 41a. In response to the signal on line 41a, PLA 113 applies a load control signal on line 41b to up/down counter 116, which counter in turn loads the count provided by PLA 110 on line 156. That count corresponds to the amount of time measured in internal system clock cycles, between the occurrence of the BOD signal on line 30 and MOD signal on line 41. Depending on the magnitude and direction of the difference, the direction being determined from the sequence in which these signals occurred, the counter 116 applies a count, corresponding to the error correction signal on line 56, to the frequency divider 46 of FIG. 3B, which in turn changes the division ratio N of the divider by +1, +2, -1 or -2 as it has been previously described. The count is applied synchronously with the occurrence of the MOD marker and it is cleared via line 136 from PLA 113. PLA 113 is programmed to apply the clear signal after a fixed number of clock cycles. The foregoing adjustment of the divisor N corresponds to a 0.05 percent or 0.1 percent frequency adjustment of the clock signal on line 28. When the counter 116 is cleared, the error correction signal on line 56 returns to its nominal value. By the foregoing, the adjustment of the divisor N is limited to be within the previously described integer values of 1861 to 1865, thereby preventing the scanner from accelerating or decelerating for a longer period of time than necessary to prevent overshoot or undershoot.

With further reference to FIG. 4C, it shows the playback data output memory circuit 36, comprising respective data latches 141 to 143 coupled to respective FIFO memories 147 to 149. The data block in the form of parallel data bytes is received on line 19 from the error correction circuit 18 of FIG. 1. The data is applied to the data latches 141 to 143, at write clock rates applied on line 42 by the PLA circuits 110 to 112 of FIG. 4A. In response to the write clock on line 42 the data from each latch 141 to 143 is written into a respective FIFO memory 147 to 149. The data from these FIFO memories is read out on lines 38 at a rate determined by the previously described read clock signal on line 39. Each respective FIFO memory 147 to 149 indicates on one of the lines 151 to 153 when it becomes full, and on one of the lines 161 to 163 when it becomes empty. When any of the signals on lines 151 t 153, or 161 to 163 occurs, indicating memory overflow or underflow, it is applied to the PLA circuits 110 to 112, which in turn initiate a new start-up process.

Now the operation of the read control circuit 40 of FIG. 1 will be described in more detail with reference to FIG. 5. In the preferred embodiment shown in FIG. 5 the read control circuit comprises a programmable logic array (PLA) 140, which receives on line 171 a power on reset signal from a conventional power control circuit (not shown). During start-up operation, the PLA 140 receives on line 172 the previously described control signal which enables reading of the output data from memory circuit 36 of FIG. 4C by applying the previously described read signals on line 39 from the read controller 140. The previously described accurate output clock signals provided by the frequency synthesizer 64 of FIG. 1 are applied on line 59 to PLA circuit 140. The PLA circuit 140 is programmed to apply, in response to the signal on line 59, accurately timed read clocks on line 39 to the respective FIFO's 147 to 149 of FIG. 4C. In response to these read clock signals the output data from the respective FIFO's is read out in the proper sequence on line 38.

It will be apparent to those skilled in the art that numerous modifications can be made to the embodiment described herein without departing from the scope of the invention. All such modifications are intended to be included within the scope of the claims appended hereto.