Method and Apparatus for Jitter Correction of a Polygon Mirror in an Image Recording Apparatus

1. Field of the Invention

The present invention relates to a method of and an apparatus for jitter correction of a polygon mirror in order to reduce dot misregistration in scanning lines caused by rotational errors of the polygon mirror in an image recording apparatus such as a flat scanning type facsimile or electronic process scanner, and for performing image recording by scanning recording beams modulated in response to variable density levels (including black and white) of respective dots in synchronization with dot recording clock signals by a polygon mirror on a photosensitive material such as a photographic paper or a film.

2. Description of the Prior Art

In a flat scanning type image recording apparatus employing laser beams as recording beams, a polygon mirror is generally used as a scanning deflector for the laser beams. However, the polygon mirror inevitably creates rotational errors whereby scanning lengths vary with respective reflecting mirror surfaces of the polygon mirror to cause dot misregistration in scanning lines, as shown in FIG. 1. Although the start positions of respective scanning lines are substantially registered or even in the figure, dot misregistration or unevenness by a distance corresponding to 1/2 dot occurs as compared to a correct scanning length L in the end position of the second scanning line. Such dot misregistration deteriorates the picture quality of the recorded image. Particularly, an electronic process scanner for duplicating halftone images is adapted to record regular halftone images (halftone dot patterns), and hence misregistration of even 1/2 dot significantly deteriorates the picture quality.

In general, dot misregistration in scanning lines caused by rotational errors of a polygon mirror has been corrected as follows.

A first method employs grating (linear encoding). In this method, a grating laser is assembled in the same optical system with a recording laser. These laser beams are deflected by a polygon mirror that performs exposure recording/scanning by the recording laser beam while grate scanning the grating laser beam to obtain pulse signals indicating positions of the recording laser beam. Dot misregistration in the respective scanning lines is eliminated by creating dot recording clock signals synchronous with the pulse signals through a synchronous control circuit such as a PLL circuit. Although dot misregistration is eliminated by this method, the optical system is complicated since the grating laser beam is assembled in the optical system. Adjustment is complicated and the PLL circuit is increased in cost when high resolution and high frequency are required.

In a second method, a crystal oscillator is combined with a start sensor. This method employs a polygon mirror of high accuracy as a deflector with a reference clock signal generated by the crystal oscillator creating a plurality of clock signals by delaying the reference clock signal by appropriate times, synchronizing the clock signal with a recording laser beam and start sensor in order to process the same as a dot recording clock signal in the corresponding scanning line, and thereby to register the start positions of respective scanning lines. A main scanning synchronous system in this method is simple in structure and hence the same can be relatively easily adjusted, and manufactured at a relatively low cost. In this method, however, the polygon mirror is inherently inferior in accuracy to the crystal oscillator and the start sensor. Thus, although the respective scanning lines substantially coincide in timing with each other without dot misregistration immediately after starting, dot misregistration is inevitably caused by slight rotational errors of the polygon mirror in the vicinity of the end positions, causing terminating ends of the scanning lines to be irregularized. Even when a polygon mirror of higher accuracy is attained in order to prevent this irregularization, such attempts are restricted by both cost and technical limitations.

A third method is adapted to modulate the frequency of a dot recording clock signal in response to rotational errors. This method analogously obtains voltage responsive to the rotational speed of the polygon mirror to perform voltage-frequency (V-F) conversion of the same in order to generate the dot recording clock signal, while digitally generating a reference clock signal to frequency-divide the reference clock signal in a frequency dividing ratio responsive to the rotational speed of the polygon mirror, thereby generating the dot recording clock signal. However, this method requires voltage ratio values of high accuracy, and selection. When the wanted frequency is finely changed in the latter method adjustment of the frequency is difficult.

The present invention is directed to a method of and an apparatus for jitter correction of a polygon mirror for a scanning recording beam modulated in synchronization with a dot recording clock signal on a photosensitive material performing image recording.

According to the present invention, a start sensor for detecting a recording beam in advance to scanning of one scanning line and an end sensor for detecting passage of the recording beam upon completion of scanning of one scanning line are provided while N dot recording clock signals obtained by delaying a dot recording clock signal of a cycle t by t/N are previously prepared.

In a first mode of the present invention, an interval between detecting times when the beam cross the two sensors is counted in time resolution t/N every one surface of a polygon mirror to obtain the difference between the count value and a prescribed reference count value as a resulting clock crossover number; a sign of the difference as a crossover phase direction, and one of the N dot recording clock signals is selected in synchronization with detection output of the start sensor for every surface of the polygon mirror, thereby to perform image recording by a crossover dot recording clock signal obtained by performing crossover from the selected dot recording clock signal to dot recording clock signals adjacent in phase sequentially in the crossover phase direction by the crossover number.

In other words, the first mode employs the aforementioned second conventional method for registering start positions of respective main scanning lines but eliminates dot misregistration of the scanning lines caused by rotational errors of the polygon mirror by performing crossover operation of the N dot recording clock signals delayed by t/N number of times responsive to the amount of dot misregistration during scanning of one scanning line.

In a second mode of the present invention, a detection time interval between the start sensor and the end sensor is counted in time resolution t/N through the N dot recording clock signals to obtain rotational error times for respective surfaces of the polygon mirror thereby performing image recording by dot recording clock signals phase-shifted in a direction for reducing dot misregistration caused by the errors by a period about half the respective error times with respect to respective surfaces.

Hence, in the second mode, the amounts of dot misregistration in the scanning lines caused by rotational errors of the polygon mirror are suppressed to about one half of maximum and disperses the amounts over the entire set of scanning lines (particularly in the vicinity of both ends) thereby reducing the overall misregistration.

Accordingly, an object of the present invention is to overcome the aforementioned problems of the prior art and provide a method of and an apparatus for jitter correction of a polygon mirror, which can substantially eliminate or reduce dot misregistration of scanning lines caused by rotational errors of the polygon mirror in simple structure, without providing grating technique or a synchronous control circuit and without requiring a polygon mirror of high accuracy.

These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.

FIG. 1 illustrates the result of dot misregistration in a conventional method;

FIG. 2 is an explanatory diagram showing the basic concept of a first embodiment of the present invention;

FIG. 3 illustrates relation between one dot and delayed dot recording clock signals;

FIG. 4 is an explanatory diagram of crossover of dot recording clock signals;

FIG. 5 is a block diagram showing the first embodiment of the present invention;

FIG. 6 is a block diagram for creating a crossover dot recording clock signal;

FIG. 7 is an explanatory diagram of detection of the amounts of dot misregistration;

FIG. 8 shows another block diagram for creating the crossover dot recording clock signal;

FIG. 9 is a block diagram showing an example of a frequency divider/delay circuit;

FIG. 10 is a signal waveform diagram showing the operation thereof;

FIG. 11 illustrates a modification of the example shown in FIG. 8;

FIG. 12 is an explanatory diagram showing the basic concept of correction according to a second embodiment of the present invention;

FIG. 13 is a block diagram for generating dot recording clock signals responsive to rotational errors of a polygon mirror;

FIG. 14 illustrates the relation between one dot and delayed clock signals;

FIG. 15 is an explanatory diagram showing the manner of obtaining the scanning interval between a start sensor and an end sensor; and

FIG. 16 illustrates the result of correction according to the present invention.

With reference to FIG. 2, description is now set forth according to a first embodiment of the present invention. FIG. 2(A) shows a dot train formed on a standard scanning line with no dot misregistration and a dot recording clock signal for forming the dot train, on the assumption that one scanning line of standard scanning length L is formed by 12 dots (for convenience of illustration). On the other hand, FIG. 2(B) shows the case where the average rotational speed on a reflecting mirror surface is delayed by approximately 2.5% (1/40) with respect to the standard level, by a rotation error of a polygon mirror or the like and dot misregistration of (d/10).times.3 is caused at the terminating end of the scanning line. The start position of the scanning line is correct by employment of, e.g., the aforementioned second conventional method. Both of the cases of FIGS. 2(A) and 2(B) require the same time for 12 cycles of the dot recording clock signals, whereas the scanning length in the said time is shorter than the standard scanning length L in the case of FIG. 2(B) as the result of delay in scanning speed. Symbol d denotes a standard dot diameter. Although the dot diameter is illustrated as equal to a dot interval, the dot diameter d is generally larger than the dot interval for exposure/recording. The following description is made on the assumption that the dot diameter is equal to the dot interval. In the case of FIG. 2(B), dot misregistration of d/10 is caused every four dots of the dot train, and the dot misregistration at the 12-th dot in the terminating end of the scanning line is (d/10).times.3.

FIG. 2(C) shows a case where crossover correction according to the present invention is performed in scanning of FIG. 2(B) to eliminate the dot misregistration. In order to perform such crossover correction, N dot recording clock signals .phi..sub.1 to .phi..sub.N are previously prepared in the present invention by equally dividing the period t of a reference dot recording clock signal .phi..sub.1 into N to delay the same by 1/N as shown in FIG. 3. FIG. 3 illustrates an example in the case of N=10. As hereinafter described, time resolution adjustable by crossover correction of these dot recording clock signals .phi..sub.1 to .phi..sub.N is t/N, and length resolution is d/N (in case of standard scanning speed).

FIG. 4 is an explanatory diagram showing crossover correction of the dot recording clock signals. In this case, crossover is performed from a dot recording clock signal .phi..sub.K within the N signals to a phase-lagging dot recording clock signal .phi..sub.K+1 adjacent to .phi..sub.K in timing as shown by an arrow in the figure, to obtain a crossover dot recording clock signal .phi..sub.X. In the cycle where crossover of the crossover dot recording clock signal .phi..sub.X is performed, the pulse time width is lengthened by t/N, whereby the dot diameter formed in the cycle is larger by d/N than the standard diameter. Thus, as compared with the scanning length only by the dot recording clock signal .phi..sub.K, the scanning length by the crossover dot recording clock signal .phi..sub.X obtained by crossover of .phi..sub.K to .phi..sub.K+1 is large by d/N. When crossover is performed toward a phase-leading side as .phi..sub.K to .phi..sub.K-1 to the contrary, the scanning length is shorter by d/N. Thus, the scanning length can be adjusted in a multiple of d/N by performing a plurality of times of crossover in a scanning interval for one scanning line.

Referring again to FIG. 2, it is assumed that scanning causing the dot misregistration of FIG. 2(B) is performed in synchronization with .phi..sub.3 within previously prepared ten dot recording clock signals .phi..sub.1 to .phi..sub.10. In the crossover correction of the present invention shown in FIG. 2(C), operation is started from the dot recording clock signal .phi..sub.3 for performing crossover of the dot recording clock signals sequentially in the phase lag direction as .phi..sub.3 .fwdarw..phi..sub.4 .fwdarw..phi..sub.5 .fwdarw..phi..sub.6 three times before completion of scanning in order to create the crossover dot recording clock signal .phi..sub.X, and thereby perform scanning synchronously with the same. Namely, adjustment is so performed that the scanning length is lengthened by d/10 per cycle of the crossover shown by arrows in the figure, whereby the dot misregistration of (d/10).times.3 caused in the case of FIG. 2(B) is completely eliminated at the terminating end of the scanning line. Further, adjustment of the dot misregistration is uniformly dispersed over one scanning line, whereby no unnaturalness is caused in the dot train thus obtained.

FIG. 5 is a block diagram showing an embodiment of the present invention for performing the aforementioned crossover correction. Referring to FIG. 5, a film feed roller 1 is rotatingly driven by a subscanning motor 2, whereby a film 3 serving as a recording photosensitive material is fed in a subscanning direction shown by an arrow in the figure. An image processing circuit 4 processes image signals obtained from an input apparatus or the like to output dot signals indicating variable density (including black and white) of respective dots to a semiconductor laser 5 in synchronization with crossover dot recording clock signals internally generated according to the described embodiment. The semiconductor laser 5 outputs a laser beam responsive to the dot signals as received. The laser beam divergently outputted from the semiconductor laser 5 is changed into parallel beam by a collimator lens 6 and corrected by a cylindrical lens 7, in order to be irradiated on reflecting mirror surfaces of a hexahedral polygon mirror 8.

The polygon mirror 8 comprises a hexahedral rotation mirror for reflecting and deflecting the laser beam, to scan one line of a dot train by one reflecting mirror surface. The laser beam reflected and deflected by the polygon mirror 8 is scanned in the main scanning direction on the film 3 through an f .theta. lens 9 and a cylindrical lens 10. The f .theta. lens 9 is adapted to obtain light collecting points in the same size regardless of positions of the laser beam on the scanning lines so that the spot of the collected light is moved by a certain distance when the polygon mirror is rotated by a certain angle, i.e., to enable scanning on the scanning lines at a constant speed. The cylindrical lens 10 is adapted to perform straightening correction of the laser beams in a subscanning direction similarly to the cylindrical lens 7, which are adapted to compensate straightening errors of the polygon mirror 8 in industrial processing.

A reflecting mirror 11 and a start sensor 12 formed by an optical detector such as a photodiode are provided immediately in front of a main scanning start position in order to detect passage of the laser beam in advance of scanning one scanning line. A reflecting mirror 13 and an end sensor 14 similar to the start sensor 12 are provided immediately at the back of a main scanning end position in order to detect passage of the laser beam after completion of scanning of one scanning line. Detection signals from the sensors 12 and 14 are input to the image processing circuit 4.

Even if the start positions of respective scanning lines are registered or regularized by the start sensor 12 as hereinabove described with reference to the second conventional method, dot misregistration can be caused by the rotational error of the polygon mirror 8 at the terminating end of each scanning line as hereinabove described with reference to FIG. 2(B). The amount of possible dot misregistration at the terminating end of the scanning line is expressed as follows:

where symbol L indicates the scanning length and symbol J indicates a rotational error (speed regulation). Assuming that, for example, L=200 mm for main-scanning a shorter edge of A4 size and J=0.02% as the rotational error of a commercially available polygon mirror, the amount of dot misregistration at the terminating end of the scanning line is expressed as follows:

Assuming that recording resolution is 1270 lines/inch (diameter d of one dot=20 .mu.m), the ratio of the amount of dot misregistration to one dot is as follows:

When misregistration of two dots is caused, linear edges of a recorded image are irregularized to the point of being useless as a line original or a halftone plate. Picture quality is considerably deteriorated for images other than half tone plates.

In the embodiment shown in FIG. 5, therefore, image processing circuit 4 generates N dot recording clock signals .phi..sub.1 to .phi..sub.N shown in FIG. 3 in synchronization with the detection output of the start sensor 12 (i.e., to regularize the start positions of the respective scanning lines) while creating the crossover dot recording clock signals .phi..sub.X obtained by starting operation from the selected dot recording clock signal in order to perform crossover correction by a number of times responsive to the amount of dot misregistration. Thus, the start positions of the respective scanning lines are registered or regularized and the dot misregistration at the terminating ends of the scanning lines can be substantially eliminated.

FIG. 6 is a block diagram showing an exemplary circuit for generating the aforementioned crossover dot recording clock signal .phi..sub.X in the image processing circuit 4. A reference dot recording clock signal is generated by a clock generator 15 such as a crystal oscillator and passed through a delay circuit 16, to create the N dot recording clock signals .phi..sub.1 to .phi..sub.N by equally dividing the cycle t of the reference dot recording clock signal into N and delaying the same by t/N. Dot recording clock signals .phi..sub.1 to .phi..sub.N are employed for creating the crossover dot recording clock signal .phi..sub.X, as well as for detecting the amounts of dot misregistration on the respective reflecting mirror surfaces caused by rotational errors of the polygon mirror 8, in this embodiment. As hereinabove described, the time resolution for detection of the dot misregistration amounts is t/N and the length resolution is d/N (d: dot diameter). With reference to a timing chart of FIG. 7, description is now made in detail on detection of dot misregistration.

As shown in FIG. 7, detection output of the start sensor 12 is supplied to a clock input of a latch circuit 17, so that current states (1, 1, 0, 0, 0, 0, 0, 1, 1, 1 in FIG. 7) of the dot recording clock signals .phi..sub.1 to .phi..sub.N are latched in the latch circuit 17. An encoder 18 encodes the contents latched in the latch circuit 17 to output a signal indicating a sequence number (3 of .phi..sub.3 in FIG. 7) of a dot recording clock signal synchronized with the detection output of the start sensor 12 (i.e., rising immediately after the detection output of the start sensor 12 to become "1"). Encoding in the encoder 18 can be performed by identifying, for example, the first occurence of continuous "0" or "0" immediately after continuous "1". Output from the endoder 18 is supplied to a first selector 19, which in turn selects the corresponding dot recording clock signal (.phi..sub.3 in case of FIG. 7), to output the same to a third counter 20.

The detection output of the start sensor 12 is also supplied to a clock input of a D flip-flop 22 through an OR gate 21, whereby the Q output of the D flip-flop 22 rises to "1". This Q output is supplied to an enable terminal of the third counter 20, which in turn is activated to count the selected dot recording clock signal (.phi..sub.3 in FIG. 7) in response to its leading edge. Thereafter, detection output of the end sensor 14 is supplied to the clock input of the D flip-flop 22 through the OR gate 21, whereby the Q output of the D flip-flop 22 falls to "0". Thus, the third counter 20 is disabled and terminates counting. FIG. 7 shows the case where counting is performed up to 10002. This count value indicates the number of dots that can be recorded between the start sensor position and the end sensor position, whereas such number is not effective since the final one count does not correspond produce a whole dot (i.e., one cycle of the dot recording clock signal) as shown in FIG. 7. This count value is reformed in the manner as hereafter described.

A subtracter 23 receives the count value to subtract a reference count value previously set in a latch circuit 24 through a CPU or the like from the count value. For example, the interval from the start sensor position to the end sensor position is mapped with the shorter edge side of 200 mm of the A4 size, to scan the same in a main scanning direction in resolution of 1270 lines/inch (dot diameter=20 .mu.m). In this case, the standard dot number is:

whereas the final one count within the count value of the third counter 20 is not effective as hereinabove described, therefore 10001, obtained by adding 1 to the standard dot number of 10000, is set in the latch circuit 24 as a reference count value in order to exclude the final one count by subtraction. Therefore, the result of subtraction by the subtracter 23 is:

Thus, it is evident that the amount of dot misregistration in the unit of dot is +1 dot. The + sign means that the rotational speed at the reflecting surface of the polygon mirror 8 is delayed as compared with the standard rotational speed, and therefore the scanning length of one scanning line is shorter than the standard scanning length (terminating end of one scanning line is immediately ahead of 10001-th count).

On the other hand, the following processing is performed in order to detect the amount of dot misregistration smaller than one dot by time resolution of t/N (length resolution of d/N in standard rotational speed): The current states of the dot recording clock signals .phi..sub.1 to .phi..sub.N are latched in a latch circuit 25 in response to detection output of the end sensor 14 to encode the same by an encoder 26 in order to derive a sequence number (i.e., 9 in FIG. 7) of a dot recording clock signal (.phi..sub.9 in FIG. 7) synchronous with the detection output of the end sensor 14. This operation is similar to that in the aforementioned case of deriving the sequence number of the dot recording clock signal synchronous with the detection output of the start sensor 12 by the latch circuit 17 and the encoders 18. A subtracter 27 receives the outputs from the encoders 18 and 26, to subtract the output of the encoder 18 from that of the encoder 26. In the example shown in FIG. 7, the result is:

Thus, it is evident that the amount of dot misregistration smaller than one dot is (d/10).times.6. When the result of subtraction in the subtracter 27 is negative, a number N (10 in FIG. 7) is added to the negative result of subtraction in a translation table 28 (of a subsequent stage) to process the result as a positive value. Assuming that, for example, the detection output of the end sensor 14 is generated as the timing shown by the one-dot chain line, the dot recording clock signal synchronous with this is .phi..sub.1 and the result of subtracting the subtracter 27 is 1-3=-2, while the translation table 28 changes the result into 10-2=8, in order to perform processing on the assumption that the amount of dot misregistration smaller than one dot is (d/10).times.8.

The amounts of dot misregistration thus resulting, i.e., the results of subtraction in the subtracters 23 and 27, are translated by using table 28 into data representing crossover timing and crossover phase direction of dot recording clock signals that is required for correcting dot misregistration. The table data are previously set through the CPU or the like.

For example, the manner of obtaining the table data in the case where N is 10 and the standard dot number of one scanning line is 10000 is as follows:

(1) When the result of subtraction in the subtracter 23 is +1 and the subtracter 27 is +6:

The total amount of dot misregistration in this case is (d/10).times.16 since 10.times.1+6=16, therefore, crossover of the dot recording clock signals may be performed 16 times. In order to uniformly perform a crossover of 16 times during one scanning (i.e., 10000 dots), crossover must be performed every 10000/17 dots. Since the result of subtraction in the subtracter 23 is positive and the scanning length of one scanning line is shorter than the standard value as hereinabove described, the crossover phase direction is that of phase lag.

(2) When the result of subtraction in the subtracter 23 is -2 and that in the subtracter 27 is -3:

As hereinabove described, -3 is processed as 7. The total amount of dot misregistration is (d/10).times.13 since 10.times.(-2)+7=-13, whereby crossover may be performed every 10000/14 dots for the reson described in the item (1). Since the result of subtraction in the subtracter 23 is negative and the scanning length of one scanning line is longer than the standard value, the crossover phase direction is that of phase lead.

Symbols of the table data created on the basis of the above are shown as follows: (Symbol INT indicates integral parts and symbols U and D indicate crossover phase directions of phase lag and phase lead respectively.)

When there is no error, a value causing no carry, e.g., INT(10000/1)+1=10001 is loaded in a first counter 30. Then, no crossover takes place since the output of a second counter 31 remains at zero.

The data of the crossover timing and the crossover phase direction thus obtained are inputted in a shift register 29 and applied to the same reflecting mirror surface of the polygon mirror 8 after one rotation. The shift register 29 then shifts the data in response to a detection output of the start sensor 12, i.e., every 1/6 rotation of the polygon mirror 8, in order to supply the data to the first counter 30 upon one rotation of the polygon mirror 8. It is well known that there is considerable regularity concerning rotational error(s) of each surface of a general polygon mirror, and hence no new errors are introduced even if correction is performed by employing error data of a preceding mirror rotation.

Further operation is described with reference to FIG. 2, on the assumption that INT (12/4)=3 as obtained from the crossover timing and U (lag) is obtained as the crossover phase direction. (This assumption is made in order to facilitate easy understanding of the present invention.) When there is detection output from the start sensor 12 with respect to the same reflecting mirror surface of the polygon mirror 8 after one rotation from the time when the above data was generated, crossover timing=3 is preset in the first counter 30 from the shift register 29, while the data of crossover phase direction=U (lag) is preset in the second counter 31 from the shift register 29. At the same time, the sequence number of the dot recording clock signal synchronous with the detection output of the start sensor 12 is detected by the latch circuit 17 and the encoder 18, as hereinabove described. The following description is made on the assumption that the dot recording clock signal synchronous with the detection output of the start sensor 12 is .phi..sub.3 and the sequence number=3 is obtained from the encoder 18.

The counter 31 is reset in a blanking interval from the detection output of the end sensor 14 to precede scanning the detection output of the start sensor 12 of the current scanning, and hence the count output of the second counter 31 is zero at the beginning. The D flip-flop 22 and the third counter 20 are similarly reset in the blanking interval. On the other hand, a load value 3 is loaded in the first counter 30 upon receipt of the detection output from the start sensor 12. Immediately after the detection output of the start sensor 15, therefore, an adder 32 receives value 3 from the encoder 18 and value zero from the second counter 31, and also supplies the value 3 to a second selector 33. The second selector 33 responsively selects .phi..sub.3 from the dot recording clock signals .phi..sub.1 to .phi..sub.N and outputs the crossover dot recording clock signal .phi..sub.X. This crossover dot recording clock signal .phi..sub.X is supplied to clock inputs of the first and second counters 30 and 31. The enable terminal of the second counter 31 is connected to the carry output of the first counter 30 and therefor the second counter 31 is disabled until occurrence of the carry output; hence counting is first performed only by the first counter 30.

The first counter 30 down-counts one by one from the aforementioned preset value 3 for every leading edge of the crossover dot recording clock signal .phi..sub.X. The carry output of the first counter 30 rises when the count value reaches 1, whereby the second counter 31 is activated. In response to a subsequent leading edge of the crossover dot recording clock signal .phi..sub.X, the second counter 31 up-counts by one from zero, whereby the count value becomes 1. The instruction for the up-counting is supplied by the aforementioned preset data of crossover phase direction=U (lag). If the crossover phase direction=D (lead), down-counting is performed so that the count value becomes -1. The carry output of the first counter 30 falls at the same time when the count value of the second counter 31 becomes 1, whereby the second counter 31 is again disabled, and the preset value 3 is loaded in the first counter 30 on the trailing edge thereof.

When the count value of the second counter 31 is 1, the adder 32 receives 3 and 1, and therefore the added output resulting thereof is 4. The second selector 33 responsively selects the dot recording clock signal .phi..sub.4 to output the same as the crossover dot recording signal .phi..sub.X. Thus, crossover of adjacent dot recording clock signals in the phase lag direction is performed.

Similar cycles of operation are repeated in order to create the crossover dot recording clock signal .phi..sub.X subjected to crossover in uniform intervals of .phi..sub.3 .fwdarw..phi..sub.4 .fwdarw..phi..sub.5 .fwdarw..phi..sub.6 every three cycles (i.e., three dots) of the crossover dot recording clock signal .phi..sub.X. The dot misregistration in FIG. 2(B) is eliminated by scanning in synchronization with the crossover dot recording clock signal .phi..sub.X, as hereinabove described. Although the 13-th dot is a dot recording clock signal .phi..sub.7, no influence is exerted by the same since scanning of one scanning line is completed by 12 dots.

FIG. 8 is a block diagram showing a modification of the circuit for creating the crossover dot recording clock signal .phi..sub.X in the image processing circuit 4. In this modification, a clock generator 15 generates a clock signal .phi..sub.ORG of a frequency N times the dot recording clock signals .phi..sub.1 to .phi..sub.N (i.e., cycle t/N) to be frequency-divided and delayed by a frequency divider/delay circuit 34, in order to create N dot recording clock signals .phi..sub.1 to .phi..sub.N.

FIG. 9 is a block diagram showing an example of the frequency divider/delay circuit 34. The clock signal .phi..sub.ORG from the clock generator 15 is frequency-divided into 1/N by a frequency dividing counter 35. The clock signal thus frequency-divided into 1/N is input to D.sub.1 input of a D flip-flop 31, to be outputted as a dot recording clock signal .phi..sub.1 in response to the leading edge of the clock signal .phi..sub.ORG. The dot recording clock signal .phi..sub.1 is also input to D.sub.2 input of the D flip-flop 36, to be outputted as a dot recording clock signal .phi..sub.2 in response to a subsequent leading edge of the clock signal .phi..sub.ORG. Thus, N dot recording clock signals .phi..sub.1 to .phi..sub.N delayed by the cycle t/N of the clock signal .phi..sub.ORG can be generated. (FIG. 10 illustrates this situation.)

In the modification shown in FIG. 8, the third counter 20 receives the clock signal .phi..sub.ORG at its clock input and is activated only during the interval between the detection output of the start sensor 12 and that of the end sensor 14 to count the clock signal .phi..sub.ORG, as hereinabove described with reference to the embodiment of FIG. 5. This count value is latched in a latch circuit 37 in synchronization with the detection output of the end sensor 14. Since the cycle of the clock signal .phi..sub.ORG is t/N, the count value of the third counter 20 is a count value by a time resolution of t/N (length resolution in standard rotational speed of the polygon mirror 8 is d/N). Therefore, if there is no dot misregistration when the standard dot number of one scanning line is 10000 for example, the count value of the third counter 20 is 10000.times.N. In other words, 10000.times.N is processed as a reference count value, so that difference between this reference count value and the count value of the third counter 20 indicates the amount of dot misregistration by the length resolution of d/N.

The translation table 28 receives the count value of the third counter 20 latched in the latch circuit 37 and outputs data for crossover timing and crossover phase direction required to eliminate the amount of dot misregistration expressed by the count value. The concept of creation of table data is similar to that in the embodiment of FIG. 6, and examples of the dot number of one scanning line is equal to 10000 and N is equal to 10 are as follows:

When there is no error, a value causing no carry, e.g., INT(10000/1)+1=10001 is loaded in the first counter 30, similar to the embodiment of FIG. 6.

This data is supplied to the shift register 29, so that the crossover dot recording clock signal .phi..sub.X is generated similarly to the embodiment of FIG. 6. Then, scanning is performed without dot misregistration by the crossover dot recording signal.

Although crossover for 16 times is performed every 10000/17 dots during scanning when the result of subtraction in the subtracters 23 and 27 is 16, as, for example, in the embodiment of FIG. 6, crossover may be performed after 10000/36 dots at the beginning to thereafter perform crossover every 10000/16 dots. In this case, first data (10000/32) and second data (10000/16) are inputted in the shift register 29 by the translation table 28 as result of subtraction. The first data 10000/32 is loaded in the first counter 30 at the beginning and the second data 10000/16 is loaded in the first counter 30 when a carry is caused from the first counter 30 after starting of recording. When the result of subtraction by the subtracters 23 and 27 is within .+-.1, both the first and second data are identical to those as hereinabove described. This also applies to the modification shown in FIG. 8.

FIGS. 11(A) and 11(B) shows a modification of this case. The translation table 28 transfers U/D signal and two types of load values to the shift register 29 as hereinabove described with reference to FIG. 6, on the basis of the result in the subtracters 23 and 27. Immediately after starting, output Q.sub.2 of a timing circuit 50 goes low at timing shown in FIG. 11(B), and the first counter 30 fetches first data (INT(10000/32)) at the timing of .phi..sub.X during this interval. The output Q.sub.2 of the timing circuit 50 goes high when .phi..sub.X continues, and second data (INT(10000/16)) is transferred as the load value to the first counter 30. When counting by the first counter 30 continues so that the first counter 30 causes a carry, the second data is loaded in the first counter 30. Thereafter the output Q.sub.2 of the timing circuit 50 holds the high level, whereby the second data is loaded every time a carry occurs.

Although crossover in each of the aforementioned embodiments, and modifications are performed toward adjacent phases, such crossovers may be performed when a phase is excessive by one and remain within a range where the picture quality is not deteriorated. The amount of crossover is reduced by the excess, as a matter of course.

According to the first embodiment of the present invention as hereinabove described, dot misregistration on the scanning lines caused by rotational errors of the polygon mirror can be easily eliminated with simple structure without providing grating or synchronous control circuitry and without requiring a polygon mirror of high accuracy.

With reference to FIG. 12, description is now made on the basic concept of a second embodiment of the present invention. First, assume the start positions of respective scanning lines are registered by the start sensor 12 as hereinabove described with reference to the second conventional method, for example, dot misregistration is caused by rotational error of the polygon mirror 8 at the terminating end of each scanning line as shown in FIG. 12(a). Referring to FIG. 12, symbols S and E denote correct start and end positions (dot center positions) of the scanning lines. The amount .DELTA. Y of dot misregistration at the terminating end of the scanning line is expressed as follows:

where symbol L indicates scanning length and symbol J indicates rotational error (speed regulation). When L=100 mm and J=0.01%, for example, the amount of dot misregistration at the terminating end of the scanning line is:

Assuming that recording resolution is 1270 lines/inch (diameter d of one dot=20.mu.m), the ratio of the amount of dot misregistration to one dot is:

FIG. 12(a) shows the case of dot misregistration of 1/2 dot, whose recorded image edges are non-linear and indented. This image cannot be employed for a line original or a halftone plate.

The second embodiment of the present invention reduces dot misregistration by compensating for approximately one half of the dot misregistration caused at the terminating end of the scanning line in a starting point of scanning. For example, the terminating end of the second scanning line shown in FIG. 12(a) is leftwardly misregistered by 1/4 dot, and hence the same is rightwardly displaced by half the amount of misregistration i.e., 1/8 dot from the scanning start position as shown in FIG. 12(b). The terminating end of the third scanning line in FIG. 12(a) is rightwardly misregistered by 1/4 dot, and hence the same is leftwardly displaced by half the amount of misregistration, i.e., 1/8 dot from the scanning start position as shown in FIG. 12(b). The scanning start positions are misaligned by this operation, whereas it is obvious that the total amount of dot misregistration is reduced to a half, i.e., 1/4 dot. According to this method, the amounts of dot misregistration at the terminating ends of the scanning lines are suppressed to about half that of the prior art at the maximum, while the same are dispersed over the entire screen (particularly in the vicinity of both ends) thereby reducing the amount of dot misregistration as a whole. Such an effect is increased as dot resolution is increased and rotational error accuracy of the polygon mirror is improved, so that apparent picture quality is improved.

In order to implement the aforementioned concept, the embodiment obtains the rotational error times of respective surfaces of the polygon mirror and performs image recording by dot recording clock signals out of phase by about half the error time of each surface of the mirror having a rotational error. The structure shown in FIG. 5 may be employed, and in this case, the image processing circuit 4 receiving the detection signals from the start sensor 12 and the end sensor 14 obtains the rotational error time of each surface of the polygon mirror 8, in order to output a dot signal indicating variable density of each dot to the semiconductor laser 5, for every surface of the polygon mirror 8, in synchronization with a dot recording clock signal responsive to the obtained rotational error of each surface of the mirror.

FIG. 13 is a block diagram showing circuitry of the image processing circuit 4 for generating the dot recording clock signals responsive to the rotational errors of the respective surfaces of the polygon mirror 8. A crystal oscillator 15 generates a reference clock signal, which is passed through a delay circuit 16 so that the cycle t of the reference clock signal is equally divided into N to create N clock signals delayed by t/N. The N clock signals are numbered from 1 to N in sequence from the reference clock signal. FIG. 14 illustrates the case of N=10. Time resolution measurable by employment of the N clock signals is t/N, and length resolution is d/N (assuming that the diameter of one dot is (d).

According to the embodiment hereafter described in detail, the aforementioned N clock signals are used to obtain the rotational error factor of the respective reflecting mirror surfaces of the polygon mirror 8 while selecting a clock signal, from the N signals, which is out of phase by 1/2 of the obtained rotational error times with respect to a clock signal synchronous with detection output of the start sensor 12, to employ the same as a dot recording clock signal.

First, a clock signal synchronous with the detection output of the start sensor 12 is selected form .phi..sub.1 to .phi..sub.N in a circuit formed by a J-K flip-flop 17, a delay circuit 18, a D flip-flop 19, a decoder 20 and a selector 21. The operation is as follows:

The J-K flip-flop 17 is reset in a blanking interval preceding scanning and current scanning; for example, to enter a set standby state by receiving the detection output of the start sensor 12 in its J input. Thereafter, Q output corresponding to a first inputted signal of clock signal .phi..sub.1 to .phi..sub.N becomes "1", and the current state of the Q output is latched in the D flip-flop 19 by clocking the D flip-flop 19 by a signal generated by delaying the detection output of the start sensor 12 through a delay circuit 18. The decoder 20 decodes the Q output of the D flip-flop 19, and outputs a signal CK.sub.S (CK.sub.S =1 to N) representing the number of the clock signal synchronous with the detection output of the start sensor 12. The selector 21 then selects a clock signal .phi.(CK.sub.S) corresponding to CK.sub.S from the N clock signals .phi..sub.1 to .phi..sub.N. FIG. 15 shows an example in which a clock signal of No. 3 (CK.sub.S =3) is selected in response to the detection output of the start sensor 12.

On the other hand, a circuit part formed by a J-K flip-flop 22, a delay circuit 23, D flip-flop 24 and a decoder 25 obtains a signal CK.sub.E (CK.sub.E =1 to N) representing the number of a clock signal synchronous with the detection output of the end sensor 14. This operation is similar to that for obtaining CK.sub.S as hereinabove described, and hence description thereof is omitted. FIG. 15 shows an example where a clock signal of No. 9 (CK.sub.S =9) is selected in response to the detection output of the end sensor 14.

The clock signal .phi.(CK.sub.S) selected by the selector 21 is counted by a counter 26 until detection output of the end sensor 14 is generated. Assuming that COUNT(CK.sub.S) represents the count number, the scanning time T between the start sensor 12 and the end sensor 14 is generated from the same and the aforementioned CK.sub.S and CK.sub.E, as follows:

When CK.sub.S .ltoreq.CK.sub.E,

when CK.sub.S >CK.sub.E,

When the time resolution t/N by the N clock signals is normalized to 1, i.e., when the scanning time is the same in resolution of the numbering of the clock signals, the count value CT of the scanning time can be expressed as follows:

When CK.sub.S .ltoreq.CK.sub.E,

When CK.sub.S >CK.sub.E,

In the example shown in FIG. 15, COUNT(CK.sub.S)=5, CK.sub.E -CK.sub.S =6 and N=10, and CT=56 from the above expression (12).

In the embodiment shown in FIG. 13, circuitry for generating the above expressions (12) and (13) comprises a multiplier 27, a subtracter 28, an adder 29, a selector 30 and an adder 31. The multiplier 27 multiplies COUNT(CK.sub.S) outputted from the counter 26 by N, to generate the first terms of the expressions (12) and (13). The subtracter 28 receives the output of the decoder 25, i.e., CK.sub.E in its subtracted input while receiving the output of the decoder 20, i.e., CK.sub.S in its subtacting input and operates CK.sub.E -CK.sub.S thereby and outputs the result to the adder 29 and the selector 30, and outputs a sign indicating negative/positive value of the result of operation to the selector 30. The adder 29 performs adding N, to output N+CK.sub.E -CK.sub.S to the selector 30. The selector 30 selects CK.sub.E -CK.sub.S, i.e., the result of the subtracter 28 when the result of the subtacter 28 is positive or zero, i.e., when CK.sub.S .ltoreq.CK.sub.E to output the same, while selecting N+CK.sub.E -CK.sub.S, i.e., the result of the adder 29 when CK.sub.S >CK.sub.E to output the same. The adder 31 adds up the output of the multiplier 27 and that of the selector 30, thereby obtaining the scanning time count value CT by the aforementioned expressions (12) and (13).

The scanning time count value CT is compared with a standard count value CT.sub.N, to recognize rotation error times of the respective surfaces of the polygon mirror 8. In this embodiment, an average value CT.sub.AVE of six scanning time count values CT obtained by one rotation of the polygon mirror 8 is employed as the standard count value CT.sub.N. Assuming that the obtained scanning time count values CT are CT.sub.1, CT.sub.2, . . . , CT.sub.6 in sequence,

In general, M (M: integral multiple of the surface number of the polygon mirror 8) of CT.sub.j corresponding to an arbitrary rotation number of the polygon mirror 8 can be averaged so that: ##EQU1## Differences between the average value CT.sub.AVE and the respective CT.sub.j indicate the rotational error times in the respective surfaces of the polygon mirror 8, and assuming that the count values of the rotational error times are expressed by CR.sub.j,

In the embodiment shown in FIG. 13, circuitry for generating the expressions (14) and (16) comprises a shift register 32, a summing circuit 33, a divider 34 and a subtracter 35. The shift register 32 receives CT.sub.j as the results of operation of the adder 31 and stores six of the same while shifting the same, and the shifted CT.sub.j are supplied to the subtracted input of the subtracter 35. The summing circuit 33 sums up the continuous six CT.sub.j stored in the shift register 32, so that CT.sub.AVE of the expression (14) is obtained by dividing the same into 1/6 by the divider 34. The CT.sub.AVE is supplied to the subtracting input of the subtracter 35, which in turn generates CT.sub.j -CT.sub.AVE of the expression (16). Thus, the count values CR.sub.j of the rotational error times of the polygon mirror 8 are obtained.

The count value CR.sub.j corresponds to the corresponding surface in the preceding rotation of the polygon mirror 8, and it is well known there is considerable regularity with respect to rotational error(s) of each surface in general rotation of a polygon mirror, whereby no new error(s) is introduced by employing the data of rotational error times of a preceding rotation.

If CR.sub.j >0, the scanning time between the start sensor 12 and the end sensor 14 is longer than the standard value (i.e., rotation of the polygon mirror 8 is delayed), and the scanning length for one scanning line recording is shorter than the standard level, as shown in the second line in FIG. 12(a). When CR.sub.j <0, on the other hand, the scanning length for one scanning line recording is longer than the standard level, as shown in the third line of FIG. 12(a). Therefore, the direction for reducing the dot misregistration caused by rotational errors of the polygon mirror 8 is rightward direction (in FIG. 13) i.e., phase shift in a positive direction in dot recording clock signal when CR.sub.j >0, while the phase shift is to negative contrary when CR.sub.j <0.

Assuming that CK.sub.H represents the count value of phase correction for finding a clock signal phase-shifted in a direction for reducing the dot misregistration caused by error by 1/2 of the rotational error time of the polygon mirror 8, the following expression holds:

Therefore, an identification number CK.sub.V for a clock signal to be selected as the dot recording clock signal (one of .phi..sub.1 to .phi..sub.N) is obtained by the following expression:

N is added for operation in situations where the value of CK.sub.S +CK.sub.H is negative, while the remainder in the division by N is obtained since assumed is such case where the amount of dot misregistration is within one dot.

In the embodiment shown in FIG. 13, circuitry for generating the above expressions (17) and (18) comprises a divider 36, a summing circuit 37 and a ROM 38. The divider 36 divides CR.sub.j outputted from the subtracter 35 by 1/2 to generate CK.sub.H of the expression (17), and outputs the same to the summing circuit 37. The summing circuit 37 receives CK.sub.H, CK.sub.S outputted from the decoder 20 and the constant N and sums up the same to generate N+CK.sub.S +CK.sub.H. On the other hand, the result of operation of (N+CK.sub.S +CK.sub.H)modN in the expression (18) is written in a look-up table in the ROM 38, which in turn receives output from the summing circuit 37, to read corresponding CK.sub.V.

The CK.sub.V thus obtained is input to a selector 39, which in turn outputs a clock signal .phi.(CK.sub.V) corresponding to CK.sub.V from the N clock signals .phi..sub.1 to .phi..sub.N as the dot recording clock signal. The image processing circuit of FIG. 13 outputs a dot signal representing variable density of each dot in synchronization with the dot recording clock signal .phi.(CK.sub.V) is thus input to the semiconductor laser 5. Thus, as shown by dotted lines in FIG. 16, the scanning lines causing dot misregistration are entirely shifted by half the amounts of misregistration, thereby reducing the total amount of dot misregistration. Referring to FIG. 16, dot misregistration of (1/2). d is corrected by the present invention so that the amount of total dot misregistration is reduced to (1/4).d. The dot misregistration is substantially zero at the center of the screen. The present invention is applicable to both on-off modulation and continuous modulation.

According to the second embodiment as hereinabove described, dot misregistration of scanning lines caused by rotational errors of a polygon mirror can be easily reduced with simple structure without providing grating or synchronous control circuitry and without requiring extremely accurate polygon mirrors. Further, the dot misregistration is substantially zero at the center of the screen.

Although the present invention has been described and illustrated in detail, it is to be clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the spirit and scope of the present invention being limited only by the terms of the appended claims.