Logic Circuit Resistant to Errors Due to Supply Fluctuations

1. Field of the Invention

This invention relates to logic circuits of the type which sense the level of one or more input signals by referencing said one or more input signals to a threshold level, and in particular to an improved logic circuit which is unaffected by large and abrupt changes in supply voltage.

2. Description of the Prior Art

FIG. 1 illustrates a representative prior art logic circuit 5, which includes input signal generator 6, differential logic circuit 7, and reference voltage generator 8, all having power supplied by supply voltage V.sub.cc. It is to be noted that the present invention can be applied to a variety of logic circuits whether they be analog or digital, or whether or not the logic circuit requires a reference voltage to establish a threshold voltage for determining a high or low state of a signal. What is important, however, is that the logic circuit have a 25 threshold voltage related to a certain voltage level, such as a power supply voltage level, and the level of an input signal to be referenced to the threshold voltage is also 28 related to the certain voltage level.

In FIG. 1, input signal generator 6 generates an input voltage V.sub.in which is to be compared to a reference voltage V.sub.ref, generated by reference voltage generator 8, to determine whether V.sub.in represents a high or low state. If V.sub.in is greater than V.sub.ref, V.sub.ref being approximately equal to [V.sub.in (high)+V.sub.in (low)]/2, differential logic circuit 7 generates an output signal V.sub.out which will be at, for example, a high state. The design of input signal generator 6 and reference voltage generator 8 is such that the two circuits will respond similarly to changes in ambient temperature and low frequency variations in supply voltage V.sub.cc. The output V.sub.out of differential logic circuit 7 is not affected by the amplitudes of V.sub.in and V.sub.ref increasing or decreasing together due to these temperature and supply voltage variations, since it is the difference between the two signals that is measured. Differential logic circuit 7 also isolates the more sensitive input signal generator 6 from output circuits coupled to V.sub.out.

If supply voltage V.sub.cc were to undergo an abrupt change, such as a voltage spike, the amplitudes of V.sub.in and V.sub.ref may not correspond identically since the frequency responses and amplitude versus time responses of input signal generator 6 and reference voltage generator 8, as determined by the time constants of each circuit, may not be identical.

Generally, for lower frequency perturbations in supply voltage V.sub.cc, the time constants of both circuits are so small in comparison to the rate of change of V.sub.cc that they have negligible effect on the responses of these circuits to these V.sub.cc perturbations. Thus, the circuits will respond similarly without causing an erroneous output voltage V.sub.out to be generated. However, for very abrupt changes in supply voltage V.sub.cc, such as when an inductive output load is switched on or off and generates a di/dt related voltage spike on the power supply line, the difference in time constants of the two circuits may be large enough for V.sub.in and V.sub.ref to vary in amplitude at significantly different rates and possibly cause an erroneous output voltage V.sub.out to result.

FIG. 2 illustrates a case wherein one power supply is used to power both an output circuit, controlled by V.sub.out, and logic circuit 5 of FIG. 1. Steady state amplitudes of supply voltage V.sub.cc, input voltage V.sub.in, reference voltage V.sub.ref, and output voltage V.sub.out are shown from time T0 to T1. As seen, V.sub.in is below V.sub.ref, which, in this case, causes V.sub.out to be at a low state. At T1, a voltage spike on the power line causes V.sub.cc to rise rapidly. This abrupt increase in supply voltage V.sub.cc causes a slightly delayed but sudden increase in V.sub.in, this increase being determined by the time constants of input signal generator 6, and causes a slower increase in V.sub.ref, due to reference voltage generator 8 having larger time constants. At T2, V.sub.in rises above V.sub.ref, causing V.sub.out to go high and to thus send an erroneous output voltage to the output circuit. At T3, V.sub.in falls below V.sub.ref, due to V.sub.ref still rising and V.sub.in starting to fall, and V.sub.out is switched to a low state. At T4, proper operation of the logic circuit resumes. To avoid these erroneous output voltages, prior art logic circuits typically employ two independent power supplies: one to power the sensitive logic circuits, and the other to power the output buffer circuits and output loads. The additional power supply increases the cost and space requirements to support the logic circuit and adds complexity to the integrated circuit containing the logic circuit due to at least two power supply pins being required. Prior art logic circuits which employ one power supply must have the permissible voltage deviations between the threshold voltage level and input signals increased to accommodate these differing responses to voltage spikes, causing a concomitant lowering in switching speed.

Disclosed herein is an improved logic circuit of the type in which one or more input signals are referenced to a threshold voltage level to determine whether said one or more input signals are above or below said threshold voltage level, and wherein said input signals and said threshold voltage level are related to a common voltage, such as a power supply voltage. In this improved logic circuit, the effective time constants of one or more input signal generators, generating said input signals, are matched with those of the circuit setting the threshold voltage level so that, for example, any power supply perturbations, including voltage spikes such as due to the switching on or off of output loads, will result in identical frequency responses and amplitude versus time responses for the input signal generators and threshold voltage level circuit and prevent an erroneous output from being generated. The time constants of the circuits may be matched by changing the equivalent resistance, capacitance, or inductance of either the input signal generator circuits or the threshold voltage level circuit to increase or decrease their time constants. With the time constants of the circuits matched, only one power supply is required to supply power to the output loads and to the more sensitive logic circuit. Prior art logic circuits already employing one power supply may, with our inventive method, decrease the voltage swing between a signal's high and low state, thus increasing switching speed, without increasing the probability of an erroneous output.

FIG. 1 is a block diagram representative of a typical prior art logic circuit.

FIG. 2 illustrates the effect on various voltage amplitudes within a logic circuit due to a voltage spike on the power supply line.

FIG. 3 is a schematic diagram of a logic circuit with parasitic capacitances shown, wherein the time constants of an input signal generator and a reference voltage generator circuit are made equal at node of interest using our inventive method.

FIG. 4 is a schematic diagram of a logic circuit illustrating a different type of threshold voltage level generator from that of the circuit in FIG. 3.

Our inventive method to match time constants of one or more input signal generator circuits with that of a circuit responsible for setting a threshold voltage level is described hereinbelow with reference to FIG. 3.

FIG. 3 is a schematic diagram of a logic circuit 18 used to sense the state of a certain voltage V.sub.B, such as a data bit, and provide an output voltage V.sub.out corresponding to the state of that voltage. Logic circuit 18 includes differential logic circuit 20, which is a differential amplifier with inputs being input voltage V.sub.in, V.sub.in being the output of input signal generator 30, which is itself a logic circuit, and reference voltage V.sub.ref, V.sub.ref being the output of reference voltage generator 40. The output voltage V.sub.out of differential logic circuit 20 is dependent on the difference between V.sub.in and V.sub.ref. Input signal generator 30 and reference voltage generator 40 are designed so that V.sub.in increases or decreases along with V.sub.ref when, for example, ambient temperature varies or supply voltage V.sub.cc varies, so that the difference between these two signals remain constant despite their absolute changes in amplitude. Abrupt changes in supply voltage V.sub.cc, however, causes V.sub.in and V.sub.ref to fluctuate dissimilarly if the frequency response and amplitude versus time response of input signal generator 30 and reference voltage generator 40, as determined by the time constants of the two circuits, are different. If the divergence of the signals exceeds a predetermined amount, an erroneous output voltage V.sub.out will be generated. The novel feature of the present invention is that the time constants of input signal generator 30 and reference voltage generator 40 are made substantially identical. This is accomplished by establishing the time constants of one of the circuits and adjusting the components of the other circuit so that both circuits have substantially identical frequency responses and amplitude versus time responses to surges on the power supply line. The schematic diagram of FIG. 3 will now be described in detail followed by a preferred method to match frequency responses and amplitude versus time responses.

In FIG. 3, components of logic circuit 18 are shown along with the parasitic capacitances associated with the circuit. Differential logic circuit 20 comprises transistors 22 and 24, which can be, for example, N-channel MOSFETs, N-channel MESFETs, or NPN bipolar transistors, with input voltage V.sub.in applied to the control terminal of transistor 22 and reference voltage V.sub.ref applied to the control terminal of transistor 24. Assuming transistors 22 and 24 are MESFETs, supply voltage V.sub.cc is coupled to the drains of transistors 22 and 24 through resistors R.sub.1 and R.sub.2, respectively. The sources of transistors 22 and 24 are made common and are coupled to ground through current controlling transistor 26 and resistor R.sub.3 in series. Control voltage V.sub.con is applied to the control terminal of transistor 26 to control the current through resistor R.sub.3. Output voltage V.sub.out is the voltage difference between the voltages on the drains of transistors 22 and 24, or alternatively, that voltage at the drain of transistor 22 or 24. The difference voltage, however, provides better common-mode rejection and will constitute V.sub.out in FIG. 3.

Input signal generator 30 comprises transistors 32 and 34, with voltage V.sub.B applied to the control terminal of transistor 32 and the inverse V.sub.B of voltage V.sub.B applied to the control terminal of transistor 34. Supply voltage V.sub.cc is coupled to the drains of transistors 32 and 34 through resistors R.sub.4 and R.sub.5, respectively. The sources of transistors 32 and 34 are made common and are coupled to ground through current controlling transistor 36 and resistor R.sub.6 in series. Control voltage V.sub.con is applied to the control terminal of transistor 36 to control the current through resistor R.sub.6. The output of input signal generator 30, V.sub.in, is that voltage at the drain of transistor 34.

Reference voltage generator 40 comprises current controlling transistor 42 with the drain of transistor 42 coupled to supply voltage V.sub.cc through resistor R.sub.7 and the source of transistor 42 coupled to ground through resistor R.sub.8. Control voltage V.sub.con is applied to the control terminal of transistor 42 to control the current through resistors R.sub.7 and R.sub.8. The output of reference voltage generator 40, V.sub.ref, is that voltage at the drain of transistor 42.

Coupled to reference voltage V.sub.ref are input signal generator/differential logic circuit pairs 2 through 10, though more may be added, illustrating that reference voltage V.sub.ref is shared by a number of other circuits.

The operation of logic circuit 18 is next described. When a high V.sub.B signal is applied to the control terminal of transistor 32 and the inverse of V.sub.B (i.e., a low state signal) is applied to the control terminal of transistor 34, transistor 32 conducts a relatively high current while transistor 34 conducts a relatively low current. The sum of these currents, I.sub.1, is kept constant by transistor 36. The reduced current through transistor 34 and resistor R.sub.5 causes a reduced voltage drop across R.sub.5 and, consequently, an increased V.sub.in, representing a high state. When a low state signal is applied to the control terminal of transistor 32 and the inverse of the signal is applied to the control terminal of transistor 34, V.sub.in is reduced, representing a low state.

Reference voltage V.sub.ref, which is to be compared with input voltage V.sub.in, is directly determined by the current I.sub.2 through resistor R.sub.7. Reference voltage V.sub.ref, thus, equals V.sub.cc -I.sub.2 R.sub.7. Control voltage V.sub.con is set so that reference voltage V.sub.ref is approximately equal to [V.sub.in(high)+V.sub.in (low)]/2 in order to make V.sub.ref be at the midpoint of the V.sub.in voltage swing.

When V.sub.in is in a high state, the current through transistor 22 is increased, drawing increased current through resistor R.sub.1 and lowering the voltage at the drain of transistor 22. The increased current through transistor 22 causes the voltage at the drain of current controlling transistor 26 to rise and, hence, the voltage at the source of transistor 24 to rise, resulting in transistor 24 conducting less current. The reduced current, I.sub.4, through resistor R.sub.2 results in a reduced voltage drop across resistor R.sub.2, producing an increased voltage at the drain of transistor 24. The difference in voltages at the drains of transistors 22 and 24 now represents a high state. A low input voltage V.sub.in would raise the voltage at the drain of transistor 22 and decrease the voltage at the drain of transistor 24 resulting in V.sub.out representing a low state.

The parasitic capacitance of the various components and metal lead lines are shown with dashed lines. Inductances are negligible in this example but may be significant where metal lead lines are long. In order to equalize the time constants of input signal generator 30 and reference voltage generator 40, as seen at node 1 and node 2, respectively, the time constants of input signal generator 30 and reference voltage generator 40 are calculated, or approximated, by well-known techniques and further defined using computer simulation, as in the preferred method. For logic circuit 18 in FIG. 3, the time constants at node 2 are made substantially identical to the time constants at node 1 by adjusting the value of resistor R.sub.7. Once the time constants of both circuits are substantial identical, the value of resistor R.sub.8 and the current through transistor 42 are adjusted to provide the proper voltage drop across resistor R.sub.7 in order to achieve the desired reference voltage V.sub.ref.

In the particular case of logic circuit 18, the time constants of reference voltage generator 40 are made substantially identical to those of input signal generator 30 by making resistor R.sub.7 equal 600.OMEGA.. To achieve the desired V.sub.ref, which is 4.5 volts in this particular case, a current of 830.mu.A must flow through the 600.OMEGA. resistor to give a 0.5 volt drop across R.sub.7. The value of resistor R8 is made 1.2K.OMEGA. so that the gate-to-source voltage on current controlling transistor 42, given a fixed control voltage V.sub.con, will result in a current of 830.mu.A through R.sub.7.

It is to be noted that our invention is applicable to a variety of circuits wherein the state or level of an input signal is referenced to an internal threshold voltage. For example, in FIG. 4, logic circuit 50 includes input signal generator 52, generating an input voltage V.sub.in, and output voltage generator 54, generating an output voltage V.sub.out and establishing a threshold voltage V.sub.th. In logic circuit 50, a high state V.sub.in applied to the base of transistor Q.sub.1 increases the current through Q.sub.1 and increases the voltage drop across R.sub.1. The decreased voltage at the collector of Q1 is applied to the base of transistor Q2, hence, reducing the voltage drop across resistor R2 and raising V.sub.out to a high state. The threshold level of circuit 54 is determined by the parameters of current source 56, formed by transistor Q3 and resistor R3, and transistors Q1 and Q2. As is apparent, a perturbation on power supply voltage V.sub.cc will cause both V.sub.in and V.sub.th to fluctuate. By matching the time constants of input signal generator 52 and output voltage generator 54, V.sub.in and V.sub.th will fluctuate similarly.

Thus, using the methods described above, logic circuits of the type herein described are essentially immune from power supply surges, and a single power supply may be used to power both the logic circuits and output circuits. An additional stage may also be added as opposed to adjusting internal components in order to adjust the time constants of one circuit.

It should be noted that parasitic capacitances and inductances may be formed by metal lines in close proximity, or if a line is relatively long. These lines should be taken into consideration in determining equivalent RC or LRC time constants.

The concept behind the preferred embodiment of the inventive device and method described above may be applied to a variety of circuits wherein both a threshold voltage and one or more input signals are affected by a common voltage. Accordingly, where the invention has been particularly shown and described with reference to the preferred embodiment thereof, it will be understood by those skilled in the art that deviations may be made therein without departing from the spirit and scope of the invention.