Vector Access Control System

The present invention relates to a vector access control system for a computer system. The system according to the present invention is used, for example, for controlling the access to vector data in a main storage relating to a vector unit in a supercomputer system.

A method of indirect address access has been used in a vector unit in a computer system where an access to a main storage is carried out by the designation of an index address for a leading address (or a base address). Generally, the main storage has a bank structure consisting of a plurality of banks, to increase the access speed, and accordingly, a plurality of data buses are connected with the main storage.

Indirect address data are read, per unit of plural sets of indirect address data, from the vector register, and a target address is produced by adding the read indirect address data to the leading address. The produced target address signal is then applied to the main storage so that the access processing is carried out.

For a "load" access operation, vector data are read in parallel from the banks of the main storage, by using the above-mentioned plural target addresses, and for a "store" access operation, vector data are written in parallel into the banks of the main storage, by using the above-mentioned plural target addresses.

It is assumed that vector data access requests with the indirect address method are simultaneously carried out by using a plurality of indirect addresses, for example, 4 indirect addresses, with respect to a main storage having a bank structure of, for example, 256 banks. If vector data are located at random in the main storage, a situation can occur in which a plurality of data in question, for example, data a.sub.1 and data a.sub.2, are located in the same address. In such a situation, a problem arises in that a bank conflict between the accesses to the main storage will occur, the access for the later data (for example, data a.sub.2, if data a.sub.1 is accessed with priority to data a.sub.2) is delayed, and the efficiency of the access operation is deteriorated.

It is an object of the present invention to provide an improved vector access control system for a computer system using the indirect address access method, in which the frequency of the occurrence of a busy state in the access to a main storage is reduced, and the speed of access to a main memory is increased, so that the efficiency of the access operation is enhanced.

In accordance with the present invention, there is provided a vector access control system for a computer system including: a main storage; a memory control unit for controlling the main storage; and a vector unit including vector registers and a memory access pipeline function unit having an indirect address match checking circuit for detecting a coincidence between data of elements accessed by a plurality of indirect address data. An access to the main storage is carried out by adding plural data, which are read from the vector registers and are necessary for an indirect address access, to a leading address. When a coincidence of data of elements and the resultant conflict between access requests to the main storage is detected by the indirect address match checking circuit, only a predetermined access request in the conflicting access requests is allowed .

FIGS. 1A, 1B, and 1C are diagrams illustrating a prior art vector access control system for a computer system;

FIGS. 2A and 2B are schematic diagrams of a vector access control system for a computer system according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of the logic circuit in the indirect address match check circuit in the system of FIGS. 2A and 2B;

FIG. 4 is a diagram of the access data control portion in the system of FIGS. 2A and 2B;

FIG. 5 illustrates the prohibition condition of the priority control circuit by the address match information in the system of FIGS. 2A and 2B;

FIG. 6 illustrates the operation of the system of FIG. 2A and 2B. de

Before describing the preferred embodiments, a prior art vector access control system for a computer system will be described with reference to FIGS. 1A, 1B and 1C.

The prior art system includes a main storage unit 1; a memory control unit 2 having a priority control unit 21, error correction code circuits 22, ports PA to PJ, address buses AA, AB, AC, and AD, data buses DA, DB, DC, and DD; a vector unit 3 having a vector register portion 37, a memory access pipeline function unit 5, an instruction control portion 6, an addition pipeline function unit 7, and a multiplication pipeline function unit 8. The vector register portion 37 includes vector registers VRA to VRD. The memory access pipeline function unit 5 includes registers VRRA to VRRD, an address generation portion 33, and an access data processing portion 36. The ports PE and PF in the memory control unit 2 are connected to a central processor unit (CPU) and a channel processor (CHP). The instruction control portion 6 is also connected to a central processor unit (CPU).

In the memory control unit 2, the ports PA to PE receive access requests, and the ports PF to PJ carry out data input or output.

In the system of FIGS. 1A, 1B and 1C, the main storage unit 1 consists of a plurality of banks having an "interleaving" structure, and a plurality of ports are provided in the memory control unit 2. Accordingly, it is necessary to avoid the "busy" state of the main storage unit and conflict of the buses. In order to avoid the "busy" state of the main storage unit and conflict of the buses, the priority control circuit 21 is provided for determining an access request priority.

After the determination of the priority is carried out, the addresses for the access requests are supplied to the main storage unit 1 through a plurality of request address buses AA, AB, AC, and AD. For a store access operation, the operation of the main storage unit 1 is started by signals sent through the address buses AA, AB, AC, and AD, and corresponding data is then supplied to the memory control unit 2 through the data buses DA, DB, DC, and DD. For a load access operation, the operation of the main storage unit 1 is started by signals sent through the address buses AA, AB, AC, and AD, and the memory control unit 2 corrects the data received from the main storage unit 1, by the error correction code circuits 22, and transmits the data to the vector unit 3, the central processor unit CPU, or the channel processor CHP.

In the vector unit 3, the instruction control portion 6 decodes the received vector instructions from the central processor unit CPU, and then the operations of the addition pipeline function unit 7, the multiplication pipeline function unit 8, and the memory access pipeline function unit 5 are started, and thus predetermined corresponding processes are carried out. The memory access pipeline function unit 5 carries out the transmission processing between the vector registers 37 and the main storage unit, 1. A pipeline function unit such as a division pipeline function unit, may be provided to supplement the addition pipeline function unit 7 and the multiplication pipeline function unit 8.

In general, there are a number of styles of vector data patterns in a main storage unit 1: A first style is a pattern in which data are located in a contiguous area; a second style is a pattern in which data are arranged with a constant stride; and, a third style is a pattern in which data are arranged at random, which is known as an indirect address access method. In the system of FIGS. 1A, 1B and 1C and in the system according to the present invention, this third style of vector data patterns is adopted.

In the system of FIGS. 1A, 1B and 1C in which the indirect address access method is adopted, first a leading address is defined, and then the data difference between the leading address and addresses of the data located at random in the main storage unit 1, that is the index data, is registered as the indirect address data per element of vector data in the vector registers VRA to VRD.

In the execution of the instruction, each of the indirect address data for the elements read from the vector register i added to a leading address instructed by the instruction control portion 6, and the access processing to the main storage unit 1 is carried out.

In the vector registers VRA to VRD, the data corresponding to the elements are registered. For example, in the vector register VRA, the data of the elements having element number 4n, where n=0, 1, 2, . . . , are registered, and in the vector register VRB, the data of the elements having element number 4n+1, where n=0, 1, 2, . . . , are registered.

As described before, it is assumed that vector data access requests with the indirect address method are simultaneously carried out by using a plurality of indirect addresses, for example, 4 indirect addresses in a main storage having the bank structure of, for example, 256 banks. The vector data are located at random in the main storage unit 1, and therefore, a situation can occur in which a plurality of data in question, for example data a.sub.1 and data a.sub.2, are located in the same address. In such a situation, a problem arises in that a bank conflict occurs between the accesses to the main storage, and the access for the later data (for example, data a.sub.2, if data a.sub.1 is accessed with priority to data a.sub.2) is delayed, and accordingly, the efficiency of the access operation is deteriorated.

A vector access control system according to an embodiment of the present invention is shown in FIGS. 2A and 2B. This system includes a main storage unit 1; a memory control unit 2 having a priority control unit 21, ports PA to PJ, and error correction code circuits 22; and a vector unit 3 having an instruction control portion 31, request address registers and match information registers 32, an address generation portion 33 having adders 331 to 334, an indirect address match check circuit 34, an address generation control portion 35, an access data processing portion 36, a vector register portion 37, and reading and holding registers 38. The main storage unit 1 and the memory control unit 2 are connected through request address buses AA, AB, AC, and AD and data buses DA, DB, DC, and DD. The vector register portion 37 consists of vector registers VRA, VRB, VRC, and VRD. The ports PA, PB, PC, and PD in the memory control unit 2 receive access requests from the request address registers RQAA, RQAB, RQAC, and RQAD, and the ports PMB, PMC, and PMD in the memory control unit 2 receive access requests from the match information registers MB, MC, and MD.

The instruction control portion 31 is connected with a central processor unit CPU. The ports PE and PF in the memory control unit CPU 2 are connected with the central processor unit CPU and a channel processor CHP.

Reading registers VRRA to VRRD for reading indirect address data and holding registers LAA to LAD for holding leading addresses are provided between the vector register portion 37 and the adders 331 to 334. The same data is supplied from the instruction control portion 31 to the holding registers LAA to LAD.

Each of the adders 331 to 334 adds a leading address and an indirect address data.

In the system of FIGS. 2A and 2B, the address generating portion 33 and the request address registers and match information registers 32 constitute a memory access pipeline function unit.

In the reading registers and the holding registers 38 in the system of FIGS. 2A and 2B, VRRA to VRRD are registers for reading indirect address data, and LAA to LAD are registers for holding leading addresses LA supplied from the instruction control portion 31. The same data is supplied to the holding registers LAA to LAD. Each of the adders 331 to 334 carries out the addition of a leading address and an indirect address. The request address registers and match information registers 32 include request address registers RQAA, RQAB, RQAC, and RQAD for reading indirect address data and match information registers MB, MC, and MD.

A pipeline start signal (START), a vector length signal (VL), and an instruction operation code signal (EOP), and the like, which are necessary for the memory access pipeline function, are supplied from the instruction control portion 31 to the address generation control portion 35 so that operations represented by EOP having lengths represented by VL are carried out in sequence according to the order of the elements.

The match information registers MB, MC, and MD supply match information to the memory control unit 2. The priority control circuit 21 prohibits a plurality of the same access requests, except for the first access request in a plurality of the same read access requests, by using the match information supplied by the match information registers MB, MC, and MD.

For "store" access, only the data of the last access request plurality of suppressed access requests is transmitted from the access data processing portion 36 to the memory control unit 2, using the match information. For suppressed "load" access requests the data supplied from the memory control unit 2 is distributed to the suppressed access requests by the access data processing portion 36, using the match information.

The indirect address match check circuit 34 includes coincidence circuits 341, 342, and 343, and a logic circuit 4. The structure of the logic circuit 4 is shown in FIG. 3. In the indirect address match check circuit 34, the existence of a coincidence between four indirect address data delivered from the reading registers VRRA to VRRD is detected. The match information obtained as the result of this detection is supplied to the access data processing portion 36 and the priority control circuit 21 in the memory control unit 2.

The logic circuit 4 shown in FIG. 3 includes inverters 411, 412, and 413, AND gates 421, 422, 423, 424, and 425, and OR gates 431 and 432.

The structure of the access data processing portion 36 is shown in FIG. 4. The access data processing portion 36 includes input buffer registers, selectors, and output buffer registers. The input registers receive data from the registers PG to PJ in the error correction code circuits 22 in the memory control unit 2. The selectors are controlled by the address match information MCH (A=B), MCH (A=C), MCH (B=C), MCH (A=D), MCH (B=D), and MCH (C=D) from the logic circuit 4 in the indirect address match check circuit 34. The signals from the output buffer registers are transmitted to the vector registers VRA to VRD.

In the coincidence circuits 341, 342, and 343, the coincidence between the VRRA data and VRRB data; VRRB data and VRRC data; or VRRC data and VRRD data is checked. When the coincidence is detected, a coincidence signal S (A=B), S (B=C), or S (C=D) is delivered from the coincidence circuit 341, 342, or 343.

In the logic circuit 4 of FIG. 3, predetermined relationships between data of the reading registers VRRA to VRRD are checked.

The signal S (A=B) indicating a coincidence between VRRA and VRRB is transmitted to the match information register MB; the signal S (A=B=C) or the signal S (A.noteq.B=C) is transmitted to the match information register MC; and the signal S (A=B=C=D), S (A.noteq.B=C=D), or S (B.noteq.C=D) is transmitted to the match information register MD. Also, the signals S (A=B), S (A=B=C), S (A.noteq.B=C), S (A=B=C=D), S (A.noteq.B=C=D), and S (B.noteq.C=D) are transmitted to the access data processing portion 36 to be used as control signals for the selectors.

In the priority control circuit 21, prohibition of the request signals from the vector unit is carried out by the address match information MB, MC, and MD in accordance with the condition indicated in FIG. 5. For a "load" state, PB, PC, and PD requests are prohibited in correspondence with an "ON" state of MB, MC, and MD. For a "store" state, PA, PB, and PC requests are prohibited in correspondence with an "ON" state of MB, MC, and MD.

The operation of the system of FIGS. 2A, 2B and 2C is explained with reference to FIG. 6. In FIG. 6, the first column indicates a timing sequence 1, 2, and 3; the second column indicates the state of the reading registers VRRA to VRRD; the third column indicates the element number; the fourth column indicates the result of the match check by the indirect address match check circuit 34; the fifth column indicates the processing in the access data processing portion 36 for a "load" access; and the sixth column indicates the processing in the access data processing portion 36 for a "store" access.

An example of the operation will be explained with reference to FIG. 6. At the timing 2, the condition is as follows:

This shows that the data in the main storage which is requested by element No. 6 coincides with the data in the main storage which is requested by element No. 5. Accordingly, for a "load access", the data of element No. 5 is transmitted to the vector register. Similarly, with regard to element No. 7, the data of element No. 5 is also transmitted to the vector register.

Although certain preferred embodiments have been shown and described, it should be understood that many changes and modifications may be made therein without departing from the scope of the appended claims.