BACKGROUND OF THE INVENTION
1. FIELD OF THE INVENTION
The present invention relates to a drive system for a thin-film electroluminescent (EL) matrix display panel.
2. DESCRIPTION OF THE PRIOR ART
The conventional drive circuit for a thin-film electroluminescent (EL) matrix display panel includes high-voltage N-ch MOS drivers performing pull-down function, and diodes performing pull-up function. An example of the conventional drive circuit is disclosed in Nikkei Electronics, April 2, 1979, "Practical Applications of Thin-Film Electroluminescent (EL) Character Display".
In such a conventional drive circuit, the phase relationship between the write pulse and the field refresh pulse sequentially varies depending on the scanning electrodes. And, the pre-charging voltage produces a D.C. voltage depending on whether the data side electrode is selected or is not selected. Furthermore, the amplitudes of the write voltage and the refresh pulse are asymmetrical to each other. This creates deterioration in the voltage-brightness characteristics of the alternating current driving thin-film electroluminescent (EL) matrix display panel. Therefore, the conventional drive circuit can not ensure a stable operation of the thin-film electroluminescent (EL) matrix display panel for a long time.
OBJECTS AND SUMMARY OF THE INVENTION
Objects of the Invention
Accordingly, an object of the present invention is to provide a novel drive system which ensures the stable operation of an alternating current driving capacitive type thin-film electroluminescent (EL) display panel for a long time.
Another object of the present invention is to provide a drive system for a thin-film electroluminescent (EL) matrix display panel, which minimizes deterioration of the voltage-brightness characteristics of the thin-film electroluminescent (EL) matrix display panel.
Other objects and further scope of applicability of the present invention will become apparent from the detailed description given hereinafter. It should be understood, however, that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.
SUMMARY OF THE INVENTION
To achieve the above objects, pursuant to an embodiment of the present invention, a scanning side drive circuit for a thin-film electroluminescent (EL) matrix display panel includes a P-ch MOS driver performing a pull-up function in addition to an N-ch MOS driver performing a pull-down function. The N-ch MOS driver and the P-ch MOS driver are combined with each other in a predetermined timing relationship. More specifically, the N-ch MOS driver and the P-ch MOS driver are alternately activated so that the polarity of the voltage applied to the thin-film electroluminescent (EL) matrix display panel is inverted field by field. The phase relationship between the positive and negative pulses applied to the thin-film electroluminescent (EL) display panel is fixed. Also, the amplitudes of the positive and negative pulses applied to the thin-film electroluminescent (EL) display panel are symmetrical.
A basic structure of the above-mentioned drive system is disclosed in a copending U.S. patent application, Ser. No. 664,958, "DRIVE CIRCUIT FOR A THIN-FILM ELECTROLUMINESCENT DISPLAY PANEL", filed on October 26, 1984 by Toshihiro OHBA, Yoshiharu KANATANI and Hisashi UEDE, and assigned to the same assignee as the present application. The British counterpart was filed on October 31, 1984 and assigned application No. 8427528. The German counterpart was filed on October 30, 1984, and assigned application Ser. No. P 34 39 719.1.
In accordance with a preferred form of the drive system of the present invention, a source level switching circuit is connected to the N-ch MOS driver to selectively vary the source voltage of the N-ch MOS transistors at a desired timing synchronous with the driving of the display pan.
BRIEF DESCRIPTION OF THE DRAWINGS
The present invention will be better understood from the detailed description given hereinbelow and the accompanying drawings which are given by way of illustration only, and thus are not limitative of the present invention and wherein:
FIG. 1 is a circuit diagram of an embodiment of a drive system for a thin-film electroluminescent (EL) matrix display panel of the present invention;
FIG. 2 is a timing chart showing the on-off timing of various circuit elements included in the drive system for a thin-film electroluminescent (EL) matrix display panel of FIG. 1;
FIG. 3 is a timing chart showing voltage signals applied to picture elements A and B in the thin-film electroluminescent (EL) matrix display panel of FIG. 1, and showing brightness variation at the picture elements A and B in the thin-film electroluminescent (EL) matrix display panel of FIG. 1; and
FIG. 4 is a graph showing the brightness versus applied voltage characteristics of the thin-film electroluminescent (EL) matrix display panel of FIG. 1.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
A thin-film electroluminescent (EL) matrix display panel related to the drive system of the present invention is designated 10 and includes a plurality of data side electrodes and a plurality of scanning side electrodes. N and P (first and second type) high voltage drivers are used to drive the display panel. An odd side N-ch high voltage MOS IC (integrated circuit chip) 20 is connected to the odd-number scanning electrodes, and an even side N-ch high voltage MOS IC 30 is connected to the even-number scanning electrodes. The odd side N-ch high voltage MOS IC 20 includes a logic circuit 21 such as a shift register. The even side N-ch high voltage MOS IC 30 includes a logic circuit 31 such as a shift register. An odd side P-ch high voltage MOS IC 40 is connected to the odd-number scanning electrodes, and an even side P-ch high voltage MOS IC 50 is connected to the even-number scanning electrodes. The P-ch high voltage MOS ICs 40 and 50 include logic circuits 41 and 51, respectively, such as a shift register. A data side N-ch high voltage MOS IC 60 is connected to the data side electrodes. The data side N-ch high voltage MOS IC 60 includes a logic circuit 61 such as a shift register. A data side diode array 70 is provided for separating the data side driving lines, and for protecting the switching elements from the reversed bias. The drive system of FIG. 1 includes a pre-charge driving circuit 80, a pull-up charge driving circuit 90, a write/refresh driving circuit 100, a source level switching circuit 110, and a data side refresh driving circuit 120. The source level switching circuit 110 functions to switch the source voltage of the N-ch high voltage MOS ICs 20 and 30. The source voltage is normally held at the ground level.
FIG. 2 shows the on-off timing of the circuit elements included in the drive system of FIG. 1, and FIG. 3 shows voltage signals applied to picture elements A and B included in the thin-film electroluminescent (EL) matrix display panel of FIG. 1.
An operational mode of the drive system of FIG. 1 will be described with reference to FIGS. 2 and 3. In the following explanation, a scanning side electrode Y.sub.2 including a picture element A is selected as the selected scanning side electrode. In accordance with the present invention, the polarity of the applied voltage signal is inverted field by field. The first field is referred to as the N-ch field, and the second field is referred to as the P-ch field.
N-CH FIELD
In the N-ch field, the source level switching circuit 110 connected to the scanning side N-ch high voltage MOS ICs 20 and 30 maintains the ground level.
N-ch Field First Stage T.sub.1 : Pre-Charge Period
The entire MOS transistors NT.sub.1 through NT.sub.i included in the scanning side N-ch high voltage MOS ICs 20 and 30 are placed in the ON state. At the same time, the pre-charge driving circuit 80 (voltage 1/2 V.sub.M =30 V) is switched on so as to charge the entire panel via the data side diode array 70. During the pre-charge period, the MOS transistors Nt.sub.1 through Nt.sub.j included in the data side N-ch high voltage MOS IC 60, and the MOS transistors PT.sub.1 through PT.sub.i included in the scanning side P-ch high voltage MOS ICs 40 and 50 are held in the OFF state.
N-ch Field Second Stage T.sub.2 : Discharge/Pull-Up Charge Period The MOS transistors NT.sub.1 through NT.sub.i included in the scanning side N-ch high voltage MOS ICs 20 and 30 are switched OFF. One of the MOS transistors included in the data side N-ch high voltage MOS IC 60 and connected to a selected data side driving electrode (for example, X.sub.2) is maintained off, and the remaining MOS transistors included in the data side N-ch high voltage MOS IC 60 are switched ON. Further, the MOS transistors PT.sub.1 through PT.sub.i included in the scanning side P-ch high voltage MOS ICs 40 and 50 are switched ON. The charges on the non-selected data side electrodes are discharged through a grounded loop formed, in combination, by the MOS transistors (other than Nt.sub.2) included in the data side N-ch high voltage MOS IC 60, MOS transistors PT.sub.1 through PT.sub.i included in the scanning side P-ch high voltage MOS ICs 40 and 50, and a diode 101 included in the write/refresh driving circuit 100. Thereafter, the pull-up charge driving circuit 90 (voltage 1/2 V.sub.M =30 V) is switched ON so as to pull each of up the scanning side electrodes to 30 V. At this stage, the MOS transistors NT.sub.1 through NT.sub.i included in the scanning side N-ch high voltage MOS ICs 20 and 30 remain off. Consequently, when observed from the scanning side electrodes (Y), the selected data side electrode (X.sub.2) is +30 V with respect to the scanning side electrodes, and the non-selected data side electrodes are -30 V with respect to the scanning side electrodes.
N-ch Field Third Stage T.sub.3 : Write-In Drive Period
Only one MOS transistor NT.sub.2 included in the scanning side N-ch high voltage MOS IC 30 and connected to the selected scanning side electrode Y.sub.2 is switched ON, and the MOS transistors PT.sub.2 through PT.sub.i included in the even side P-ch high voltage MOS IC 50 are switched OFF. The MOS transistors PT.sub.1 through PT.sub.i-1 included in the odd side P-ch high voltage MOS IC 40 are held at the ON state. The write/refresh driving circuit 100 (V.sub.W = 190 V) is switched on so that all of the odd number scanning side electrodes are pulled up to +190 V via the entire MOS transistors PT.sub.1 through PT.sub.i-1 included in the odd side P-ch high voltage MOS IC 40. Due to the capacitive coupling, the selected data side driving electrode is pulled up to +220 V (=V.sub.W +1/2 V.sub.M), and the non-selected data electrodes are pulled up to +160 V (=V.sub.W -1/2 V.sub.M).
In the case where one of the odd number scanning side electrodes is selected, the MOS transistors PT.sub.2 through PT.sub.i included in the even side P-ch high voltage MOS IC 50 are switched on so as to pull up all of the even number scanning side electrodes to +190 V. The above-mentioned three-staged driving is sequentially conducted for each of the scanning side electrodes Y.sub.1 through Y.sub.i. Then, a refresh driving is carried out during a blanking period provided before the following P-ch field.
N-ch Field Refresh Period RF
All of the MOS transistors included in the scanning side N-ch high voltage MOS ICs 20 and 30 are held in the OFF state, while all of the MOS transistors included in the data side N-ch high voltage MOS IC 60 and the scanning side P-ch high voltage MOS ICs 40 and 50 are switched ON to pull-down the data side driving electrodes to the ground level. The write/refresh driving circuit 100 is switched ON to pull-up the scanning side driving electrodes to the voltage level V.sub.W (=190 V). A refresh pulse (1) having a polarity opposite to the write pulse in the N-ch field is applied to all the picture elements. Thereafter, all the MOS transistors included in the scanning side P-ch high voltage MOS ICs 40 and 50 and the data side N-ch high voltage MOS IC 60 are switched OFF, and the MOS transistors NT.sub.1 through NT.sub.i included in the scanning side N-ch high voltage MOS ICs 20 and 30 are switched ON so as to pull down all of the scanning side electrodes to the ground level. The data side refresh driving circuit 120 is switched ON so that all of the data side driving electrodes are pulled up to the voltage level V.sub.W (=190 V) via the data side diode array 70. A refresh pulse (2) having the same amplitude but the opposite polarity to the refresh pulse (1) is applied to the entire picture elements.
Due to the polarization effect produced in the thin-film electroluminescent (EL) matrix display panel, the picture elements at which the electroluminescence has occurred during the writing operation produce the electroluminescence in response to the application of the refresh pulses (1) and (2). Although two refresh pulses are applied to the panel in the above embodiment, even one refresh pulse (1) having the polarity opposite to that of the writing pulse can perform a desirable refreshing operation. After completion of the refresh driving, the P-ch field drive is carried out.
P-ch FIELD
P-ch Field First Stage T.sub.1 ': Pre-Charge Period
The pre-charge operation is conducted in the same manner as the N-ch Field First Stage T.sub.1.
P-ch Field Second Stage T.sub.2 ': Discharge/Pull-Up Charge Period
The MOS transistors NT.sub.1 through NT.sub.i included in the scanning side N-ch high voltage MOS ICs 20 and 30 are switched OFF. The MOS transistor (for example, Nt.sub.2) included in the data side N-ch high voltage MOS IC 60 and connected to the selected data side driving electrode is maintained at the ON state, and the remaining MOS transistors included in the data side N-ch high voltage MOS IC 60 are switched OFF. At the same time, the MOS transistors PT.sub.1 through PT.sub.i included in the scanning side P-ch high voltage MOS ICs 40 and 50 are switched ON. Charges on the selected data side electrode are discharged through a grounded loop formed, in combination, by the on state MOS transistor Nt.sub.2 included in the data side N-ch high voltage MOS IC 60, the MOS transistors PT.sub.1 through PT.sub.i included in the scanning side P-ch high voltage MOS ICs 40 and 50, and the diode 101 included in the write/refresh driving circuit 100. Thereafter, the pull-up charge driving circuit 90 is switched ON to pull up the entire scanning side electrodes (Y) to 30 V (=1/2 V.sub.M). At this stage, the MOS transistors NT.sub.1 through NT.sub.i included in the scanning side N-ch high voltage MOS ICs 20 and 30 remain OFF. Consequently, when observed from the scanning side electrodes (Y), the selected data side electrode (X.sub.2) is -30 V, and the non-selected data side electrodes are +30 V.
P-ch Field Third Stage T.sub.3 ': Write-In Drive Period
Only the MOS transistor PT.sub.2 included in the scanning side P-ch high voltage MOS IC 50 and connected to the selected scanning side electrode Y.sub.2 is held in the ON state, and the remaining MOS transistors included in the scanning side P-ch high voltage MOS IC 50 are switched OFF. The MOS transistors NT.sub.2 through NT.sub.i included in the even side scanning N-ch high voltage MOS IC 30 are maintained OFF, and the MOS transistors NT.sub.1 through NT.sub.i-1 included in the odd side scanning N-ch high voltage MOS IC 20 are switched ON. The write/refresh driving circuit 100 is switched ON so that the selected scanning side electrode Y.sub.2 receives a voltage of 220 V (=V.sub.W (190 V) +1/2 V.sub.M (30 V)) via the on state MOS transistor PT.sub.2. At this stage, the source level switching circuit 110 is switched to 30 V (=1/2 V.sub.M). The source voltage applied to the odd side scanning N-ch high voltage MOS IC 20 is 30 V, whereby the odd number scanning electrodes are pulled down to +30 V. Due to the capacitive coupling, the selected data side driving electrode X.sub.2 is pulled down to -220 V, and the non-selected data side electrodes are pulled down to -160 V.
In the case where one of the odd number scanning electrodes is selected, the MOS transistor included in the scanning side P-ch high voltage MOS IC 40 and connected to the selected scanning electrode, and the MOS transistors NT.sub.2 through NT.sub.i included in the scanning side N-ch high voltage MOS IC 30 are switched ON. The above-mentioned three-staged driving is sequentially conducted for each of the scanning side electrodes Y.sub.1 through Y.sub.i.
P-ch Field Refresh Period RF'
All of the MOS transistors included in the scanning side P-ch high voltage MOS ICs 40 and 50 and the scanning side N-ch high voltage MOS ICs 20 and 30 are switched ON so as to pull down the scanning side driving electrodes to the ground level. The data side refresh driving circuit 120 is switched ON so as to pull up each of the data side driving electrodes to the voltage level of V.sub.W (=190 V) via the data side diode array 70. A refresh pulse (1)' having a polarity opposite to the write pulse in the P-ch field is applied to all of the picture elements. Thereafter, all of the MOS transistors included in the data side N-ch high voltage MOS IC 60 and the scanning side P-ch high voltage MOS ICs 40 and 50 are switched ON so as to pull down the data side driving electrodes to the ground level. The write/refresh driving circuit 100 is switched ON so that the scanning side driving electrodes are pulled up to the voltage level V.sub.W (=190 V). A refresh pulse (2)' having the same amplitude and the opposite polarity to the refresh pulse (1)' is applied to all of the picture elements. As in the case of the N-ch field, the refresh driving of only one refresh pulse (1)' can produce a similar brightness.
The above-mentioned N-ch field drive and the P-ch field drive are alternately conducted. The selected picture element receives the opposing two write-in voltages each having the amplitude of 220 V (=V.sub.W +1/2 V.sub.M) at the N-ch field and the P-ch field. Further, the selected picture element emits the electroluminescence in response to the application of the refresh voltage of 190 V. That is, the selected picture element performs the electroluminescence at least four times in one cycle of driving including the N-ch field and the P-ch field. In the above-mentioned embodiment, the two refresh pulses are applied in each field. That is, the alternating cycle is completed by the refresh pulse itself. Of course, the entire driving includes symmetrical pulses. That is, the panel driving completes the alternating cycle by the combination of the N-ch field and the P-ch field. The non-selected picture element receives the voltage of 160 V (=V.sub.W -1/2 V.sub.M) and the refresh pulse of 190 V. However, the non-selected picture element does not produce the electroluminescence because the write-in voltage is less than the threshold level.
Although the refresh pulses are applied to the entire panel in the foregoing embodiment, the refresh driving is not necessarily required to achieve the alternating current driving. The refresh driving is effective only to enhance the brightness. FIG. 4 shows a comparative brightness when the refresh pulse is applied to the entire panel in the drive system of the present invention, and when the refresh pulse is not applied to the entire panel in the drive system of the present invention.
The invention being thus described, it will be obvious that the same may be varied in many ways without departure from the spirit and scope of the invention, which is limited only by the following claims.