US 4,864,528 AGrant
Arithmetic Processor and Multiplier Using Redundant Signed Digit Arithmetic
Issue Date:1989-09-05
•24 Claims
•14 Drawing Sheets
Abstract
A high speed processor including a multiplier is disclosed. The multiplier includes a multiplier recorder circuit which may record multipliers in groups of digits, and intermediate partial product generators which generate partial products from the recorded digits and a multiplicand. Addition/subtraction is then carried out on the intermediate partial products generated by the partial product generators. The processor may operate using signed digit expressions.
Metadata
Assignee
- Matsushita Electric Industrial Co., Ltd.
Inventors
- Tamotsu Nishiyama
- Shigeo Kuninobu
- Naofumi Takagi
- Takashi Taniguchi
Application Information
Application Number:US 0749710
Filing Date:1987-07-17
Priority Date:1986-07-18
Art Unit:231
Classifications
IPC:
G06F 749G06F 752
Field of Search:
364754;760;761;768
Patent Drawings (14 sheets)
Description
Background of the Invention
The present invention relates to an arithmetic processor and, more particularly, to a high speed arithmetic processor and multiplier thereof which provides multiplication for internal arithmetic operations, and may be implemented by LSI.
A high speed binary multiplier utilizing a redundant binary adder tree is discussed on pages 683 to 690 of Trans. of IECE Japan, Vol. J66-D, No. 6 (1983). That multiplier utilizes a redundant binary expression (a kind of signed digit ("SD") expression) in which each digit is represented by an element of the set {-1, 0, 1}. In n-bit multiplication, n n-bit partial products, considered as redundant binary numbers, are added by partial trees in units of two in the redundant binary number system, and the product which is obtained as a redundant binary expression is converted to an ordinary binary expression. In the redundant binary number system, addition of two numbers without carry-propagation can be performed within a predetermined time irrespective of the number of digits to be added. Accordingly, a multiplier utilizing redundant binary adder trees is capable of executing n-bit multiplication at high speed in the computation time of log n. Computation speed is as high as that of a high speed multiplier utilizing Wallace trees, and is considerably higher than a prior art array multiplier. In addition, a regular array circuit structure is utilized, as in the case of an array multiplier, and with a simpler fan out arrangement than a multiplier using Wallace trees.
Use of the 2-bit Booth method reduces hardware requirements in the multiplier described above. In the 2-bit Booth method, the number of partial products may be reduced by almost half by recoding the multiplier in the quaternary signed digit number system, in which each digit is represented by an element of the set {-2, -1, 0, 1, 2}, which provides high speed operation and reduces the amount of hardware required. However, double folding of the multiplicand, which folding may be realized by left-shifting one bit, and inversion of positive and negative signs are necessary to generate a partial product. The inversion of positive and negative signs may be executed by obtaining a 2's complement binary number or by setting the "1" digits of the multiplicand to "-1" using the fact that inversion of positive and negative redundant binary numbers can be realized by inversion of the positive and negative signs of each digit.
Although the multiplier can easily generate a partial product, since each digit of the partial product may be positive (e.g., "1"), zero ("0") or negative (e.g., "-1"), it has been necessary to form all stages of the adder tree with the same ordinary redundant binary adder cells. No consideration, however, has been given to practical problems in the implementation of the multiplier, such as reducing the large number of elements (about 50 transistors) required, simplifying circuit structure in view of the large number of individual cells needed to form a redundant binary adder, and the difficulty in implementing the cells utilizing combinational circuitry since the number of elements required increases with the number of digits involved in the arithmetic operations which in turn requires complicated circuit structures.
Objects and Summary of the Invention
It is an object of the present invention to provide a high speed arithmetic processor and multiplier thereof which avoid the problems described above.
It is another object of the present invention to provide a high speed arithmetic processor and a multiplier thereof utilizing combinational circuitry.
It is another object of the present invention to reduce the number of elements (e.g., transistors) in a multiplier.
It is another object of the present invention to provide a multiplier which prevents carry-propagation in arithmetic addition and subtraction.
It is another object of the present invention to provide a multiplier which may be fabricated on an LSI chip.
It is another object of the present invention to provide a multiplier having a reduced number of stages of gates through simplification of circuit structure.
According to the present invention, an arithmetic processor is provided comprising first generating means for generating first intermediate partial products from a first group comprising a plurality of digits of a multiplier and a multiplicand, second generating means for generating second intermediate partial products from a second group comprising a plurality of digits of the multiplier and the multiplicand, and third generating means for generating partial products from intermediate partial products generated by the first and second generating means. The first group may comprise substantially half of the digits of the multiplier and the multiplicand, and the second group may comprise substantially the other half of the digits of the multiplier and the multiplicand. For example, the first group may comprise even digits and the second group odd digits.
The first generating means may comprise a first multiplier recoder means and a first partial product generating means for generating the first partial products as signed digit expressions in which each digit is nonnegative. The second generating means may comprise second multiplier recoder means and second partial product generating means for generating the second partial products as signed digit expressions in which each digit is nonpositive. The third generating means may comprise means for generating the partial products from the first and second partial products as signed digit expressions where each digit may have any positive, zero, or negative value.
According to one embodiment of the present invention, a multiplier to be processed is divided into parts, each part comprising, for example, two digits. The first recoder means recodes half of the parts into which the multiplier is divided, while the second recoder means recodes the remaining half of the multiplier parts in such a manner that the positive and negative signs of the multiplier parts are inverted from each other as recoded in the first and second recoder means. Upon generating each partial product, subtraction is carried out between the first partial product generated from the digits of the multiplier recoded by the first recoder means and the second partial product generated from the digits of the multiplier recoded by the second recoder means, and a sum of the partial products is obtained, specifically, a partial product of four digits of the multiplier is obtained in the form of a signed digit number each digit of which may have any negative, zero or positive value.
Processing proceeds as follows. First, an intermediate first partial product and a second partial product are generated corresponding to the first recoder means and the second recoder means, respectively, by the partial product generating means, where the multiplier recoded in the second recoder means is obtained through inversion of the positive and negative signs of the multiplier recoded in the first recoder means. Next, a partial product is generated in the form of a signed digit expression through subtraction between the intermediate first and second partial products. Since both first and second partial products are nonnegative, the subtraction between such first and second partial products does not generate a carry (or borrow), i.e., in redundant subtraction (namely subtraction in which the subtraction result is expressed by a signed digit expression with redundancy). A subtraction circuit for carrying out such subtraction may be formed by simple circuit structure. Accordingly, the number of partial products may be reduced to about half in comparison with those in the 2-bit Booth method.
In addition, an adder tree utilizing adders in the signed digit expression system may be used for addition of the partial products, and thereby processing time may be reduced.
Further in accordance with the invention, signed digit expressions in which the digits may have any negative, zero or positive value are used for arithmetic operations, and an arithmetic processor is provided comprising means for recoding a multiplier as a signed digit number, and means for generating partial products as signed digit number expressions, each digit of which may have any positive, zero or negative value, from two digits of a multiplier recoded in said recoding means and a multiplicand which is a signed digit number expression.
In one embodiment, a first means generates a first partial product as a signed digit expression each digit of which except for the most significant digit is nonnegative, and a second means generates a second partial product as a signed digit expression each digit of which except for the most significant digit is nonpositive. The first partial product generated by the first means and second partial products generated by the second means from a partial product or pair which are added together.
According to another embodiment, signed digit numbers each digit of which has a nonnegative value, i.e. zero or positive, are used for arithmetic operations, and the processor generates a partial product as a signed digit expression from two digits of a multiplier recoded as a signed digit expression and a multiplicand. An intermediate partial product corresponding to the lower of the two digits is generated by inverting the sign of each digit of the multiplicand when the lower digit is negative. An intermediate partial product corresponding to the upper of the two digits is generated by inversion of the sign of each digit of the multiplicand or a 2's complement binary number operation when the sign of the most significant digit of the higher digit is different from the sign of most significant digit of the lower digit. The partial product is generated as a signed digit number expression by adding these intermediate partial products. A supplementary term (e.g., 1) generated during generation of the intermediate partial product corresponding to the upper of the digits is considered as a part of the partial product thereof, and is added in succeeding stages, (e.g. in the higher order stages of an adder tree).
Brief Description of the Drawings
FIG. 1 is a block diagram of a multiplier according to one embodiment of the present invention.
FIG. 2 is a circuit diagram of a circuit which forms the even portion of the multiplier recoder circuit of the multiplier depicted in FIG. 1.
FIG. 3 is a circuit diagram of the circuit which forms the odd portion of the multiplier recoder circuit of the multiplier depicted in FIG. 1.
FIG. 4 is a circuit diagram of an intermediate partial product generator of the multiplier depicted in FIG. 1.
FIG. 5 is a circuit diagram of the redundant subtraction unit of the multiplier depicted in FIG. 1.
FIG. 6 is a circuit diagram of an addition cell of the redundant addition unit of the multiplier depicted in FIG. 1.
FIG. 7 is a block diagram of a multiplier according to another embodiment of the invention.
FIG. 8 is a circuit diagram of a multiplier recoder circuit of the multiplier of FIG. 7.
FIG. 9 is a circuit diagram of the partial product generating circuit of the multiplier of FIG. 7.
FIG. 10 is a circuit diagram of an addition cell of the redundant addition circuit of the multiplier depicted in FIG. 7.
FIG. 11 is a block diagram of still another embodiment of a multiplier according to the present invention.
FIG. 12 is a circuit diagram of a multiplier recorder circuit of the multiplier depicted in FIG. 11.
FIG. 13 is a circuit diagram of a cell forming part of the even partial product generator of the multiplier depicted in FIG. 11.
FIG. 14 is a circuit diagram of a first stage addition cell.
FIG. 15 is a circuit diagram of a second and successive stage addition cell .
Description of the Preferred Embodiments
FIG. 1 depicts an embodiment of an 8-bit.times.8-bit multiplier according to the present invention which includes multiplier recoder circuit 100, intermediate partial product generators 110, redundant subtraction units 120, redundant addition unit 130 and redundant binary/binary converter 140.
Multiplier recoder circuit 100 recodes digits of a multiplier in a quaternary code in which each digit may be expressed as an element of the set {-2, -1, 0, 1, 2} according to an improved 2-bit Booth method.
Alternating even and odd intermediate partial product generators 110 receive digits of multipliers recoded by multiplier recoder circuit 100 and a multiplicand, and generate intermediate partial products.
Redundant subtraction units 120 subtract a partial product (having nonnegative digits) generated by an odd, i.e., the (2k+1)th, intermediate partial product generator 110 adjacent thereto from a partial product generated by an even, i.e., the (2k)th (including 0), intermediate partial product generator 110, and outputs the difference in the form of a redundant binary number in which each digit may be expressed as an element of the set {-1, 0, 1}.
Redundant adder 130 forms an adder tree and executes addition in the redundant binary system for ordinary redundant binary numbers.
Redundant binary/binary converter 140 converts a redundant binary number obtained as a product into a binary number, and may be implemented by carry, look-ahead circuitry.
The following is a description multiplier recoder circuit 100.
A multiplier Y can be expressed in a 2's complement binary number expression by the following; ##EQU1## where y.sub.n is a sign bit, and y.sub.n-1, . . . , y.sub.1 are magnitude bits. For simplification, if Y is considered as an even number, then: ##EQU2## where y.sub.0 =0. The multiplication of X, Y can be expressed by the following arithmetic expression. ##EQU3## The intermediate partial product may be expressed by ##EQU4## when j is even number (including 0), or by ##EQU5## when j is an odd number. The final partial product can be obtained by subtraction between the intermediate partial product expressed above when j is even number and the intermediate partial product expressed above when j is odd number. Accordingly the multiplier recoder circuit 100 recodes multipliers as quaternary signed digit numbers in which each digit b.sub.j may be expressed by any one of the elements of the set {-2, -1, 0, 1, 2}, as represented by the arithmetic expression
when j is even number, or by the arithmetic expression
when j is odd number.
A description of the quaternary coding system and binary signals representing same follows, after which the circuits depicted in FIGS. 2 and 3 which form part of the multiplier recoder circuit 100 of FIG. 1 are described. The digit b.sub.j of a recoded multiplier in the quaternary code may be expressed by the 3-bit binary signal b.sub.j.sup.s, b.sub.j.sup.2, b.sub.j.sup.1 according to Table 1.
As described above, when the quaternary code signal is converted to a binary signal, the j-th digit b.sub.j of the multiplier recoded in the multiplier recode circuit 100 is determined by the following expressions, where, j is an integer ranging from 0 to n/2-1.
(i) When j is even (namely, j=2k): ##EQU6##
(ii) When j is odd (namely, j=2k+1): ##EQU7##
When j=0, the above expressions may be simplified as follows.
b.sub.0.sup.s =y.sub.2,
b.sub.0.sup.2 =y.sub.2 y.sub.1,
b.sub.0.sup.1 =y.sub.1
In the above expressions, "." represents the logical product (AND), "+" represents the logical sum (OR), ".crclbar." represents the exclusive logical sum (EX-OR), and "--" represents logical inverse or negation (not).
FIGS. 2 and 3 depict embodiments of circuits forming the even digit portion and odd digit portion, respectively, of the multiplier recoder circuit 100 of FIG. 1. The circuit illustrated in FIG.2 generates the even digits b.sub.2k of a recoded multiplier and the circuit illustrated in FIG. 3 generates the odd digits b.sub.2k+1 of a recoded multiplier.
In the signals represented in FIG. 2, j is an even number (for example, 2k, where k is 0 or a positive integer). In the circuit of FIG. 2, gate 211 is an inverter, gate 212 is NAND gate, gate 221 is an AND-NOR composite gate, gate 222 is an OR-NAND composite gate, and gate 223 is an exclusive OR gate. Signals 201 (y.sub.2j+2), 202 (y.sub.2j+1), and 203 (y.sub.2j) are 1-bit binary signals representing the (2j+2)th digit, (2j+1)th digit and (2j)th digit, respectively, of the multiplier Y, j being an even number as indicated above. Output signals 231 (b.sub.j.sup.s), 232 (b.sub.j.sup.2), 233 (b.sub.j.sup.1) form a 3-bit signal representing the (j)th digit b.sub.j of the recoded multiplier. Signal b.sub.j.sup.2 (232) is provided by the circuit formed by OR-NAND composite gate 222, inverter 211 and NAND gate 212, while signal b.sub.j.sup.1 (233) is provided by exclusive OR gate 223 and signal b.sub.j.sup.s (231) is provided by the circuit formed by the AND-NOR composite gate 221 and inverter 211.
In the signals represented in FIG. 3, j is an odd number (for example, 2k+1 where k is 0 or a positive integer). In FIG. 3, gate 261 is an inverter, gate 262 is an NAND gate, gate 272 is a composite OR-NAND gate and gate 273 is an exclusive OR gate, similar to inverter 211, NAND gate 212, OR-NAND composite gate 222 and exclusive OR gate 223, respectively, shown in FIG. 2. Gates 263 and 271 are NOR gates. Signals 251 (y.sub.2j+2), 252 (y.sub.2j+1), 253 (y.sub.2j) are 1-bit binary signals representing the (2j+2)th digit, (2j+1)th digit and (2j)th digit, respectively, of the multiplier Y, j being an odd number. Output signals 281 (b.sub.j.sup.s), 282 (b.sub.j.sup.2), 283 (b.sub.j.sup.1) form a 3-bit signal representing the (j)th digit b.sub.j of the recoded multiplier. In FIG. 3, the circuit which determines the signals b.sub.j.sup.2 (282) and b.sub.j.sup.1 (283) is similar to that illustrated in FIG. 2, but signal 281 (b.sub.j.sup.s) is determined by the circuit formed by NOR gates 263 and 271.
The intermediate partial product generators 110 are described next. Intermediate partial products may have a value -2X, -X, 0, X, 2X in accordance with the value of b.sub.j, where weighting by 2.sup.j has been omitted and 2X means twice the multiplicand. Twice the multiplicand X can be realized by a shift of one bit and can be formed easily with combinational circuits. Inversion of positive and negative signs results in the inversion of X, i.e., the logical NOT X or X (for each digit) due to the 2's complement binary number expression and addition of 1 to the least significant digit of X. However, if 1 is added in the intermediate partial product generator 110, hardware requirements increase and processing time is lengthened. Therefore, 1 is added to the least significant digit of X, not in the intermediate partial product generator 110, but in adders (redundant addition units 130) for successive partial products. Thereby, an increase in hardware is prevented and high speed operation is realized. In addition, other computations are carried out earlier including supplementation (i.e., addition of 1) to the lower order digits in the intermediate partial product generator 110 to facilitate adding the supplementary term 1 in redundant addition unit 130. In practice, the least significant digit is computed in intermediate partial product generator 110 and supplementation (addition of 1) is carried out with respect to the second lowest order digit.
In that case, the (i)th digit of the intermediate partial product corresponding to the (j)th digit b.sub.j of the recorded multiplier is determined by the following expressions: ##EQU8## where c.sub.2 denotes a supplementary term to be added to the second digit which is added in the adder tree. The suffix j has been omitted from z.sub.1, z.sub.i, c.sub.2.
FIG. 4 depicts a circuit for determining each of the intermediate digits (i.e., the second digit to the (n)th digit) of the intermediate partial product in intermediate partial product generator 110 of FIG. 1. As depicted in FIG. 4, the circuit determines the (i)th digit z.sub.i between the second digit and the (n)th digit of the intermediate partial product corresponding to the (j)th digit b.sub.j of the recorded multiplier. In FIG. 4, gate 411 is an AND-NOR composite circuit and gate 421 is an exclusive NOR gate. Signals 401 (b.sub.j.sup.5), 402 (b.sub.j.sup.2) and 403 (b.sub.j.sup.1) form a 3-bit binary signal which represent (j)th digit of the recoded multiplier, where j is an integer between 0 and n/2-1. Output signal 431 (z.sub.i) is a 1-bit binary signal representing the (i)th digit of the intermediate partial product, where i is an integer from 1 to n. Circuits for generating z.sub.1, z.sub.n+1 and c.sub.2 may similarly be easily formed.
Redundant subtraction unit 120 is described next. A value obtained by subtracting the intermediate partial product corresponding to the odd digits b.sub.2k+1 from the intermediate partial product corresponding to the even digits b.sub.2k of the recoded multiplier may be expressed as a redundant binary number, and carry (borrow) propagation may be eliminated during subtraction. As a result, a very simple circuit may be provided to carry out subtraction.
The digits r.sub.i of a redundant binary number are expressed by the 2-bit binary signal r.sub.i.sup.s, r.sub.i.sup.a shown in Table 2 below, according to which the (i)th digit of the subtraction carried out in the redundant subtraction unit 120 may be determined.
The (i)th digits r.sub.i of the subtracted value are determined by the following expressions for the (i)th digits z.sub.i of the intermediate partial products corresponding to the even digits b.sub.2k and the (i-2)th digits w.sub.i-2 of the intermediate partial products corresponding to the odd digits b.sub.2k+1 : ##EQU9## or by the following expressions: ##EQU10## for i=3.about.n+2. The (i-2)th digits w.sub.i-2 of the intermediate partial products for the odd digits b.sub.2k+1 are subtracted from the (i)th digit z.sub.i of the intermediate partial products for the even digits b.sub.2k because the digits for even b.sub.j are offset by two digits (i.e., the weighting of 2.sup.2) from the digits for odd b.sub.j. Moreover, z.sub.n+3, z.sub.n+2 are determined as z.sub.n+3 =z.sub.n+1 ; z.sub.n+2 =z.sub.n+1.
FIG. 5 depicts an embodiment of a subtraction circuit forming part of redundant subtraction unit 120 of FIG. 1 which executes subtraction between a minuend z.sub.i and subtrahend w.sub.i for each digit i. In FIG. 5, gate 511 is a NAND gate, a gate 521 is an inverter and a gate 522 is an OR-NAND composite circuit. Signal 501 (z.sub.i) is a 1-bit signal which represents the logical inverse of the (i)th digit z.sub.i of the intermediate partial product of the even number (i.e., corresponding to b.sub.2k). Signal 502 (w.sub.i) is a 1-bit signal which represents the (i-2)th digit of the intermediate partial products of the odd number (i.e., corresponding to b.sub.2k+1). Since a subtrahend w.sub.i is always 0 for i=1, 2, a minuend z.sub.i may be used as the subtraction result. Moreover, when i=n+3, the subtraction circuit of FIG. 5 may also be operated by interchanging the minuend z.sub.i and subtrahend w.sub.i of the input signal. Output signals 531 (r.sub.i.sup.s) and 532 (r.sub.i.sup.a) form a 2-bit binary signal which represents the (i)th digit r.sub.i of the subtraction value namely the partial product (i.e., a redundant binary number) for each 4-bits of a multiplier. Alternatively, the subtraction circuit may be formed by a 2-input NOR gate and an exclusive NOR gate in place of the circuit of FIG. 5. Here, the logical inverse signal z.sub.i (501) of the digits z.sub.i of the intermediate partial products of FIG. 5 may be obtained easily without increasing the number of transistor gates by replacing the exclusive NOR gate 421 of FIG. 4 with an exclusive OR gate.
Addition of the supplementary term in even numbered partial products (i.e., corresponding to b.sub.2k) facilitates addition in an adder tree when computed at the same time as the redundant subtraction. Addition of the second digit z.sub.2 of even numbered intermediate partial products and the supplementary term c.sub.2 is determined by the following expressions: for the second digit of the intermediate partial products
r.sub.2.sup.s =0,
r.sub.2.sup.a =x.sub.2 .sym.c.sub.2,
and for the supplementary term t.sub.3 to the third digit (i.e., carry)
t.sub.3.sup.s =0,
t.sub.3.sup.a =x.sub.2 -c.sub.2.
The supplementary term t.sub.3 and the supplementary term c.sub.2 to the second digit of each odd-numbered intermediate partial product are easily added to partial product, respectively, in an adder tree. However, since odd-numbered intermediate partial products are subtracted from even-numbered partial products, the supplementary term thereof becomes -c.sub.2 instead of c.sub.2.
A redundant adder 130 which forms the adder tree will be described next.
Addition in which carry propagation in the redundant adder 130 is 1 digit at most is carried out in accordance with Table 3.
The signal P.sub.i, which indicates combination of the (i)th digit x.sub.i of the augend and the (i)th digit y.sub.i of the addend, is introduced in the form
The variables u.sub.i, v.sub.i, are introduced by the following arithmetic expressions,
The variables u.sub.i, v.sub.i are related to the intermediate carry c.sub.i and the intermediate sum digit s.sub.i respectively in Table 3. The variables u.sub.i, v.sub.i and an absolute value s.sub.i.sup.a of intermediate sum digit s.sub.i, are determined by the following expressions: ##EQU11##
The final sum z.sub.i represented by a 2-bit signal z.sub.i.sup.s, z.sub.i.sup.a is determined by the following expressions:
FIG. 6 is a circuit diagram of an embodiment of an addition circuit forming redundant addition unit 130 of FIG. 1. In FIG. 6, gate 311 is a NOR gate, gates 312 and 351 are NAND gates, gate 313 is an exclusive OR gate, gate 332 is an exclusive NOR gate, gate 353 is an inverter, gate 331 is AND-NOR composite circuit, gate 352 is an OR-NAND composite circuit.
Signals 301 (x.sub.i.sup.s) and 302 (x.sub.i.sup.a) FIG. 6 form a 2-bit signal which indicates the (i)th digit x.sub.i of the redundant binary number as the augend. Signals 303 (y.sub.i.sup.s) and 304 (y.sub.1.sup.a) form a 2-bit signal which indicates the (i)th digit y.sub.i of the redundant binary number as the addend. Output signal 321 (P.sub.i) is a 1-bit signal which indicates the state of said augend and addend at the (i)th digit. Signal 322 (S.sub.i.sup.a) is a 1-bit signal which indicates the absolute value of the intermediate sum digit of the (i)th digit. Output signal 341 (v.sub.i) is a 1-bit signal which indicates the intermediate carry at the (i)th digit. Signal 343 (v.sub.i-1) is a 1-bit signal which indicates the intermediate carry at the (i-1)th digit. Signal 342 (u.sub.i) is the logical inverse of the signal u.sub.i which indicates the intermediate sum digit at the (i)th digit. Output signals 361 (z.sub.i.sup.s) and 362 (z.sub.i.sup.a) form a 2-bit signal which indicates the (i)th digit of the final sum.
In the embodiment of FIG. 1, a partial product is generated by subtracting the odd numbered intermediate partial products from the even numbered intermediate partial products. However, a partial product may be generated by subtracting the even numbered intermediate partial products from the odd numbered intermediate partial products.
For example, the arithmetic expressions given above for the product of the multipliers XY may be transformed as indicated below. ##EQU12##
Sign (X) is a function which becomes 1 when X is positive or zero, and -1 when X is negative, and .vertline.X.vertline. is the absolute value of X.
In the above arithmetic expressions,
represents a subtraction between two terms; when S.sub.k =1, the second term (the odd numbered intermediate partial products) is subtracted from the first term (the even numbered intermediate partial products), and when S.sub.k =-1, the reverse is true, i.e., the first term is subtracted from the second term. In that case, since E.sub.k may have any value from the elements in the set {0, 1, 2}, E.sub.k X is always nonnegative. However, since F.sub.k may have any value from the elements in the set {-2, -1, 0, 1, 2}, F.sub.k X2.sup.2 may sometimes be negative. On the other hand, utilizing the 2's complement binary number expression, each digit of F.sub.k X2.sup.2 is nonnegative.
Since the even numbered intermediate partial products can not be expressed as a 2's complement binary number, the 2's complement binary number and supplementation by adding +1, as described above, may be used only in the generation of the odd numbered intermediate partial products where the addition of the supplementary term can be realized easily. Moreover, subtraction of these two terms can also be interpreted as the addition of a redundant binary number having only nonnegative digits and a redundant binary number having only nonpositive digits.
FIG. 7 illustrates another embodiment of a multiplier according to the present invention. The multiplier of FIG. 7 has basically the same structure as the multiplier of FIG. 1, and combines two intermediate partial product generators 110 and the related redundant subtraction unit 120 of FIG. 1 into respective partial product generators 122 and 123. The multiplier of FIG. 7 generates the partial product of a redundant binary number from two consecutive digits of the recoded multiplier. The multiplier recoder circuit 100, the redundant addition unit 130 and redundant binary/binary converter 140 illustrated in FIG. 7 are respectively equivalent to the multiplier recoder circuit 100, redundant addition unit 130 and redundant binary/binary converter 140 illustrated in FIG. 1.
Multiplier recoder circuit 100 in FIG. 7 recodes each digit in the same manner and does not discriminate between even and odd digits of the recoded multiplier, unlike the multiplier of FIG. 1. For example, both the even digit portion and odd digit portion of multiplier recoded circuit 100 in FIG. 7 may be formed by the circuit illustrated in FIG. 2.
According to the embodiment of FIG. 7, the digits b.sub.j of the recoded multiplier may be expressed by the 3-bit binary signal composed of bits b.sub.j.sup.s, b.sub.j.sup.2, b.sub.j.sup.1, as indicated in Table 4.
The (i)th digit R.sub.i of the recoded multiplier may be expressed by the following expressions using the binary encoding of Table 4. ##EQU13##
FIG. 8 is an embodiment of a circuit which forms part of the multiplier recoder circuit 100 of FIG. 7. In FIG. 8, signals y.sub.2i+2, y.sub.2i+1 and y.sub.2i are input signals respectively representing the 2i+2, 2i+1 and 2i digits of the multiplier Y, and output signals b.sub.j.sup.s, b.sub.j.sup.1 and b.sub.j.sup.2, representing digits of the recoded multiplier, are generated from those signals by inverter 211, NAND gate 212, EX-OR gate 223 and OR-NAND composite circuit 222 in a manner similar to that described in connection with FIG. 2.
Partial product generators 122 and 123 of FIG. 7 will be described next. Partial product generators 122 and 123 generate partial products of redundant binary numbers from the multiplicand and two digits of the recoded multiplier expressed as a quaternary SD number. In this case, the adjacent two digits of the recoded multiplier may be expressed as a lower digit represented by R.sub.L and an upper digit represented by R.sub.H. By adding an intermediate partial product obtained from the lower digit R.sub.L and a multiplicand and an intermediate partial product obtained from the upper digit R.sub.H and a multiplicand, a partial product is generated.
For a multiplicand X, the partial product may have any value from the elements in the set -2X, 31 X, 0, X, 2X of recoded values R.sub.L, R.sub.H. In this case, the 2.sup.i weighting factor is omitted. 2X, which is twice the multiplicand X, can be realized by shifting the multiplicand one digit to the left. Inversion of positive and negative signs may be realized by inverting the positive and negative signs of each digit of multiplicand or by a 2's complement binary number. Such sign inversion of each digit of the multiplicand may be realized for the intermediate partial product of the lower digit R.sub.L of the recoded multiplier and the multiplicand. Further, the sign of the most significant digit of the intermediate partial product of the higher digit R.sub.H of the recoded multiplier, is equalized with inversion of the sign of the most significant digit of the intermediate partial product for the lower digit R.sub.L of the recoded multiplier by sign inversion of each digit and 2's complement.
As described previously, when the intermediate partial product is generated, supplementation by +1 or +1 (.about. indicates sign inversion) is required for the 2's complement binary number expression for generating the intermediate partial product for the upper digit R.sub.H of the recoded multiplier, and addition of the supplementary term may be carried out during addition of the redundant binary numbers in the generation of the partial product. In that case, computation of the least significant digit is carried out during generation of the partial product in order to facilitate addition of the supplementary term, which is carried out to the second less significant digit. Thereby, since the least significant digit of the partial product is shifted by four digits from the least significant digit of the partial product generated from the next two higher order digits of the recoded multiplier, the supplementary term may be added to the next digit lower than the least significant digit of the partial product generated from next digits higher than the digit of the recoded multiplier, and it can be handled as one digit of the upper partial products. Generation of the intermediate partial product for the digits R.sub.L, R.sub.H of the recoded multiplier including the supplementary term is indicated in the Table 5.
Addition of intermediate partial products is facilitated by generating the intermediate partial products as described above. Since the signs of each digit of the partial product generated by R.sub.L and the partial product generated by R.sub.H are inverted, a carry is not generated, which enables the partial product of the redundant binary number to be generated by a simple circuit. For example, if one digit a.sub.i of redundant binary number is encoded in accordance with Table 5 above, into a binary code by the two binary signals a.sub.i.sup.s, a.sub.i.sup.a, each digit of the partial product may be generated by adding the intermediate partial product for R.sub.L and the intermediate partial product for R.sub.H shifted by two digits to the left, and may be expressed by the following logical expressions. ##EQU14##
In the above expressions, r.sub.L.sup.s, r.sub.L.sup.1, r.sub.L.sup.2 are binary signals representing R.sub.L, while r.sub.H.sup.s, r.sub.H.sup.1, r.sub.H.sup.2 are binary signals representing R.sub.H.
In addition, the supplementary term may be expressed by C.sup.s and c.sup.a as indicated below. ##EQU15##
FIG. 9 is an embodiment of a circuit forming part of the partial product generators 122 and 123 of FIG. 7 which generates the partial products from the n-th digit to fourth digit. The circuit of FIG. 9 combines the circuits of FIGS. 4 and 5. In FIG. 9, gates 411 and 412 are AND-NOR composite gates similar to gate 411 in FIG. 4, gates 421, and 422 are EX-NOR gates similar to gate 421 in FIG. 4, gate 432 is also an EX-NOR gate, and gate 431 is a NOR gate. The circuit of FIG. 9, outputs a signal corresponding to the intermediate partial product from EX-NOR gate 421 for the lower order digits of a recoded multiplier and from EX-NOR gate 422 for the higher order digits. These two signals are added in FIG. 9 and the partial product is output from the NOR gate 431 and EX-NOR gate 432 as signals a.sub.i.sup.s and a.sub.i.sup.a (which are equivalent to the output of the circuit of FIG. 6) in the form of a redundant binary number expression.
The redundant addition unit 130 of FIG. 7, which forms the adder tree, is implemented for each digit, similar to the multiplier of FIG. 1, by the adder circuit illustrated in FIG. 6.
FIG. 10 is an adder circuit for one digit which is equivalent to the adder circuit of FIG. 6. Each gate in the circuit of FIG. 10 corresponds to the like-numbered gate in the circuit of FIG. 6, except for gate 354 in FIG. 10 which is logically equivalent to and replaces the circuit consisting of OR-NAND composite circuit 352 (and connection thereto of NAND gate 351).
The redundant addition unit 130 of FIG. 7 may be implemented by connecting as many redundant adders of FIG. 10 as are required for the number of digits to be added.
In the case of the 8.times.8-bit multipliers of FIGS. 1 and 7, two partial products are generated and therefore only one redundant addition unit is necessary, but the number of partial products generated increases with the number of digits of the multiplier. In such a case, a plurality of redundant addition units are required so that the partial products are added in tree fashion in units of two partial products.
It should be apparent that certain gates may be replaced by other gates, inverters and/or use of inverted signals. For example, EX-NOR gate 223 in FIG. 2 may be replaced by an EX-OR gate, and NOR gate 311 in FIG. 10 may be to replaced by a NAND gate (and vice versa) and logical inversion of signals or combinations with the inverters. Similarly composite gates or exclusive OR gates, etc. may be replaced by the NAND gates, NOR gates and combinations thereof with inverters, and vice versa.
The circuit embodiments described above may be implemented by binary logic using CMOS circuits, but they may also be implemented by utilizing other technology (for example, NMOS, ECL, TTL, IIL, etc.) or higher-radix logic.
An embodiment of a multiplier according to the present invention implemented by ECL circuits is described next.
In the generation of partial products as described above, the augend is nonnegative and the addend is nonpositive for almost all digits in addition in the first stage of the adder tree, and carry can be eliminated in such addition by generating the intermediate partial products as a signed digit expression where all digits, except for the most significant digit, are either all nonnegative, or all nonpositive, and then adding these partial products in the first stage of the adder tree. FIG. 11 is a block diagram of such a multiplier.
Referring to FIG. 11, multiplier recorder circuit 100 recodes a multiplier as a quarternary SD number using the 2-bit Booth method and is the same as multiplier recoder circuit 100 of FIG. 7. Odd partial product generator 101 generates from odd recoded digits of the multiplier and the multiplicand a partial product in the form of redundant binary numbers (namely, binary SD numbers) where the most significant digit is nonnegative and the other digits are all nonpositive. Even partial product generator 102 generates from even recoded digit of the multiplier (counted from zero) and the multiplicand partial a product in the form of redundant binary numbers where the most significant digit is nonpositive and the other digits are all nonnegative.
First stage redundant adder 121 (FIG. 11) executes addition in the redundant binary number system for the redundant binary numbers described above generated by the even and odd partial product generators 102, 101, respectively. Redundant binary adder 130 forms the second and the successive stages of the adder tree and executes addition in the redundant binary number system for ordinary redundant binary numbers in a manner similar to that of the redundant addition units illustrated in FIGS. 1 and 7. Redundant binary/binary converter 140 converts the redundant binary number obtained as a product into a binary number, and may easily be implemented by a look-ahead adder, etc.
Generation of partial products by the multiplier of FIG. 11 is described next, preceded by a description of a method for expressing inversion of positive and negative signs in redundant binary numbers.
A binary integer [X.sub.n-1 X.sub.n-2 . . . X.sub.0 ].sub.2 (X.sub.i .epsilon.{0,1}) of an n-bit 2's complement binary number has a value, x=-X.sub.n-1.2.sup.n-1 + ##EQU16## A Redundant binary number expressed as [X.sub.n-1 X.sub.n-2 . . . X.sub.0 ].sub.SD2 (where X.sub.n-1 is -1 (hereinafter simply indicated as 1) when X.sub.n-1 is 1 or 0) have a value of X when X.sub.n-1 is 0. Redundant binary number expressed as [X.sub.n-1 X.sub.n-2 . . . X.sub.0 ].sub.SD2 (where X.sub.i is similar to X.sub.n-1) have a value of -X (utilizing inversion of positive and negative signs of redundant binary number, which may be accomplished by inversion of the positive and negative signs of each digit). In addition, the inversion of the sign of a redundant binary number may be accomplished by the principle similar to inversion of the positive and negative signs of a 2's complement binary number which may be accomplished by obtaining a 2's complement. Specifically, since [X.sub.n-1 X.sub.n-2 . . . X.sub.0 ].sub.SD2 (where X.sub.i is 0 or 1 when X.sub.i is 1 or 0, respectively) has the value, ##EQU17## the redundant binary number having a value -X is obtained using the above value
and the supplement of +1. For [X.sub.n-1 X.sub.n-2 . . . X.sub.o ].sub.SD2, the most significant digit is nonpositive (0 or 1) and the other digits are all non-negative. Similarly, since [X.sub.n-1 X.sub.n-2 . . . X.sub.0 ].sub.SD2 has a value x+1, it is possible to use [X.sub.n-1 X.sub.n-2 . . . X.sub.0 ].sub.SD2 as the redundant binary number having a value X and thereafter execute supplementation by -1. The most significant digit of [X.sub.n-1 X.sub.n-2 . . . X.sub.0 ].sub.SD2 is nonnegative and all the other digits are all nonpositive.
Next, a method is described with reduces hardware requirements by utilizing the above redundant binary numbers as the partial products when the 2-bit Booth method is adopted for the binary multiplier using a redundant binary adder tree. Here, a multiplicand is expressed as [a.sub.n-1 a.sub.n-2 . . . a.sub.0 ].sub.2 and a multiplier as [b.sub.n-1 b.sub.n-2 . . . b.sub.0 ].sub.2. For simplification, n is a power of 2. As described above, the multiplier is recoded as a quaternary SD number according to the 2-bit Booth method. The recoded multiplier is expressed as [b'.sub.n/2-1 b'.sub.n/2-2 . . . b'.sub.0 ].sub.SD4 (b'.sub.j .epsilon.{-2, -1, 0, 1, 2}). The partial products are generated as shown in Table 6 for the digit b'.sub.j of the recoded multiplier. When the partial products are generated as shown in Table 6, the most significant digit of the partial product is nonpositive and the other digits are all nonnegative when j is an even number, and the most significant digit is nonnegative and the other digits are all nonpositive when j is an odd number.
Circuits implementing the blocks of the multiplier of FIG. 11 will be described next.
An example of a recorded multiplier (a quaternary SD number) and encoding thereof to a redundant binary number which is then supplemented is described below.
A digit b'.sub.j of the recoded multiplier is expressed by the 3-bit binary signal b'.sub.j-, b'.sub.j2, b'.sub.j1 or b'.sub.j+, b'.sub.j2, b'.sub.j1 shown in Table 7, and a digit x.sub.i of a redundant binary number by the 2-bit binary signals x.sub.i+, x.sub.i- shown in Table 8.
However, the (j)th digit b'.sub.j of the recoded multiplier is expressed by the 3-bit signal b'.sub.j-, b'.sub.j2, b'.sub.j1, when j is even number or by the 3-bit signal b'.sub.j+, b'.sub.j2, b'.sub.j1 when j is an odd number.
When encoding into the binary number is carried as described above, the j(th) digit b'.sub.j of the recoded multiplier is determined in the cell of the multiplier recoder by the following expressions.
b'.sub.0- =b.sub.1
b'.sub.02 =b.sub.1.b.sub.0
b'.sub.01 =b.sub.0
For an integer j which has a value ranging from 1 to n/2-1, ##EQU18##
In the above theoretical expressions, "." represents the logical product (AND), "+" represents the logical sum (OR), "b" represents the logical inverse (NOT) of b.
FIG. 12 is a schematic diagram of an embodiment of a cell of multiplier recoder circuit 100 of FIG. 11 for recoding a multiplier, specifically for the case of j set for even numbers, and utilizing NOR/OR functions. Gates 2311 through 2319 are NOR/OR composite circuits. Signals 2301 (b.sub.2j+1), 2303 (b.sub.2j), 2305 (b.sub.2j-1) are 1-bit binary signals indicating, respectively, the (2j+1)th digit, (2j)th digit and (2j-1)th digit of the multiplier. Signals 2302 (b.sub.2j+1), 2304 (b.sub.2j), 2306 (b.sub.2j-1) are 1-bit binary signals which are logical inversions (NOT) of signals 2301 (b.sub.2j+1), 2303 (b.sub.2j) and 2305 (b.sub.2j-1), respectively.
Output signals 2401 (b'.sub.j-), 2321 (b'.sub.j2) and 2325 (b'.sub.j1) form a 3-bit signal which represents recoded multiplier b'.sub.j. Output signals 2402 (b'.sub.j-), 2403 (b'.sub.j2) and 2404 (b'.sub.j1) form a 3-bit signal in which each of the bits is the logical inverse (NOT) of the corresponding bit of the 3-bit multiplier signal 2401, 2321 and 2325. FIG. 12 illustrates a cell for the multiplier recoder circuit when j is an even number. When j is odd number, the cell for the multiplier recoder circuit may similarly be easily formed.
Partial product generators 101, 102 will be described next.
When the results of some computations conducted previously including supplementation (i.e., addition of 1 or -1) to the lower order digit are obtained as a partial product, supplementation in the second and succeeding stages of the adder tree becomes easier. Specifically, during generation of partial products for the digits b'.sub.j of the recoded multiplier, when j is even number, the two least significant digits are computed and supplementation is carried out on the third least significant digit. When j is odd number, the least significant digit is computed and supplementation is carried on the second least significant digit.
In that case, the i(th) digit of the partial product corresponding to the (j)th digit b'.sub.j of the recoded multiplier is determined by the following theoretical expressions.
When j is even number, ##EQU19##
However, c.sub.2j+ and c.sub.1j-, indicating supplementation, are added in the second and successive stages of the adder tree.
FIG. 13 is a schematic diagram of a cell for partial product utilizing NOR/OR functions which forms the even partial product generator 102 of FIG. 11. Gates 2411 through 2416 are NOR/OR composite circuits. Signal 2401 (b'.sub.j-) is a 1-bit element of the 3-bit signal which represents the (j)th digit b'.sub.j of the recoded multiplier. Signals 2402 (b'.sub.j-), 2403 (b'.sub.j2) and 2404 (b'.sub.j1) are the logical inverses (NOT) of the individual bits of the 3-bit signal representing b'.sub.j. Output signal 2421 (x.sub.ij+) is one bit of the 2-bit signal representing the i(th) digit of the partial product corresponding to the j(th) digit of the recoded multiplier. Output signal 2422 (x.sub.ij+) is the logical inverse (NOT) of x.sub.ij+. However, "i" is an integer ranging from 2 to n-1, and the remaining one bit x.sub.ij- of the two bit signal is always zero. Similarly, a cell for generating partial products for the case i=0, 1, n may also be easily formed. In addition, a cell for generating the partial product which forms the odd partial product generator 101 may be formed with a similar circuit.
The first stage redundant binary adder 121 is described next. Since the augend is nonnegative and the addend is nonpositive for almost all digits, a carry is not generated at all during addition in the first stage redundant binary adder 121, which simplifies the addition cell. Addition is carried out in accordance with Table 9.
Addition of the i(th) digit is determined by the following expressions.
Z.sub.i+ =x.sub.i+.y.sub.i-
Z.sub.i- =x.sub.i+.y.sub.i-
where x.sub.i+ is a 1-bit signal which represents the augend x.sub.i, and y.sub.i- is a 1-bit signal which represents the addend y.sub.i.
FIG. 14 is a schematic diagram of an addition cell utilizing NOR/OR functions which forms the first stage of first redundant binary adder 121 of FIG. 11. Gates 2511 and 2512 are NOR/OR composite circuits. Signal 2501 (x.sub.i+) is a 1-bit signal which represents the i(th) digit x.sub.i of the addend of a redundant binary expression having all nonnegative digits. Signal 2502 (x.sub.1+) is the logical inverse (NOT) of signal x.sub.1+. Signal 2503 (y.sub.i+) is a 1-bit signal which represents the i(th) digit y.sub.i of the addend of a redundant binary expression having all non-positive digits. Signal 2504 (y.sub.i-) is the logical inverse (NOT) of signal 2503 (Y.sub.i-). Output signals 2522 (Z.sub.i+) and 2523 (Z.sub.i-) form a 2-bit signal which represents the (i)th digit Z.sub.i of the redundant binary number obtained as a result of addition. Output signal 2521 (Z.sub.i+) is the logical (NOT) of signal 2522 (Z.sub.i+).
Redundant binary adder 130 of FIG. 11 is described next.
Addition in redundant adder 130 proceeds in accordance with Table 3 above. Addition at the (i)th digit is determined by the following expressions. ##EQU20##
FIG. 15 is a schematic diagram of an addition cell utilizing NOR/OR functions which forms part of redundant binary adder 130 of FIG. 11. Gates 611 through 623 are NOR/OR circuits. Signals 602 (x.sub.i+) and 603 (x.sub.i-) form a 2-bit signal which represents the (i)th digit x.sub.i of a redundant binary number augend. Signal 601 (x.sub.i+) is a 1-bit signal representing the logical inversion (NOT) of signal 602 (x.sub.i+). Signals 605 (y.sub.i+) and 606 (y.sub.i-) form a 2-bit signal which represent the (i)th digit y.sub.i of the redundant binary number addend. Signal 604 (y.sub.i+) is a 1-bit signal which represents the logical inverse (NOT) of signal 605 (y.sub.i+). Output signal 631 (P.sub.i) indicates whether or not the (i)th digit of the augend (x.sub.i) and the (i)th digit of the addend (y.sub.i) are all nonnegative. Output signal 633 (P.sub.i-1) indicates whether or not the (i-1)th digit of the augend (x.sub.i-1) and the (i-1)th digit of the addend (y.sub.i-1) are all nonnegative. Output signals 632 (P.sub.i) and 634 (P.sub.i-1) are logical inversions (NOT) of signals 631 (p.sub.i) and 633 (p.sub.i-1), respectively. Output signal 635 (u.sub.i) is a 1-bit signal related to the intermediate carry at the (i)th digit, and output signal 636 (u.sub.i) is the logical inverse (NOT) of signal 635 (u.sub.i). Output signal 637 (u.sub.i-1) is related to the intermediate carry for the (i-1)th digit, and output signal 638 (u.sub.i-1) is the logical inverse (NOT) of signal 637 (u.sub.i-1). Output signals 642 (z.sub.i+ ) and 643 (z.sub.i-) form a 2-bit signal representing the (i)th digit z.sub.i of the result of addition. Output signal 641 (z.sub.i+) is the logical inverse (NOT) of signal 642 (z.sub.i+).
While embodiments of multipliers utilizing a redundant binary adder tree have been described above, multipliers may also be formed utilizing the multi-bit Booth method or signed digit numbers of higher radices. In addition, the present invention can also be applied to multipliers utilizing the Wallace tree or array multipliers, etc.
According to the present invention, since the number of partial products may be reduced to almost half of that in the Booth method of the prior art by providing a redundant subtraction unit having simplified structure, the following advantages are achieved: the number of adder tree stages may be reduced by one in the multiplier by, for example, utilizing the redundant binary adder tree; processing time may be shortened by the time equivalent of 2-3 gate stages; and the number of elements required can be reduced by about 40%.
The present invention provides two kinds of partial product generating methods and is capable of substantially reducing the number of partial products by providing a subtraction circuit of simplified construction, which:
(1) enables the number of elements in the arithmetic processor to be reduced;
(2) high speed operation of the arithmetic processor to be achieved;
(3) comparatively simple circuit structure to be utilized;
(4) the arithmetic processor to be mounted easily and economically on an LSI chip.
Claims
What is claimed is:
1. A multiplier circuit for generating a product from inputs corresponding to a binary multiplicand and a binary multiplier, said multiplier circuit comprising: (a) a plurality of even intermediate partial product generators each of which receives two or more digits of said binary multiplier and said binary multiplicand and determines therefrom a first intermediate partial product; (b) a plurality of odd intermediate partial product generators each of which receives two or more digits of said binary multiplier and said binary multiplicand and determines therefrom a second intermediate partial product; (c) a plurality of partial product generators each of which receives one said first intermediate partial products and one said second intermediate partial products and determines therefrom a partial product which corresponds to an integer times said multiplicand; and (d) a plurality of addition means forming stages of an adder tree, each stage of which receives two of said partial products and outputs generated by other stages of said adder tree, and determines therefrom a final product.
2. A multiplier circuit in accordance with claim 1, wherein the number of said even intermediate partial product generators is equal to the number of said odd intermediate partial product generators.
3. A multiplier circuit for generating a product from inputs corresponding to a binary multiplicand and a binary multiplier comprising: (a) a plurality of even recoders each of which recodes two or more digits of said binary multiplier and determine therefrom a recoded even digit of said binary multiplier expressed as a signed-digit number; (b) a plurality of odd recoders each of which recodes two or more digits of said binary multiplier and determines therefrom a recoded odd digit of said binary multiplier expressed as a signed-digit number; (c) a plurality of even intermediate partial product generators each of which receives a different even digit of said recoded binary multiplier and said binary multiplicand, determining therefrom an even intermediate partial product; (d) a plurality of odd intermediate partial product generators, each of which receives a different odd digit of said recoded binary multiplier and said binary multiplicand, determining therefrom an intermediate partial product; (e) a plurality of partial product generators each of which receives one of said even intermediate partial products and one of said odd intermediate partial products and determines therefrom a partial product which corresponds to an integer times said multiplicand; and (f) a plurality of addition means forming an adder tree each of which receives two of said partial products and outputs generated by other stages of said adder tree, and determines therefrom a final product.
4. A multiplier circuit in accordance with claim 3 wherein the number of said even recoders and that of said odd recoders, and the number of said even intermediate partial products and that of said odd intermediate partial products are approximately equal to each other respectively.
5. A multiplier circuit in accordance with claim 4 wherein said odd recoders further comprise means for inverting the sign of said recoded odd digit of said binary multiplier, and wherein each of said partial product generators includes a subtraction unit which performs subtraction between said even intermediate partial products and said odd intermediate partial products input thereto.
6. A multiplier circuit in accordance with claim 4, wherein each said even recoders recodes three digits y.sub.2j, y.sub.2j+1, Y.sub.2j+2 of said multiplier corresponding to different value of the index j to a quaternary signed digit number b.sub.j determined by the arithmetic formula, b.sub.j =(y.sub.2j +y.sub.2j+1 -2y.sub.2j+2) where j is 0 or even; wherein each said odd recoders recodes three digits y.sub.2j, y.sub.2j+1, y.sub.2j+2 of said multiplier corresponding to a different value of the index j to a quaternary signed digit number b.sub.j determined by the arithmetic formula b.sub.j =(2y.sub.2j+2 -y.sub.2j+1 -y.sub.2j) where j is odd; wherein each of said partial product generators includes a subtraction unit which subtracts each odd digit b.sub.j of said odd intermediate partial product from each even digit b.sub.j of said even intermediate partial product input thereto and generates therefrom a binary signed-digit number; and wherein said addition means includes at least one adder which receives two of said binary signed-digit numbers and determines therefrom a sum in the form of a binary signed-digit number.
7. A multiplier circuit in accordance with claim 6, wherein, said even intermediate partial product generators or said odd intermediate partial product generators, output a number which is the logical negation of each digit of the corresponding intermediate partial product determined therein, when a recoded digit of said multiplier having a negative value is input thereto; and wherein at least some of said partial product generators and said addition means receive a correction term corresponding to plus one or minus one which is applied to the least significant digit of said partial products input thereto.
8. A multiplier circuit in accordance with claim 6, which further includes means to convert a binary signed-digit number obtained as a product into a binary number.
9. A multiplier circuit in accordance with claim 6 which further includes means to convert a signed-digit number obtained as a final product into a binary number.
10. A multiplier circuit in accordance with claim 3 wherein said odd recoders further comprise means for inverting the sign of said recoded odd digit of said binary multiplier, and wherein each of said partial product generators includes a subtraction unit which performs subtraction between said even intermediate partial product and said odd intermediate partial product input thereto.
11. A multiplier circuit in accordance with claim 2, wherein each said even recoders recodes three digits y.sub.2j, y.sub.2j+1, Y.sub.2j+2 of said multiplier corresponding to different value of the index j to a quaternary signed digit number b.sub.j determined by the arithmetic formula, b.sub.j =(y.sub.2j +y.sub.2j+1 -2y.sub.2j+2) where j is 0 or even; wherein each said odd recoders recodes three digits y.sub.2j, y.sub.2j+1, y.sub.2j+2 of said multiplier corresponding to a different value of the index j to a quaternary signed digit number b.sub.j determined by the arithmetic formula b.sub.j =(2y.sub.2j+2 -y.sub.2j+1 -y.sub.2j) where j is odd; wherein each of said partial product generators includes a subtraction unit which subtracts each odd digit b.sub.j of said odd intermediate partial product from each even digit b.sub.j of said even intermediate partial product input thereto and generates therefrom a binary signed-digit number; and wherein said addition means includes at least one adder which receives two of said binary signed-digit numbers and determines therefrom a sum in the form of a binary signed-digit number.
12. A multiplier circuit in accordance with claim 11, wherein, said even intermediate partial product generators or said odd intermediate partial product generators, output a number which is the logical negation of each digit of the corresponding intermediate partial product determined therein, when a recoded digit of said multiplier having a negative value is input thereto; and wherein at least some of said partial product generators and said addition means receive a correction term corresponding to plus one or minus one which is applied to the least significant digit of said partial products input thereto.
13. A multiplier circuit in accordance with claim 11, which further includes means to convert a binary signed-digit number obtained as a product into a binary number.
14. A multiplier circuit in accordance with claim 11 which further includes means to convert a signed-digit number obtained as a final product into a binary number.
15. A multiplier circuit for generating a product from inputs corresponding to a binary multiplicand and a binary multiplier, comprising: (a) a plurality of recoders each of which recodes two or more digits of said binary multiplier and generates a recoded mutliplier digit as a signed-digit number; (b) a plurality of first means, each of which receives an even recoded multiplier digit and said multiplicand and determines therefrom a first signed-digit intermediate partial product in which the most significant digit is non-positive and all other digits are non-negative; (c) a plurality of second means, each of which receives an odd recoded multiplier digit and said multiplicand and determines therefrom a second signed-digit intermediate partial product in which the most significant digit is non-negative and all other digits are non-positive; and (d) a plurality of addition means each of which receives said first and second signed-digit intermediate partial products and determines therefrom a signed-digit partial product which is the sum thereof; and (e) a plurality of signed-digit adders forming an adder tree each of which receives the signed-digit partial products from two of said addition means and outputs generated by higher stages of said adder tree, to determine therefrom a final product.
16. A multiplier circuit in accordance with claim 3, wherein, said even intermediate partial product generators or said odd intermediate partial product generators, output a number which is the logical negation of each digit of the corresponding intermediate partial product determined therein, when a recoded digit of said multiplier having a negative value is input thereto; and wherein at least some of said partial product generators and said addition means receive a correction term corresponding to plus one or minus one which is applied to the least significant digit of said partial products input thereto.
17. A multiplier circuit in accordance with claim 15, wherein the number of said first means, that of the said second means and that of said addition means are approximately equal to each other.
18. A multiplier circuit in accordance with claim 17 wherein said first means outputs a first complement number whose digits are the logical negation of each digit of said first signed-digit intermediate partial product when said even recoded multiplier digit received thereby is negative in value; wherein said second means outputs a second complement number whose digits are the sign-inverted digits of the logical negation of each digit of said second signed-digit intermediate partial product, when said odd recoded multiplier digit received thereby is positive in value; and wherein at least some of said addition means receive a correction term corresponding to plus one or minus one which is applied to the least significant digit or to the second least significant digit of said first and second complementary numbers input thereto.
19. A multiplier circuit in accordance with claim 15 wherein said first means outputs a first complement number whose digits are the logical negation of each digit of said first signed-digit intermediate partial product when said even recoded multiplier digit received thereby is negative in value; wherein said second means outputs a second complement number whose digits are the sign-inverted digits of the logical negation of each digit of said second signed-digit intermediate partial product, when said odd recoded multiplier digit received thereby is positive in value; and wherein at least some of said addition means receive a correction term corresponding to plus one or minus one which is applied to the least signficiant digit or to the second least significant digit of said first and second complementary numbers input thereto.
20. A multiplier circuit for generating a product from inputs corresponding to a binary multiplicand and a binary multiplier comprising: (a) a plurality of recoders each of which recodes two or more digits of said binary multiplier and generates a recoded multiplier digit as a signed-digit number; (b) a plurality of first means each of which receives an odd recoded multiplier and said multiplicand and determines therefrom a first signed-digit intermediate partial product in which the most significant digit is non-positive and all other digits non-negative; (c) a plurality of second means each of which receives an even recoded multiplier digit and said multiplicand and determines thereby a second signed-digit intermediate partial product in which the most significant digit is non-negative and all other digits are non-positive; (d) a plurality of addition means each of which receives said first and second signed-digit intermediate partial products and determines therefrom a signed-digit partial product which is the sum thereof; and (e) a plurality of signed-digit adders forming an adder tree each of which receives the signed-digit partial products from two of said addition means and outputs generated by higher stages of said adder tree to determine therefrom a final product.
21. A multiplier circuit in accordance with claim 20 wherein the numbers of said first means, that of the said second means and that of the said addition means are approximately equal to each other.
22. A multiplier circuit for generating a product from inputs corresponding to a binary multiplicand and a binary multiplier comprising: (a) a plurality of recoders each of which recodes two or more digits of said multiplier and generates a recoded multiplier digit expressed as a signed-digit number; (b) a plurality of partial product generators each of which receives two recoded multiplier digits and said multiplicand and determines therefrom a partial product expressed as a signed-digit number; and (c) a plurality of signed-digit adders forming stages of an adder tree, each of which receives two of said partial products and an output generated by some of the higher stages of said adder tree.
23. A multiplier circuit in accordance with claim 22 wherein each of said partial product generators further includes: (a) a first intermediate partial product generating means for receiving the lower order digit of two recoded multiplier digits and said multiplicand, determining therefrom a first intermediate partial product and providing as an output the sign inversion of each digit of said first intermediate partial product when said lower order digit is negative; (b) a second intermediate partial product generating means for receiving the higher order digit of said two recoded multiplier digits and said multiplicand, determining therefrom a second intermediate partial product and providing as an output a number obtained by the sign inversion of each digit of said second intermediate partial product when said lower order digit is positive and said higher order digit is negative, or a number which is the two's complement of said second intermediate partial product when said lower order digit and said higher order digit are negative, or a number obtained by sign inversion of each digit of the two's complement of said second intermediate partial product when said lower order digit and said higher order digit are positive; and (c) an addition means for receiving said outputs from said first and second intermediate partial product generating means and determining therefrom a final product.
24. A multiplier circuit in accordance with claim 23 wherein said second intermediate partial product generating means outputs both a number obtained by the logical negation of each digit of the intermediate partial product determined therein and a correction term when said lower order digit and said higher order digit are both negative, or generates the logic negation of each digit of said intermediate partial product determined therein and outputs both a number obtained by the sign inversion of each logically negated digit and a correction term when said lower order digit and said higher order digit are both positive; and wherein said correction term so generated by said second intermediate partial product generating means in output to said addition means.
Patent Citations (1)
| Patent | Date | Inventor | Cited By |
|---|---|---|---|
| US4745570 | 1988-05-01 | Diedrich et al. |
Non-Patent Literature (14)
- A VLSI-Oriented High-Speed Divider Using Redundant Binary Representation, Takagi et al, IECE, Japan, vol. 67, D. #4, pp. 450-457, 4/84.
- A VLSI-Oriented High-Speed Multiplier Using Redundant Binary Adder Tree, Takagi et al., IECE, Japan, vol. J66.d, pp. 683-690, 6/84.
- A New Class of Digital Division Methods, James Robertson, IRE Transactions on Electronic Computers, pp. 218-222, 9/58.
- Signed-Digit Number Representations for Fast Parallel Arithmetic, Avizienis, IRE Transactions on Electronic Computers, pp. 389-400, 9/61.
- A Class of Binary Divisions Yielding Minimally Represented Quotients, Metze, IRE Transactions on Electronic Computers, pp. 761-764, 12/62.
- Design of the Arithmetic Units of ILLIAC III, Redundancy & Higher Radix Methods, Atkins, IEEE Transacts. on Computers, vol. C-19, pp. 720-732, 8/70.
- Multiple Operand Addition and Multiplication, Shanker Singh et al., IEEE Transactions on Computers, vol. C-22, pp. 113-120, 2/73.
- Concise Papers, Lyon, IEEE Transactions on Communications, pp. 418-425, 4/76.
- Real-Time Processing Gains Ground with Fast Digital Multiplier, Waser et al., Electronics, pp. 93-99, 9/77.
- High Speed Multiplier Using a Redundant Binary Adder Tree, Harata et al., IEEE International Conference on Computer Design, pp. 165-170, 1984.
- High Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree, Takagi et al., IEEE Transactions on Computers, vol. C-34, No. 9, pp. 1789-1795, 9/85.
- Design of High Speed MOS Multiplier and Divider Using Redundant Binary Representation, Kuninobu et al., Proceedings 8th Symposium on Computer Arithmetic, pp. 80-86, 5/87.
- Avizienis, "Binary-Compatible Signed-Digit Arithmetic", Proceedings-Fall Joint Computer Conference, 1964, pp. 663-672.
- Tung, "Division Algorithm for Signed-Digit Arithmetic", IEEE Trans. on Computers, Sep. 1968, pp. 887-889.