Solid-State Imaging Device

1. Field of the Invention

The present invention relates generally to an imaging device and more particularly to a solid-state imaging device comprising a plurality of photoelectric conversion elements integrated on a semiconductor substrate.

2. Description of the Related Art

The solid-state imaging device has numerous advantageous features such as reduced size, light weight, freedom from maintenance, elongated uselife and others which are excellent over those of the image pick-up tube. Being backed up by the remarkable progress in the semiconductor technology, the solid-state imaging device is now developed to such a state as to replace the image pick-up device from the stand point of the manufacturing costs as well as performance.

The solid-state imaging device can be generally classified into two categories, i.e. the MOS type solid-state imaging device in which signal charges generated by photoelectric conversion elements (such as photodiodes or the like) are read out over aluminum signal lines through MOS transistors and the CCD type solid-state imaging device in which photoelectric charges generated by the individual photoelectric conversion elements are read out through CCD (abbreviation of Charge Coupled Device) shift registers. The CCD type solid-state imaging device in turn can be classified into three types, that is, a frame transfer type CCD imaging device which includes light-receiving or light-sensitive parts and charge storage parts separately from each other, an interline type CCD solid-state imaging device having stripe-like charge storage parts and charge transfer parts between light-sensitive pixels (or picture elements), and a FIT (Frame Interline Transfer) type CCD imaging device which is a hybrid of the frame transfer type and interline type device. These types of CCD solid-state imaging devices enjoy an advantageous feature in that the photoelectric signal charges generated by the photoelectric elements can be outputted with high efficiency, whereby noise generation can be reduced significantly as compared with the MOS type imaging device.

A typical one of the CCD solid-state image device is disclosed in ISSCC 82, pp. 168-169 and ISSCC 86, pp. 94-95.

For having a better understanding of the present invention, an interline type CCD solid-state imaging device known heretofore will be described in some detail by referring to FIGS. 1 and 2 of the accompanying drawings, in which FIG. 1 shows a structure of the hitherto known interline type CCD solid-state imaging device.

Referring to FIG. 1, each of photoelectric conversion elements 1 is constituted by a photodiode implemented in the form of a pn-junction diode. The element 1 converts photoelectrically the light incident thereon into photoelectric signal charge and stores the charge therein. These photoelectric conversion elements are disposed in vertical and horizontal arrays in a regular matrix-like configuration. Vertical CCD registers 3 are provided for the vertical rows of the photoelectric conversion elements in one-to-one correspondence for shifting or transferring electric charges in the vertical direction. A select gate 2 is provided between each of the photoelectric conversion elements and the associated one of the vertical CCD registers 3 for the purpose of controlling the signal charge flow from the photoelectric conversion element to the associated vertical CCD register 3. A horizontal CCD register 4 are provided at one ends of the vertical CCD registers 3 for receiving in parallel the signal charges transferred through the individual vertical CCD registers 3 to thereby transfer the received charges in the horizontal direction. An output amplifier 5 is provided at one end of the horizontal CCD register 4 for amplifying the signal charges transferred the horizontal CCD register 4.

The photoelectric signal charge stored in the photoelectric conversion element 1 is transferred to the associated vertical CCD register through the select gate 2. The signal charge thus selected is then transferred to the output amplifier 5 through the vertical CCD register 3 and horizontal CCD register 4 to be finally outputted from through the output amplifier 5 as the image (video) signal.

The vertical CCD register 3 is usually driven by a four-phase clock signal. Accordingly, four phase clock wires 6 to 9, 10 to 13, 14 to 17 are connected to the vertical CCD registers 3, wherein the clock wires for two phases 7; 9; 11; 13 and 15; 17 serve also as gate wires for the select gates 2.

Operation of the vertical CCD registers 3 of the imaging device will be explained by referring to FIGS. 2A and 2B of the accompanying drawings, wherein FIG. 2A is a sectional view of the vertical CCD register 3 taken along a line A--A' in FIG. 1 and FIG. 2B shows time charts for illustrating charges in potential in the vertical CCD register 3 as a function of time. Upon application of the clock pulses .phi..sub.V2 and .phi..sub.V4 onto the clock wires (gate wires) 11, 13, 15 and 17, photoelectric signal charges Q.sub.3, Q.sub.4, Q.sub.5 and Q.sub.6 stored in the photodiodes 1 are transferred to areas underlying the gate electrodes of the associated vertical registers 3, respectively. At a time point t.sub.2, the clock pulse .phi..sub.V3 is applied onto the clock wires 12 and 16, resulting in that the photoelectric signal charges Q.sub.3 and Q.sub.4 on one hand and the photoelectric signal charges Q.sub.5 and Q.sub.6 on the other hand are mixed together into photoelectric signal charges (Q.sub.3 +Q.sub. 4) and (Q.sub.5 +Q.sub.6), respectively. Subsequent successive applications of the clock pulses at time points t.sub.3, t.sub.4 and t.sub.5 in the similar manner result in that the photoelectric signal charges (Q.sub.1 +Q.sub.2), (Q.sub.3 +Q.sub.4) and (Q.sub.5 +Q.sub.6) resulting from the mixing are sequentially transferred in the vertical direction. The photoelectric signal charges transferred in this manner are outputted to the output amplifier 5 sequentially through the horizontal CCD register 4 during the vertical scan period. Upon completion of the transfer of all the signal charges present in the vertical CCD register 3, then the photoelectric signal charges stored in the individual photodiodes 1 are again transferred to the vertical CCD registers 3, whereby the similar process described above is repeated. As will now be seen, the signal storage period in the hitherto known imaging device corresponds to the time required for the signal charges to be transferred through the vertical CCD register 3, i.e. the time equal to one field period.

In the solid-state imaging device known heretofore, the number of the signal charges which can be transferred through the vertical CCD register is limited by the number of transfer electrodes of the vertical CCD register and phase number of the clock pulse signal. Consequently, the signal storage time of the photodiode remains constant, whereby a problem arises that the signal charge storage time or duration can not be controlled freely, making it impossible to implement the electronic shutter function and others.

An object of the present invention is to provide a solid-state imaging device having an electronic shutter function through which the signal charge storage time can be varied in a facilitated manner.

In view of the above object, it is proposed according to an aspect of the present invention that the signal charge transfer from the photoelectric conversion elements to the vertical charge transfer means is performed at least twice during one field period, wherein the vertical charge transfer means are so arranged as to transfer the charges transferred thereto independent of one another.

In a preferred embodiment of the present invention, the vertical charge transfer means transfer the signal charges having respective different storage durations independent of one another during one field period, the signal charges being read out through the horizontal charge transfer means. In this manner, the signal charges having respective different storage durations an be outputted without being mixed together, thus making it possible to select arbitrarily the charge storage time or duration. In other words, the electronic shutter function can be implemented in the solid-state imaging device.

These and other objects and many of the attendant advantages of the present invention will be readily appreciated as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings.

FIG. 1 is a schematic circuit diagram showing a structure of a solid-state imaging device known heretofore;

FIG. 2A is a schematic sectional view of a vertical CCD register taken along the line A--A' in FIG. 1;

FIG. 2B is a time chart for illustrating changes in potential as a function of time in the vertical CCD register shown in FIG. 2A;

FIG. 3 is a schematic circuit diagram showing a general arrangement of a solid-state imaging device according to an exemplary embodiment of the present invention;

FIG. 4A is a schematic sectional view of a vertical CCD register shown in FIG. 3;

FIG. 4B is a time chart for illustrating changes in potential in the vertical CCD register shown in FIG. 4A as a function of time;

FIGS. 5A and 5B are signal waveform diagrams illustrating pulse signals employed for driving the vertical CCD registers shown in FIG. 3;

FIG. 6 is a timing chart for illustrating driving operation in the solid-state imaging device shown in FIG. 3;

FIGS. 7A and 7B are views similar to FIG. 4A and show changes in potential as a function of time in a solid-state imaging device according to another embodiment of the present invention;

FIGS. 8 and 9 are schematic circuit diagrams showing, respectively, general arrangements of solid-state imaging devices according to other embodiments of the present invention; and

FIGS. 10A and 10B are views similar to FIG. 3 and show another exemplary structure of the vertical CCD register shown in FIG. 3.

The present invention will now be described in detail in conjunction with a first exemplary embodiment thereof by reference to FIG. 3.

FIG. 3 shows a general arrangement of the solid-state imaging device according to an embodiment of the present invention which is, by and large, identical with that of the hitherto known device shown in FIG. 1 except for the differences in that the clock wires 106 to 117 of the vertical CCD registers 3 are driven by clock signals of eight phases, and that a charge sink region 121 is additionally provided for sweeping off useless charges in combination with an interposed coupling region 120 for connecting the charge sink area 121 to the horizontal CCD 4. Useless charges of those transferred from the vertical CCD registers 3 during each horizontal blanking period are transferred to the charge sink region 121 through the coupling region 120. The charge sink region 121 may be formed of an impurity-diffused layer to which a voltage is applied externally.

Now, description will be directed to the operation of the solid-state imaging device shown in FIG. 3 by reference to FIGS. 4A and 4B, FIGS. 5A and 5B and FIG. 6.

FIG. 4A is a sectional view showing schematically a structure of the vertical CCD register 3, and FIG. 4B is a view for illustrating change in potential in the vertical CCD register 3 shown in FIG. 4A. Further, FIGS. 5A and 5B are views showing driving pulse signals for the vertical CCD registers 3. Finally, FIG. 6 is a timing chart for illustrating the driving operation of the solid-state imaging device shown in FIG. 3.

At a time point t=t.sub.1 shown in FIG. 4B (corresponding to t=t.sub.al in FIG. 6), a high voltage clock signal is applied to clock wires 105, 107, 109, 111, 113 and 115, which serve also as the gate wires for transferring the photoelectric signal charges stored in the individual photodiodes 1 to the vertical CCD registers 3. As the result, the signal charges Q.sub.2, Q.sub.3, Q.sub.4, Q.sub.5, Q.sub.6, and Q.sub.7 are stored underneath the associated electrodes of each vertical CCD register. The signal charges transferred to the vertical CCD register 3 are held in the regions indicated by hatching.

As a time point t=t.sub.2, the clock pulses .phi..sub.V3 and .phi..sub.V7 are applied to the clock wires 108 and 112, whereby the signal charges Q.sub.3 and Q.sub.4 on one hand and the signal charges Q.sub.5 and Q.sub.6 on the other hand are, respectively, mixed together to the signal charges (Q.sub.3 +Q.sub.4) and (Q.sub.5 +Q.sub.6).

At a time point t=t.sub.3, the mixed signal charges (Q.sub.3 +Q.sub.4) and (Q.sub.5 +Q.sub.6) are stored underneath the electrodes associated with the clock wires 109 and 113, respectively.

At a time point t=t.sub.4, only the signal charge (Q.sub.3 +Q.sub.4) is transferred to a region underlying the electrode of the succeeding stage.

During periods t.sub.5 to t.sub.18 and t.sub.18 to t.sub.31 which correspond to one horizontal blanking period, respectively, each of the signal charges is transferred to the vertical CCD register 3. The regions indicated by hatching represents those regions which hold the signal charges, while blank (non-hatched) areas Q.sub.0 represent the empty regions for holding other signal charges.

Subsequently, the process corresponding to that carried out during the period (t=t.sub.5 to t.sub.31) is repeated for one field period to transfer the signal charges. In this process, if the signal charges stored in the photodiodes 1 are read out at a time point t=t.sub.a2 shown in FIG. 6, the storage time of the signal charges capable of contributing to the generation of video (image) signal corresponds to the period of (t.sub.a3 -t.sub.a2). The time points t.sub.a1, t.sub.a3 and t.sub.a5 correspond to repetitions of one field period, and can be specified. Accordingly, by setting t.sub.2 and t.sub.a4 at arbitrary time points, the storage time or duration can be varied freely.

Next, description will be made in what manner the vertical CCD register 3 reads out the signal charges and the useless charges.

During the period of t.sub.a1 to t.sub.a3 shown in FIG. 6, the process carried out during the period of t.sub.5 to t.sub.31 shown in FIG. 4B is repeated. In that case, at the time point t.sub.18 corresponding to t.sub.a2 shown in FIG. 6, the empty or quiescent regions (no-signal region) Q.sub.0 exist underneath the gates 111 .phi..sub.V6) and 113 (.phi..sub.V8), respectively. Accordingly, at the time point t.sub.18, the high voltage clock is applied to the clock wires 111 and 113 to read out the electric charge from the photodiodes 1. Further, at a succeeding time point t.sub.31 corresponding to t.sub.a2 shown in FIG. 6, the high voltage clock is applied to the clock wires 107 and 109 to read out the charges from the photodiodes 1. The signal charges thus read out through two operations performed at the time points t.sub.18 and t.sub.31 as mentioned above are transferred to the charge sink region 121 from the horizontal CCD register 4 by way of the coupling part 120 to be processed as the useless charges. In this manner, it is possible to read out the signal charges stored at other time points even during the normal signal transfer. Although it is assumed in the case of the example illustrated in FIG. 4 that the horizontal scan is performed at the time points t.sub.5, t.sub.13 and t.sub.31, it will be appreciated that the horizontal scan is not necessarily limited to such timing. Further, the reading of the signal charges from all the regions indicated by the hatched areas is performed at the time point t.sub.1. It should however be mentioned that this reading operation may be performed with a deviation in time of 1 H (horizontal blanking period) in correspondence with the timing at which the signal charges are read out from the blank regions (non-hatched regions). By way of example, the signal charges may be read out from the

photodiodes corresponding to .phi..sub.V6 and .phi..sub.V8, being followed after lapse of 1 H by the reading of the signal charges from the photodiodes corresponding to the clocks .phi..sub.V2 and .phi..sub.4, for the purpose of uniformizing the storage duration of the individual signal charges in the regions indicated by the hatched areas. FIG. 5 shows an example of pulse timing for realizing the potential transitions illustrated in FIG. 4B. The pulses .phi..sub.V1 to .phi..sub.V4 rising up at the time point t.sub.5 may be same as the pulses .phi..sub.V5 to .phi..sub.V8 rising up at the time point t.sub.18 after lapse of one horizontal blanking period. Similarly, the pulses .phi..sub.V5 to .phi..sub.V8 rising up at the time point t.sub.5 may be same as the pulses .phi..sub.V1 to .phi..sub.V4 rising up at the time point t.sub.18.

FIG. 7 shows a modification of the operation illustrated in FIG. 4 according to another embodiment of the invention. Since the number of the electrodes for the non-hatched regions is decreased, the amount of charges as transferred is decreased. However, the timing control is further simplified.

In the ordinary imaging operation requiring no electronic shutter operation, the clock signal of four phases can be used for driving the vertical CCD registers.

In the foregoing description of the embodiments of the invention, it has been assumed that the clock signal for driving the vertical CCD is of eight phases. It should however be mentioned that the aimed effects can be obtained by using the clock signal of at least seven phases.

FIG. 8 shows a solid-state imaging device according to another embodiment of the invention. The imaging device shown in FIG. 8 differs from the one shown in FIG. 3 in that the charge sink region 121 is replaced by a CCD register 122 destined for the charge absorption. The useless charges of those transferred through the vertical CCD registers 3 during each horizontal blanking period are transferred to the charge sink CCD register 122 by way of the interposed coupling part 120. The useless charges once fetched by the CCD register 122 are swept off from the external terminal by driving the CCD register 122.

FIG. 9 shows a solid-state CCD imaging device according to still another embodiment of the invention which differs from that shown in FIG. 8 in that an output amplifier 123 is additionally provided for detecting and amplifying the charge signal outputted through the CCD register 122. With the arrangement shown in FIG. 9, it is possible to detect the charge signal originating in the non-hatched regions (quiescent regions) Q.sub.0 shown in FIG. 4B, whereby the detection signal can be made use of in the image (video) signal processing.

FIGS. 10A and 10B show another embodiment of the present invention, wherein FIG. 10A shows a vertical CCD register 3 in a fragmentary sectional view. As will be seen in FIG. 10A, impurity layers 202 are provided in the surface of a semiconductor substrate 201 for forming potential barriers for the charge carriers. With this arrangement, the potential distribution underneath the gate electrodes 203 can be made finer, as illustrated in FIG. 10B. Consequently, there are available an increased number of electrodes for reading the signal charges even with the clock signal of four phases. Thus, the signal storage duration can be controlled.

As will now be appreciated from the foregoing description, a solid-state imaging device having an electronic shutter function can be realized by virtue of the improved device structure in which the signal storage duration can be varied freely.