Semiconductor Device

The present invention relates to a technique which is especially useful when applied to a semiconductor device having a plurality of IIL (i.e., Integrated Injection Logic) elements and, more particularly, to a technique which is effective when applied to a semiconductor integrated circuit device having a logic circuit composed of IIL elements and an analog circuit composed of bipolar transistors.

An IIL element is characterized by a high integration density and a low power consumption. Such an IIL element is produced at a low cost because it can be formed on a substrate by using a similar process to that of fabricating bipolar transistors used in an analog circuit. Therefore, an inexpensive semiconductor device having a logic circuit composed of IIL elements and an analog circuit composed of bipolar transistors has been widely adopted in an IC (i.e., integrated circuit) for public and industrial applications.

The operation speed of the IIL element has been remarkably improved to have a high speed by the recent progress of techniques related to VLSI (i.e., Very Large-Scale Integration) processes and devices. Therefore, the IIL element has been noted as a fundamental circuit for future VLSI.

On the other hand, a wiring method of electrically wiring between semiconductor elements has also been noted in accordance with the recent minute structure of semiconductor elements. This is because the minute structure never fails to promote a higher wiring density.

This high wiring density can be achieved to some extent by adopting a multi-layered wiring structure. Despite of this fact, however, the adoption has to be determined while sufficiently considering how to use the multi-layered wiring layer. If wirings are formed by randomly using the multi-layered wiring layers without determining the usage, the wiring density may sometimes be decreased. This is because the wirings have to be spaced so that they may be prevented from being shorted. Moreover, the drop in the wiring density raises another problem that the integration density of the device itself is also dropped. In the fabrication of the IC composed of highly densified semiconductor elements, therefore, the method of using the multi-layered wirings is considered to become an important target in future.

In the recent design of ICs, on the other hand, the computer-aided design (i.e., CAD) technique for designing the wires between semiconductor elements by using a computer advances to promote shortening of the IC design time.

An object of the present invention is to provide an IIL element wiring technique which is suitable for automation of a wiring design without blocking high densification of the IIL elements.

The aforementioned and other objects and novel features of the present invention will become apparent from the following description given with reference to the accompanying drawings.

The representative of the invention to be disclosed hereinafter will be briefly described in the following.

Specifically, the wirings for connecting a plurality of IIL elements together are composed of: a plurality of first wirings formed in substantially parallel with one another; and a plurality of second wirings which formed in generally parallel one another; the second wirings extending in a direction substantially perpendicular to the extending direction of the first wirings.

The extending direction of the first wirings which formed in generally parallel one another is determined in relation to the construction of the IIL elements and is the same direction as the extending direction of an injector which is provided correspondingly to the plural IIL elements. And, these first wirings are used as wirings between the plural IIL elements formed in a one-side area of the injector and as wirings provided for reducing the resistance of the injector.

On the other hand, the second wirings are used as wirings between the plural IIL elements formed in the one-side area of the injector and the plural IIL elements formed on the other-side area of the injector.

It is advantageous that the interval of the first wirings is made equal to that of the base and collector electrode terminals of each IIL element whereas the interval of the second wirings is made equal to that of the electrode terminals of the IIL elements.

For the device construction, a multi-layered wiring structure is adopted to form the first and second wiring. The first wirings are formed of a first layer of wiring, and the second wiring are formed of a second layer of wiring. This structure is advantageous when considered from the standpoint that the wirings for reducing the resistance of the injector can be connected all over to the injector.

The more specific wiring structure for improving the wiring density has the following characteristics.

The connecting portions between the first and second wirings may preferably be formed on the base or collector electrode terminals of the IIL elements, i.e., on the so-called "element regions".

Moreover, the wiring width of the first and second wirings in the connecting portions may preferably be equal to the wiring width of the first and second wirings in portions other than the connecting portions.

FIG. 1 is a schematic top plan view for explaining a concept of the present invention and shows a state in which first wiring L.sub.Y and second wiring L.sub.X are orthogonally arranged;

FIG. 2(a) is an enlarged top plan view showing a wiring structure of the present invention shown in FIG. 1 and shows a state in which the array pitch a of an IIL gate is larger than the minimum pitch b of the second wirings L.sub.X ;

FIG. 2(b) is a top plan view for explaining devised points, in case the present invention is to be applied, and shows a state in which the respective pitches a and b of the first wirings L.sub.Y and the second wirings L.sub.X are regulated;

FIG. 3(a) is a sectional view of the device related to the ILL element portion, to which the present invention is applied, and shows the characteristics of the contact portions between the first wirings L.sub.Y and the second wirings L.sub.X ;

FIG. 3(b) is a top plan layout showing the device and provides the section view;

FIG. 3(c) is a schematic top plan view of a semiconductor device, to which the present invention is applied, and shows one example of application of a third-layer wiring of a multi-layered wiring structure;

FIG. 3(d) shows an equivalent circuit diagram of FIG. 3(c);

FIG. 3(e) is a schematic top plan view of a semiconductor device, to which the present invention is applied, and shows another example of the third-layer wiring;

FIG. 4 is a schematic top plan view showing a semiconductor device, in which the present invention is applied to an IIL element layout different from that of FIG. 1;

FIG. 5(a) is a top plan layout showing the whole structure of a semiconductor device, to which the present invention is applied, and shows a wiring state of circuit blocks 102 to 105;

FIG. 5(b) is a sectional view of FIG. 5(a); and

FIGS. 6(a), 6(b) and 6(c) are a sectional view, a top plan layout and a circuit diagram showing the IIL, respectively.

Prior to the description of the embodiment of the present invention, the characteristics of the construction of an IIL element will first be described, and the embodiment of the present invention will then be described in detail.

FIGS. 6(a), 6(b) and 6(c) show the construction of an IIL (i.e., Integrated Injection Logic): FIG. 6(a) is a section showing the device; FIG. 6(b) is a top plan layout; and FIG. 6(c) is a basic circuit diagram.

As shown in FIG. 6(c), a basic circuit A of the IIL is composed of a PNP bipolar transistor Q.sub.p1 acting as a current source and an NPN bipolar transistor Q.sub.n1 acting as a logic (or IIL) gate. The PNP transistor Q.sub.p1 has its base connected commonly with the emitter of the NPN transistor Q.sub.n1 and the collector of the PNP transistor Q.sub.p1 is connected commonly with the base of the NPN transistor Q.sub.n1. The NPN transistor Q.sub.n1 has its base (B) acting as an input and its collector (C) acting as an output. The operations of the IIL thus constructed will be described in the following. When this input is at a high level, an injector current I.sub.inj generated by the PNP transistor Q.sub.p1 is fed to the base (B) of the NPN transistor Q.sub.n1 so that the NPN transistor Q.sub.n1 becomes conductive and has its collector potential at a low level. When the input is at the low level, on the other hand, the injector current I.sub.inj provides the collector current of an NPN transistor Q.sub.n2 at an upstream stage so that it is not fed to the base of the NPN transistor Q.sub.n1. As a result, this NPN transistor Q.sub.n1 is left nonconductive to have its collector potential at the high level.

A general device structure of the IIL element is made, as shown in FIG. 6(a), by forming a p-type elongated injector diffusion layer (region) 21 and a p-type base diffusion layer (region) 22 in an n.sup.- -type epitaxial layer, which is formed in a p-type semiconductor substrate, and one or more of n.sup.+ -type collector diffusion layers in the p-type base diffusion layer 22. Equivalently, the base region (i.e., the n.sup.- -type epitaxial layer) of a PNP transistor Q.sub.p as the injector transistor, the emitter region (i.e., the n.sup.- -type epitaxial layer) of an inverse NPN transistor Q.sub.n, the collector region of the PNP transistor Q.sub.p, and the base region of the inverse NPN transistor Q.sub.n are formed in the common semiconductor region so that the integration density of the IIL can be increased.

FIG. 6(b) shows a layout pattern of a plurality of IIL elements. As seen from FIG. 6(b), a plurality of IIL gates (IIL1 to IIL6) are formed in areas S.sub.1 as a first surface area and S.sub.2 as a second surface area on both sides of an injector INJ21 as an elongated injector (semiconductor) region. This injector INJ is provided for the plural IIL gates (IIL to IIL6) and is linearly formed for highly integrating the IIL gates. Incidentally, the wiring between the IILs are omitted from FIG. 6(b) so as to simplify the illustration but are shown for the impurity-introduced layers 21, 22 and 3. A plurality of spaced semiconductor regions 22 face to but spaced from one elongated side S.sub.1 and S.sub.2 of the elongated region 21. As to bases indicated by broken lines, on the other hand, there are shown portions where the bases and the aluminum as wirings are connected. Moreover, the device section taken along line VI(a)--VI(a)' corresponds to FIG. 6(a).

A representative embodiment of the present invention will be described in the following with reference to the accompanying drawings.

Incidentally, the common reference characters appearing in the drawings to be used in the following description are assumed to designate the same or corresponding portions.

FIG. 1 is an enlarged schematic top plan view showing an essential portion of a semiconductor device to which the present invention is applied.

FIG. 1 is an enlarged view showing the IIL element forming portion of a semiconductor device in which an IIL element is formed. It is characteristic that the wirings between the IIL elements are composed of a plurality of first wirings L.sub.Y as first conductive or first elongated conductive members, which are arranged in an identical direction, and which formed in generally parallel one another, i.e., in a Y direction; and a plurality of second wirings L.sub.X which formed in generally parallel one another, and which are arranged in a direction substantially perpendicular (or orthogonal) to those first wirings L.sub.Y, i.e., in an X direction. In FIG. 1, the first wirings L.sub.Y are indicated by broken lines whereas the second wirings L.sub.X as first conductive layers or first elongated conductive members are indicated by solid lines.

As seen from FIG. 1, the first wirings L.sub.Y and the second wirings L.sub.X are regularly used to effect the electric connections of the plural IIL elements. This facilitates the software of the automatic wiring design (i.e., the computer-aided design, as will be abbreviated into "CAD") using a computer. This results in shortening the design time of a semiconductor device.

The aforementioned first and second wirings L.sub.Y and L.sub.X are formed by using a multilayer wiring structure. Specifically, the first wirings L.sub.Y are made of a first layer wiring whereas the second wirings L.sub.X are made of a second layer wiring. Namely the first and second wirings are formed at different level. The first and second wirings L.sub.Y and L.sub.X can be electrically connected by forming through holes TH in a first inter-layer insulating film as insulative material which is formed on SiO.sub.2 or the like between the first and second layer wiring. Blank circles appearing in FIG. 1 designate the through holes TH. On the other hand, the sold circles designate the contact portions between the first wirings and the base (or collector) regions of IIL gates. Incidentally, for simplicity of illustration, only the blank circles are located at the portions, in which the first wirings L.sub.Y and the second wirings L.sub.X are connected on the base or collector regions of the IIL gates but in which the first wirings L.sub.Y and the base or collector regions of the IIL gates contact as a matter of fact. Moreover, those ones of the second wirings L.sub.X, which terminate on the base or collector regions, are underlaid by the portions of the first wirings L.sub.Y contacting with the base or collector regions. Still moreover, the respective wirings L.sub.Y and L.sub.X are made of aluminum.

The characteristics of the method of using the first wirings L.sub.Y and second wirings L.sub.X described above will be described in more detail in the following with reference to FIGS. 2(a) and 2(b).

FIGS. 2(a) and 2(b) shows the first wirings L.sub.Y and the second wirings L.sub.X in an enlarged scale.

As shown in the figure, the first wirings L.sub.Y are formed in the first layer of the multilayer wiring whereas the second wirings L.sub.X are formed in the second layer of the same. Moreover, the first wirings L.sub.Y and the second wirings L.sub.X are suitably connected through the through holes TH so that the wirings of plural IIL gates are regularly effected. Incidentally, the through holes TH are designated by symbols "X", and the contacts CONT are designated by symbols "/".

The first wirings L.sub.Y are arranged in the same direction as the running direction (Y) of the injectors INJ21 of the aforementioned IIL elements. On the other hand, the second wirings L.sub.X are arranged in the direction (X) perpendicular to the running direction (Y) of the injectors INJ21. As a result, the electrodes of the injectors INJ can be formed by the first wirings L.sub.Y so that they can be kept in contact with the whole or the part surface of the p-type injector diffusion layer 21. This leads to an advantage of reducing the diffusion resistance of the doped injector diffusion layer 21 to uniform the operating speeds of the plural IIL gates.

By the second wirings L.sub.X, the plural IIL gates, which are formed in the areas S.sub.1 and S.sub.2 on both sides of an injector electrode L.sub.Y21, are connected with each other across the injector electrode L.sub.Y21. Namely, the wiring L.sub.X extend transversely to the elongated region 21 or the electrode 21.

More specifically, the first wirings L.sub.Y are used to connect the plural IIL gates which are formed in the areas S.sub.1 (or S.sub.2) on one side of the injector electrode L.sub.Y21. On the other hand, the second wirings L.sub.X are mainly used to electrically connect the IIL gate formed in the areas S.sub.1 and the IIL gate formed in the areas S.sub.2 across the injector electrode L.sub.Y 21 connected with the whole or part surface of the injector diffusion layer 21 so as to reduce the resistance of the same layer 21.

FIG. 2(a) shows the case in which the gate array pitch a of the IIL gates is larger than the minimum array pitch b of the second wirings L.sub.X. Between the IIL gates, the wirings L.sub.Y and L.sub.X are electrically connected to make effective use of a region Z between the IIL gates thereby to improve the wiring density.

On the other hand, FIG. 2(b) shows the state in which the present invention is applied to other IIL gates. The difference from FIG. 2(a) are: in that the gate array pitch a of the plural IIL gates is equal to the minimum array pitch of the second wiring layers L.sub.X ; the electrode pitch d between the base B of the IIL gates and the collectors C is equal to the minimum array pitch of the first wirings L.sub.Y ; and in that the wirings L.sub.Y and L.sub.X are connected on the gate electrodes such as the bases or collectors of the IIL gates. Thanks to those differences in the construction, it is possible to make the array pitch d of the gate electrodes and the array pitch of the wirings L.sub.Y equal to each other and the gate array pitch a and the array pitch of the wirings L.sub.X. As a result, the automatic wiring design by the CAD can be better simplified.

FIGS. 3(a) and 3(b) are diagrams for explaining the structural characteristics of the aforementioned first wirings L.sub.Y, second wirings L.sub.X and through holes TH for making the wiring structure shown in FIG. 2(b). FIG. 3(b) is a device layout, and FIG. 3(a) is a device section view.

FIG. 3(a) shows a section showing a state in which the base B of the IIL gate (i.e., IIL1) and the collector C of the IIL gate (i.e., IIL2) are connected through the second wirings L.sub.X. The wirings L.sub.X are connected with the wirings L.sub.Y acting as the gate electrodes of the IIL gates (i.e., IIL1 and IIL2) through the through holes TH1 add TH2 which are formed in a first interlayer insulating film 5. It should be noted that the width W.sub.1 of a gate electrode L.sub.YB (or L.sub.YC) is made slightly larger than the width W.sub.2 of the through hole TH1 (or TH2), as shown in FIG. 3(a). In an alternative, although not shown, the width W.sub.1 of the gate electrode L.sub.YB (or L.sub.YC) and the width W.sub.2 of the through hole TH1 (or TH2) are made to have substantially equal values. In other words, the area of the gate electrode L.sub.YB (or L.sub.YC) exposed through the through hole TH1 (or TH2) is made substantially equal to or slightly smaller than the area of the gate electrode L.sub.YB (or L.sub.YC) viewed from above.

As shown in FIG. 3(b), the width W.sub.LYCONT of the contacting portion CONT of the wiring L.sub.Y with the collector 3 (or the base 22) is made equal to the width W.sub.LC of the wiring L.sub.Y in portions other than the aforementioned contacting portion CONT. Therefore, the wiring L.sub.Y is devised not to bulge at the contacting portion CONT. Likewise, the width W.sub.LXTH of the wiring L.sub.X at the through hole TH is made equal to the width W.sub.LX of the wiring L.sub.X in portions other than the through hole TH. By these devices, the improvement in the wiring density is achieved.

The cautions of the array of the IIL gates shown is FIGS. 2(b) and 3(b) will be described in the following. In FIGS. 2(b) and 3(b), both the pitch of the wirings L.sub.Y and the pitch of the gate electrodes in the IIL gates are made to have the common value d, and the array pitch of the wirings L.sub.X and the array pitch of the IIL gates are made to have the common value a. In this case, it is the value of the gate electrode pitch d that should be noted. This gate electrode array pitch d is so designed that the inverse current amplification factor .beta..sub.i of the npn inverse transistor Q.sub.n1 (or Q.sub.n2) shown in FIG. 6(c) may be sufficiently retained. It has been confirmed by our experiments that inverse current amplification factor .beta..sub.i is proportional to the area ratio S.sub.C and S.sub.B of the area S.sub.C of the collector diffusion layer 3 of the IIL gate viewed from above to the area S.sub.B of the base diffusion layer 22 of the same viewed from above. It is therefore necessary that the array pitch d of the wirings L.sub.Y be determined from the value of the area ratio S.sub.C /S.sub.B, i.e., the minimum inverse current amplification factor .beta..sub.i required by the IIL. In the fabrication process the development of which was handles by us, the area ratio (S.sub.C /S.sub.B) has a value of S.sub.C /S.sub.B .apprxeq.0.078, and the inverse current amplification factor .beta..sub.i of .beta..sub.i .apprxeq.4. It is, however, thought that the relation between the value of the area ratio S.sub.C /S.sub.b and the inverse current amplification factor .beta..sub.i is determined by the fabrication process, and that the inverse current amplification factor .beta..sub.i is to be improved by promising development in the fabrication process.

By making the formations of the wirings L.sub.Y and L.sub.X regular, as described above, the wirings for connecting the IIL gates can be suited for automations by the CAS (i.e., Computer-Aided Design) system. Thus, the wiring design can be optimized for sufficiently automating the wiring design and making the best use of the advantages of the IIL.

Incidentally, in FIG. 3(a), reference numeral 4 designates a surface insulating oxide film, and numeral 5 a first inter-layer insulating film made of a silicon oxide film or a polyimide resin (e.g., polyimideisoindro-quinazolinedion).

Next, the wiring direction of third wirings L.sub.Z will be described with reference to FIGS. 3(c), 3(d) and 3(e).

FIG. 3(c) is a top plan view, and FIG. 3(d) is an equivalent circuit diagram of the same. As shown, the third wirings L.sub.Z are so drawn as are thicker than the first and second wirings L.sub.Y and L.sub.X. It should be noted in FIG. 3(c) that the wirings L.sub.Z are wired in the same direction as the wirings L.sub.Y formed on the injector INJ and are electrically connected at several portions by the wirings L.sub.X. As a result, as shown in the equivalent circuit diagram of FIG. 3(d), the voltage drop of the injector INJ due to the unnegligible parasitic resistances R, R and so on of the wirings L.sub.X is reduced to uniform the voltage between the two terminals of the injector INJ elongated on the substrate and equalizes injector currents I.sub.j and I.sub.j ' to uniform the speed of the IIL gates.

FIG. 3(e) shows the method of wiring the wirings L.sub.Z in a finer IIL element. In case the gate array pitch a is made smaller than the minimum array pitch b of the second wires L.sub.X so as to ensure that fineness, an IIL gate incapable of being wired by the wirings L.sub.X is formed across the injector INJ. These IIL gates are wired by the wirings L.sub.Z. As a result, the gate array pitch a can be made equal to the array pitch f between the wirings L.sub.X and L.sub.Z to facilitate the automatic wiring by the CAD.

FIG. 4 shows the case in which the present invention is applied to another array example of the IIL gates. In FIG. 4, there is shown a high-speed IIL circuit in which the gate electrode (i.e., the base B or collector C) of each IIL gate is arrayed in parallel with the injector INJ. In a semiconductor integrated circuit device formed with the IIL gates (IIL1 to IIL6) having such a layout, the first wirings L.sub.Y are formed in the first layer of the multi-layered wiring structure, and the second wirings L.sub.X are formed in the second layer of the same. The first wirings L.sub.Y are formed in the same direction as the gate electrode array direction (Y) in the IIL gate. On the other hand, the second wirings L.sub.X are formed in the direction perpendicular to the gate electrode array direction (Y).

Moreover, the extending direction of the first wirings L.sub.Y is identical to that of the injection diffusion layers 21, whereas the extending direction (X) of the second wirings L.sub.X is perpendicular to that of the injector diffusion layers 21. Most of the second wirings L.sub.X are used to connect the IIL gates IIL1 to IIL3 formed in the area S.sub.1 formed on one side of each injector diffusion layer 21 and the IIL gates IIL 4 to IIL6 formed in the area S.sub.2 on the other side. On the other hand, most of the first wirings L.sub.Y are used to connect the IIL gates in the area S.sub.1 (or S.sub.2).

FIG. 5(a) shows the overall construction of the semiconductor integrated circuit device thus far described.

In a semiconductor integrated circuit device 100 shown in FIG. 5(a), a plurality of IILs are formed in each of blocks 102, 103, 104 and 105 by both the first wirings L.sub.Y formed in the first layer of the multilayer wiring structure and the second wirings L.sub.X formed in the second layer of the same to wire the IIL gates of those blocks. Moreover, the blocks are also wired by the third wirings L.sub.Z as first and second and third conductive strips which are formed in the third layer of the multilayer wiring structure. Therefore, the first wirings formed over a first insulative material covering the substrate, and the second wirings formed over a second insulating material covering at least the first wirings, and the third wirings disposed over a third insulative material. As a result, the plural IIL elements or linear elements (or analog circuit elements) constitute one circuit function block, and a plurality of these circuit function blocks are connected to constitute the semiconductor integrated circuit device 100 having an arbitrary function. In this case, moreover, the wirings in and between the blocks are formed in the different wiring layers so that they can be designed independently of each other without any interference. As a result, by changing only the wirings between the blocks while leaving the functions in the blocks as they are, for example, it is possible to freely construct a variety of semiconductor integrated circuit devices having high functions. Reference numeral 101 appearing in FIG. 5(a) designates bonding pads.

FIG. 5(b) is a sectional view of a portion of the semiconductor integrated circuit device 100, to which the present invention is applied and shows portions of the circuit block 102 composed of a plurality of IIL elements and the circuit block 104 having a bipolar transistor BIP as a linear element (or analog circuit element).

As has been described above, the IIL element portion is constructed of: a substrate 1 having a p-type semiconductor substrate 10, an n.sup.- -type epitaxial layer 12 formed on the substrate 10, and a buried layer 11 formed selectively between the semiconductor substrate 10 and the n.sup.- -type layer 12; an injector diffusion layer 21 and a base layer 22 formed selectively in the principal face of that substrate 1; and collector layers 3, 3 and so on formed in the principal face of the base layer 22. On the other hand, the bipolar transistor Bip is constructed of: a collector buried layer 13 formed simultaneously with the buried layer 11 of the IIL portion; an n.sup.- -type epitaxial layer 14 formed simultaneously with the n.sup.- -type epitaxial layer 12 of the IIL portion; a base layer 23 formed simultaneously with the injector layer 21 and the base layer 22 of the IIL portion; and an emitter layer 31 formed simultaneously with the collector layer 3 of the IIL portion. Likewise and simultaneously formed are an emitter electrode leading layer 41 of the IIL portion and a collector electrode leading layer 42 of the bipolar transistor. In the fabricating process, are selectively formed on the p-type semiconductor substrate 10 the buried layers 11 and 13, on which is formed the epitaxial layer 12 (or 14). Then, an inter-element separating layer 20 is formed, and the individual electrode leading layers 41 and 42 are formed. After this, the injector layer 21 and the base layer 22 of the IIL portion and the base layer 23 of the bipolar transistor Bip are formed, and the surface oxide film is selectively etched to form the contact holes CONT. After this, the electrodes or wirings of each element are formed by the first wirings L.sub.Y. After this, the first inter-layer insulating film 5 made of a polyimide resin or the like is formed. After the through holes TH are formed in the portion of the insulating film 5, the second wiring L.sub.X are formed to be connected with the first wirings L.sub.Y Next, a second inter-layer insulating film 6 made of a polyimide resin or the like is prepared and is again formed selectively with the through holes. Then, the third wirings L.sub.Z are formed and covered with a passivation film 7 made of a polyimide resin or the like. Incidentally, this passivation film 7 on the bonding pad 101, as shown in FIG. 5(a), is removed, and the resultantly exposed portions of the bonding pad 101 are connected with Au wires. As described above, the bipolar transistor and the IIL can be formed by the common fabrication process so that an IC can be produced at a reasonable cost without any increase in the process cost.

The results of the present invention will be described in the following.

The IIL gates are connected by the first wirings arranged in a common direction, the second wirings arranged in the direction perpendicular to the first wires, and the through holes connecting the first and second wirings, so that the wires connecting the IIL gates can be regulated suitably for automation. This results in an effect to automate the wiring design and sufficiently optimize the advantages of the IIL elements.

Although the present invention has been specifically described on the basis of the embodiment, it should not be limited to the embodiment but can be variously modified without departing from the gist thereof. For example, the electrodes of the aforementioned injectors need not be led out all over the surface but can be led out partially from suitable portions. Moreover, plural columns of injectors having different running directions may be arranged in parallel.

Although the present invention has been described hereinbefore in case it is applied to the analog/digital composite type semiconductor integrated circuit device, it should not be limited thereto but can be applied to an especially digital semiconductor integrated circuit device of a bipolar/MOS composite type semiconductor integrated circuit device, for example.