Bit-Map CRT Display Control

This invention relates to a method and apparatus for controlling a CRT display. More particularly, this invention relates to a method and apparatus for controlling a bit-mapped raster type CRT display.

CRT's have long been known as a useful output device for the display of information where a permanent record was not necessary. They provide a high speed, quiet and inexpensive output device for displaying information to an operator. Hertofore, two types of CRT display have been used; a vector, or X-Y plot, display and a raster display. The vector display is useful for the display of graphic information. In a vector display vectors, or directed line segments, are drawn between any two arbitrary points on the CRT display screen. Such line segments are typically straight but may in more advanced systems be curved line segments. Such vector displays are useful for the display of graphic or pictorial information. The other type of display which heretofore has been commonly used is a raster type display wherein the CRT traces out a raster consisting of a sequential set of essentially horizontal scan lines, typically beginning at the top left hand corner and tracing lines from left to right and top to bottom. After completing the full set of lines, commonly referred to as a frame, the CRT returns to the top left hand corner to begin a new frame. As the beam traces out each frame the beam is modulated by a video signal to display information on the CRT face. Typically, for the display of information from a data processing system the CRT beam is modulated by a digital signal which may only provide for "on" and "off" states or may provide for a limited number of other attributes such as a limited number of colors, bolded operation, or blinking operation. (those familiar with the television art will recognize the similarity between a raster display as described herein and a television raster display, though typically, a display used with a data processing system will not provide for an interlaced raster or for a continuously variable analog video input signal, as is provided in a television raster.)

Raster displays have heretofore been most useful for the display of patterns of limited numbers of predetermined signals, (e.g., text). The symbol patterns, (e.g., letters) could be stored in memory and scanned to generate a video signal in synchronism with the raster display. Further, since raster displays are less expensive to build and place less the computational burden on a processing unit, heretofore raster displays have been used for the display of graphic information by a technique known as "bit-mapping".

A schematic block diagram of a typical apparatus useful for display of bit-mapped information is shown in FIG. 1. A processor (not shown) loads data over data bus 30 into memory 10 in accordance with addresses on address and control bus 20. The processor establishes a sequence of data words in memory 10 corresponding to a "bit-map" of the display raster. That is, each bit in sequence corresponds to a "on-off" signal for a particular picture element to be displayed.

Once a bit-map is stored in memory 10 the processor issues an I/O instruction to control 40 which then sequentially unloads the data words in memory 10 to serializer 50, which outputs a serial bit stream of data to the CRT video input. Control 40 contains logic which allows it to read data from memory 10 in synchronism with the raster display and control 40 further provides horizontal synchronization signals for each line and vertical synchronization signals for each frame to maintain the raster in synchronism with the bit stream being output from serializer 50. The I/O instructions issued by the processor may be a simple initialization command where the bit-map is always stored in the same memory locations or may define a starting memory location. Access to memory 10 for both the processor and control 40 is through contention logic 60 so that the processor and the control may access memory 10 concurrently.

Apparatus such as that shown in FIG. 1 has proved useful, especially in applications where the simultaneous display of graphics and textual information was desired. However, such apparatus still presented certain problems. In particular when a display was to be changed it was necessary to extensively rework the bit-map stored in memory 10. The simple insertion of a few lines into the bit-map might require that the entire bit-map be rewritten.

In considering this problem applicant noted a heretofore unobserved analogy between the problem of controlling a bit-map display and problems in programming and text processing. All three, applicant realized, could be viewed as involving manipulation of ordered sets of symbols. In both programming and text processing strings of symbols, i.e., program code or text symbols, were linked by pointers. That is, each string of symbols was followed by data which defined the initial address of the next string. Thus, by modification of these pointers strings of symbols could be linked or unlinked.

Thus, considering the above background, it is an object of the subject invention to provide a method and apparatus wherein the data processing required to alter a CRT raster display is minimized.

It is another object of the subject invention to minimize the memory required to store and reorganize a bit-mapped display.

It is still another object of the subject invention to provide an apparatus wherein the memory used to store a bit-map may be shared concurrently by a processor and a controller. It is still another object of the subject invention to provide a method and apparatus which provide output signals in such a form that the method and apparatus may be used by standard CRT display without modification.

The disadvantages of the prior art are overcome and the above objects are achieved in accordance with the subject invention by means of an apparatus for controlling a bit-mapped CRT display raster which includes a buffer memory for storing data, the stored data further including data constituting a picture element by picture element mapping of the information to be displayed, the mapping data consisting of groups of sequential words, each of the groups constituting a picture element by picture element mapping of a single scan line and the data further including pointers associated with the groups; each of the pointers indicating the starting address of the group associated with the next scan line, and means responsive to the pointers for outputting the mapping data as a serial bit stream with each group being synchronized with its associated scan line so that the mapping data is displayed in said display raster.

In another embodiment the apparatus of the subject invention includes a buffer memory and a processor operatively associated with the buffer memory, the processor storing data in the buffer memory, including data constituting a picture element by picture element map of the information to be displayed, the mapping data consisting of groups of sequential data words, each of said groups constituting a picture element by picture element mapping of a single scan line of the raster and the data further including pointers associated with said groups; each pointer indicating the initial address of the group associated with the next scan line, and the apparatus of this embodiment further including circuitry responsive to said pointers for outputting the mapping data as a serial bit stream; each of the groups of mapping data being synchronized with its associated scan line. The synchronized bit stream may be used as a video input signal to a CRT.

The above apparatus may be used in accordance with the method of the subject invention by storing sequential groups of data words defining a bit-map of associated scan lines in a buffer memory, storing pointers associated with the groups in the buffer memory the pointer defining the initial address of the next group, sequentially outputting and serializing the first group synchronously with the first scan line, determining the initial address of the next group from the associated pointer, sequentially outputting and serializing the next group synchronously with the next scan line, repeating the previously two steps until the last group is output and returning to output the first group again synchronously with the first scan line.

Thus, it may be seen that the subject invention advantageously provides a method and apparatus whereby the time required to alter a bit-mapped display is significantly reduced.

It is a further advantage of the subject invention that it achieves the above objects while requiring only relatively minor changes to the circuitry of the display control and only relatively minor changes in programming.

Other objects and advantages of the subject invention will be obvious to those skilled in the art from a consideration of the detailed description set forth below and the attached drawings.

FIG. 1 is a schematic block diagram of a piror art apparatus for controlling a CRT raster display.

FIG. 2 is a schematic block diagram of an apparatus in accordance with the subject invention.

FIGS. 3 and 3a are a schematic block diagram of control circuitry for the apparatus of FIG. 2.

FIGS. 4 and 4a are a sequence diagram for the operation of the control logic of FIG. 3.

FIGS. 5a and 5b are a representation of the storage and display of a raster in accordance with the subject invention.

FIGS. 6a and 6b are a representation of the storage and display of a raster which is modified by "wrapping-around" one line.

FIGS. 7a and 7b are a representation of the storage and display of a raster which is scrolled down one line in accordance with the subject invention.

FIGS. 8a and 8b are a representation of a raster which is scrolled up one line in accordance with the subject invention.

FIGS. 9a and 9b are a representation of the storage and display of a raster wherein a substitute line is inserted in accordance with the subject invention.

Referring to FIG. 2, a schematic block diagram of an apparatus in accordance with the subject invention is shown. It may be noted that the apparatus of FIG. 2 differs from that of the prior art, as shown in FIG. 1, in that controller 70, which accesses data bus 30 and has been substituted for controller 40. Because controller 70 accesses data bus 30, pointers, as described below, may be read by controller 70 allowing controller 70 to "link" groups of data words representing sequential scan lines in a manner which will be described more fully below. Also, it will be noted that the inputs and outputs of the apparatus of FIG. 2 remain unchanged from those of the apparatus of FIG. 4, thus, ensuring that the apparatus of the subject invention may be readily substituted for prior art apparatus.

FIGS. 3 and 3a show a more detailed schematic block diagram of controller 70 of FIG. 2. Considered in conjunction with FIGS. 4 and 4a, these figures show the operation of the apparatus of the subject invention.

Prior to time t.sub.0 the processor (not shown) issues an initialization signal on line INIT. In response sequence control 72 issues a clear signal on line CLR to address register 78. At time t.sub.0 control 72 issues two memory read signals on line RDM and the memory responds with two data ready signals on line DRY. Between the RDM signals address register 78 is incremented by a signal on line INC and as each DRY signal is received the data is sequentially strobed from data bus 30 into buffer registers 74a and 74b by a signal on line STB. Sequence control 72 then transfers data from register 74a and 74b into address register 78 by generating a signal on line STA; thus reading the pointer for the initial address of the initial scan line group from memory locations 0 and 1.

Optionally the range of addressable memory locations may be extended by the addition of buffer register 76 which is loaded by a processor I/O instruction coincidently with the INIT instruction, providing an additional 8 bits of memory address range.

In another preferred embodiment the initial pointer need not be stored in memory but may be transferred by a sequence of I/O operations to registers 74a and b and 76 as shown in FIGS. 3a and 4a.

No matter which technique is used, however, to establish the initial address of the initial scan line group; at time t.sub.1 sequence control 72 issues another RDM signal and memory 10 responds with a DRY signal Sequence controller 72 then issues a strobe signal on line STS to serializer 50 loading the first word of the first scan line group into serializer 50. Sequence control 72 then issues a series of 8 clock pulses on line CLK to serializer 50 shifting the 8 bits of data out in a serial form to the video input of the CRT. While the data word is being output by serializer 50 sequence control 72 issues a signal on line INK to address register 78 to increment to the next word in the scan line group.

(For purposes of this illustrative description a non-interlaced scan of 300 lines, with 400 picture elements per line and a frame repetition rate of 30 frames per second is assumed. Allowing time for scan retrace, both vertical and horizontal, this yields a bit rate of approximately 4 megabits per second (and clock rate of approximately 4 megahertz). Also, for simplicity of description, the bit map will consist of one bit per picture element, though those skilled in the art will recognize that additional bits may be added in parallel memory planes to provide more attributes per picture element.)

Thus, at time t.sub.3 in FIG. 4 sequence control 72 repeats the cycle shown from time t.sub.1 to t.sub.3 for the next word in the scan line group. From time t.sub.3 to time t.sub.4 this cycle is repeated for words one through 49 of the initial scan line group. (it should be noted that though in FIG. 4 considerable separation is shown between signals on the CLK line this is for ease of illustration only. Those skilled in the art will recognize that memories having cycle times of less than 250 nano seconds are readily commercially available and that the next word may be transferred to serializer 50 within one CLK cycle so that data may be presented smoothly and without interruption. Alternatively the RDM signal maybe generated one or two CLK cycles before time t.sub.3 (as shown at "A" in FIG. 4) so as to assure the availability of the data on data bus 30 at time t.sub.3.)

At times t.sub.4 to t.sub.5 sequence control 72 repeats the cycle from t.sub.0 to t.sub.1. Signal address register 78 then accesses the next two data words at the end of the initial scan line group and the information is strobed by the STB signal into buffer registers 74a and 74b from data bus 20 and then transferred to address register 78.

From times t.sub.5 to t.sub.7 words 0-49 of line 1 are output and serialized by repeating the cycle as described above.

The cycle shown from times t.sub.3 to t.sub.6 is repeated for lines 1-299 to display a full raster. The time from time t.sub.7 to t.sub.8 is a pause to allow for vertical retrace.

Horizontal blanking signal HB and vertical blanking signal VB are generated for the CRT at the appropriate times to blank the video signal for retrace and to maintain synchronization with the data bit stream from serializer 50 by sequence control 72 as shown in FIG. 4.

At time t.sub.7 sequence control 72 generates a signal on line FRE to the processor (not shown) to indicate that a frame is complete. After receiving the FRE signal the processor (not shown) may generate an INIT signal or may extend the pause to modify the bit-map as described below.

Returning to FIG. 2, contention resolution logic 60 preferably allows the processor to access memory 10 on a "cycle-scaling" basis. That is, the processor (not shown) may access memory 10 for one cycle whenever controller 70 is not accessing memory 10. If the memory cycle time is sufficiently short with respect to the access cycle of controller 70 such cycle stealing will not visibly effect the display. Alternatively, as described above, sequence controller 70 may generate the RDM signal one or two CLK cycles early as shown at "A" in FIG. 4 to prevent interference with its access to memory 10 and assure a smooth bit stream from serializer 50. (such "cycle-stealing" control of memory access is well known to those skilled in the art and need not be described further here for an understanding of the subject invention.)

In FIG. 5a and 5b a typical raster is shown as stored in memory 10 and, in a highly stylized fashion, as displayed on the CRT. The first scan line group is stored in memory locations i through i+49 and is represented in FIG. 5b by "a". Locations i+50 and i+51 contain the low order and high order bits of a pointer to location j. The second scan line group is stored in memory locations j through j+49, and is shown in FIG. 5b as the scan line represented by "b". Locations j+50 and j+51 contain the low order and high order bits respectively of a pointer to location k which stores the first word of the scan line group for the third scan line (not shown). Other locations not shown store the other scan line groups between scan lines 2 and 297 and scan line group 298 is stored in locations l through l+49 and is shown in FIG. 5b as the scan line represented by "y". Locations l+50 and l+51 again contain the pointer to location m where scan line group 299, the last scan line begins. Note that locations m+50 and m+51 are reserved but are not defined since the sequence control is re-initialized for each frame.

The initial pointer for location i is shown in FIG. 5a as being stored in memory locations 0 and 1. However, as described above the initial pointer may be either wholly or partially transferred to controller 70 through I/O operations from the processor.

FIG. 6 shows a representation of the storage and display of the raster display of FIG. 5 which has been modified by a "wrap-around" operation. The processor has modified the pointer in location 0 and 1 to point to the second scan line, represented by "b" in FIG. 6b and modified the pointer in locations m+50 and m+51 to point to location i. The resultant display is seen in FIG. 6b wherein all display lines are moved upward one line and the initial line represented by "a" is "wrapped-around" to the bottom of the display. Thus, it may be seen that the display may be readily be altered simply by changing the correlation between the groups of data words and the scan lines by a simple adjustment of the pointers.

FIG. 7 shows a representation of the storage and display of the raster display of FIG. 5 which has been scrolled down one line. The processor has stored a new line in locations n through n+49 with a pointer in locations n+50 and n+51 pointing to the original initial line "a" in location i. To scroll the display up one scan line the processor rewrites the initial pointer in locations 0 and 1 to point to location n. Note that the last line displayed is now stored in locations l through l+49 and that the pointer in locations l+50 and l+51 still points to location m but is no longer used during the display.

FIG. 8 shows a representation of the storage and display of the raster display of FIG. 5 which has been scrolled up one line. The processor stored a new line in locations n through n+49 and reserves locations n+50 and n+51 for a pointer. To scroll the display up one line the processor rewrites the initial pointer in locations 0 and 1 to point to location j and stores a pointer to location n in the reserved pointer at locations m+50 and m+51. As seen in FIG. 8b this results in the shifting up of each line in the display and the substitution of line "s" for the bottom line of the display.

FIG. 9 shows a representation of the storage in display of the raster display of FIG. 5 where a substitution has been made. Again the processor stores a new line in location n+49 and stores a pointer to location k in locations n+50 and n+51. To substitute the line stored in location n through n+49 for the line represented by "b" the processor rewrites the pointer in location i+50 and location i+51 to point to location n. The resulting substitution is seen in FIG. 9b where the line represented by "s" is substituted for the line represented by "b".

Those skilled in the art will recognize that the operation shown in FIGS. 6-9 need not, of course, be limited to operations on single scan lines. Simply by assembling appropriately linked groups the display may be scrolled by an arbitrary number of lines or an arbitrary number of lines may be substituted into a display. Further, merely by rewriting the pointers appropriately existing lines may be rearranged in a completely arbitrary manner. Further it should be noted that while new groups may be stored and linked in memory 10 at any time during the display cycle it is preferable that the active pointers be modified only during the pause at time t.sub.7 time and before the processor re-initializes control 70 to prevent the accidental modification of a pointer while it is being used, which might result in a display of "garbage" on the CRT. To provide time for modifying the active the processor may extend the pause and delay re-initialization for the next frame until the pointers are appropriately linked for the display.

The above description of preferred embodiments and the attached drawings have been provided by way of illustration only and numerous other embodiments of the subject invention will be apparent to those skilled in the art from the examples and illustrations provided. Thus, the limitations on the claimed invention are to be found only in the claims set forth below.