Method of Fabricating Airbridge Metal Interconnects

This invention relates, in general, to manufacturing semiconductor devices and, more particularly, to a method of making airbridge metal interconnects on semiconductor devices.

Airbridge metal interconnects are typically employed in gallium arsenide devices, such as microwave integrated circuits. Gallium arsenide devices are used in high frequency applications. The performance of high frequency integrated circuits is significantly reduced if high parasitic capacitances are present. Airbridge technology reduces parasitic capacitances, thus permits high frequency integrated circuits, greater than 1 GHz, to function with lower loss and a higher gain than those fabricated with non-airbridge technologies. An airbridge metal interconnect is one in which the typical dielectric layer is replaced by air. Using nitride or oxide as a dielectric layer is not acceptable in high frequency devices because the high parasitic capacitances of nitride or oxide result in unacceptable high loss and low gain.

In the past, airbridges have been fabricated by applying a bottom photoresist layer to the surface of the device structure. Subsequently, the bottom photoresist layer is patterned and a thin metal ground plane is evaporated onto the surface. Another layer of photoresist is applied and patterned over the metal ground plane A thick layer of metal is then electroplated in the openings of the top photoresist. A problem then arises when removing the top photoresist layer; the developer or solvent used to remove the top photoresist layer also dissolves the bottom photoresist layer through the sides of the structure and through the thin metal ground plane. The ground plane metal, typically comprised of titanium and gold, is then removed with hydrofluoric acid and a cyanide based acid called Technistrip. Hydrofluoric acid is an etchant for titanium, but it also etches nitride, thus any nitride on the underlying device surface is also etched if there are regions in the bottom photoresist layer which have been dissolved. The cyanide based acid etches gold, thus other gold on the underlying device structure is also etched. This will result in poor device yields. Thus, there is a need to provide a method of forming airbridge metal interconnects where the underlying semiconductor device structure is not disturbed.

One such method involves using an ion-miller process to remove the top photoresist layer and ground plane metal. The ionic milling etches only in the vertical direction, thus does not attack the bottom photoresist through the sides. Using an ion-miller process is effective, however, is more expensive than using solvents and wet etches to remove the top photoresist layer and the metal ground plane. In addition, an ion-miller process can potentially leave metal residue over the wafer. Other methods of fabricating airbridge metal interconnects use a photoresist lift-off technique. Lift-off techniques, however, do not have good process latitude for thick metal. Thus, methods other than lift-off techniques are desirable to increase yield.

By now, it should be appreciated that it would be advantageous to provide a method of fabricating airbridge metal interconnects with an improved process yield.

Accordingly, it is an object of the present invention to provide an airbridge metal interconnect process which produces stable airbridge structures.

Another object of the present invention is to provide a method of fabricating airbridge interconnects without etching of the underlying device structures.

An additional object of the present invention is to provide an improved method of fabricating airbridge interconnects which has good process latitude, thereby leading to higher device yields and the ability to make high frequency devices.

In accordance with the present invention, the above and other objects and advantages are achieved by providing a method of fabricating an airbridge metal interconnect by using two photoresists having different solubility characteristics. A first photoresist layer is deposited onto a semiconductor device structure and is then patterned. A metal ground plane is then formed on the surface of the first photoresist layer and the device structure. A second photoresist layer, different than the first photoresist layer, is then deposited and patterned. Subsequently, a metal interconnect is formed on the exposed metal ground plane. The second photoresist layer is removed, without dissolving the first photoresist layer, since it has different solubility characteristics. The metal ground plane is then wet etched without etching the underlying semiconductor structure. Thus, stable metal interconnect layers are formed with high yields.

FIGS. 1-7 illustrate enlarged cross-sectional views of a portion of a semiconductor structure embodying the present invention in various stages of development.

The preferred embodiments of the present invention are illustrated in the accompanying drawings for purposes of exemplification, and are not to be construed as limiting in any manner.

FIG. 1 illustrates a semiconductor device structure at a intermediate step in the fabrication process. Device structure 10 illustrates a substrate 11 with a polymer 12 applied and patterned on its surface. Substrate 11 is an integrated circuit structure in the final stages of fabrication. In a preferred embodiment, polymer 12 is a positive photoresist layer. A positive photoresist layer is used only to obtain good definition, otherwise a negative photoresist layer may also be used. Here, a positive photoresist layer S2400-33 provided by the Shipley Company is used. The thickness of photoresist layer 12 determines the spacing of the airbridge metal interconnect to be formed; a thickness of approximately 2 to 3 microns is used in this embodiment.

FIG. 2 illustrates device structure 10 of FIG. 1 with a metal ground plane 13 formed on the surface. Metal ground plane 13 can be formed by suitable techniques known in the art, such as evaporation, sputter, or the like. Metal ground plane 13 is preferably comprised of a titanium layer and a gold layer. The titanium provides good adhesion to the surface of semiconductor substrate 11, and the gold acts as a good conductor. The total thickness of metal ground plane 13 is shown to be approximately 800 angstroms, however other thicknesses may be readily used.

FIG. 3 illustrates device structure 10 of FIG. 2 with a second polymer 15 applied and patterned on the surface of substrate 11 to leave portions of metal ground plane 13 exposed. In a preferred embodiment, polymer 15 is also a positive photoresist layer. Photoresist layer 15 must have different solubility characteristics than photoresist layer 12. Suitable solvent or developer solutions used to remove photoresist layer 15 should not be able to remove any portion of photoresist layer 12. For example, one such photoresist layer 15 which has different solubility characteristics than photoresist layer 12 is a positive photoresist provided by the American Hoechst Corporation, called AZ4330. The thickness of photoresist layer 15 is determined by the desired thickness of metal layer 16 illustrated in FIG. 4. For purposes of exemplification, the thickness of photoresist layer 15 is shown to be approximately 3 microns.

FIG. 4 illustrates device structure 10 of FIG. 3 having a metal layer 16 formed on the exposed surface of metal ground plane 13. Metal layer 16 is preferably electroplated onto the exposed portion of metal ground plane 13. Metal layer 16 can be made of gold or another metal which is a good conductor. The thickness of metal layer 16 is determined by the application of semiconductor device 10. For lower frequency applications, a metal layer 16 having a thickness of approximately 3 microns is desirable.

FIG. 5 illustrates device structure 10 of FIG. 4 with photoresist layer 15 removed. Photoresist layer 15 is removed with a suitable developer or solvent. For example, a Microposit developer, supplied by the Shipley Company, can be used to remove photoresist layer 15 without affecting photoresist layer 12.

FIG. 6 illustrates device structure 10 with an exposed portion of metal ground plane 13 removed. Ground plane 13 is preferably removed with a wet etch. The gold layer in ground plane 13 can be removed with cyanide base acid called Technistrip, while the titanium may be removed in a hydrofluoric acid. In the present invention, the hydrofluoric acid nor the Technistrip are able to attack the surface of substrate 11 because photoresist layer 12 is fully intact. Other etchants may be also be used without affecting the surface of substrate 11.

FIG. 7 illustrates device structure 10 of FIG. 6 with photoresist layer 12 removed. Photoresist layer 12 can be removed by using a suitable developer or solvent. For example, acetone may be used to remove photoresist layer 12.

What is thus formed is a stable airbridge metal interconnect comprised of metal layers 13 and 16 which can be fabricated with high yield. The airbridge interconnect is shown to make contact to the surface of substrate 11 in two places, with the space between the contacts being air instead of a typical dielectric layer such as nitride or oxide. The length of the airbridge metal interconnect is typically approximately 150 microns in length. This allows for obtaining low parasitic capacitances, thereby increasing performance of the semiconductor device.

By now it should be appreciated that there has been provided a new and improved method of fabricating airbridge metal interconnects which provides for stable metal interconnects and a high yield in fabricating integrated circuits used in high frequency applications.