Dual Port Memory Circuit

The present invention relates to a memory circuit and more particularly to a dual port memory circuit.

Random access memories (RAMs) utilizing the LSI technique have been used mainly as the main memories of computers and have come into widespread use in office automation devices, such as personal computers. Due to the remarkable reduction in the cost per bit of storage, MOS random access memories are used for processing video images, especially for displaying images on a CRT. A memory device used with such a display is connected between a CPU and the CRT. However, conventional RAMs are inefficient for display applications. During the display period, the data is sent to the CRT continuously at a high speed data rate such as 45 ns. During this period, the RAM cannot exchange data with the CPU so that the CPU can neither rewrite nor read the content of the RAM. The data exchange between the RAM and the CPU is limited to the blanking period during which no image is displayed on the CRT. As a result, the CPU and the system efficiency is remarkably low.

It has been proposed that RAMs having an input/output system for a CPU and an output system for a CRT are the best suitable for display use. Such RAMs are called "dual port memory".

A known dual port memory is structured such that a serial access port is provided to the known RAM and a serial read operation to the CRT is performed via the serial access port while performing the usual random access operation by the commonly provided random input/output port. The serial access port includes a data register circuit for holding a plurality of data bits, a data transfer circuit for operatively applying a plurality of data bits stored in the selected row of the memory array to the data register circuit, and a serial selection circuit for serially selecting the data bits stored in the data register circuit.

However, the data transfer from the memory array to the data register circuit through the data transfer circuit must be performed in synchronism with the operation of the random access port. Furthermore, such data transfer necessitates a certain time period, and therefore serial access operations over the plurality of rows selected in sequence cannot be achieved at a high speed.

It is an object of the present invention to provide dual port memory which has a great flexibility in operating its random access port and serial access port.

It is another object of the present invention to provide a dual port memory operable at a high speed in the serial access mode.

The dual port memory circuit according to the present invention is of the type with a memory cell array having memory cells arranged in rows and columns, a random access peripheral circuit for performing random access operations with respect to the memory cell array in response to row and column address information, and a serial access peripheral circuit for serially accessing the columns of the array in response to shift clocks. The above serial access peripheral circuit includes a first transfer circuit provided for a first half of the columns, a second transfer circuit provided for the second, remaining half of the columns, a first data register having a plurality of storage bits coupled to the first transfer circuit, a second data register having a plurality of storage bits coupled to the second transfer circuit, a serial selection circuit for selectively extracting data stored in the first and second data register, and a control circuit for allowing the first transfer circuit to be enabled thereby to transfer data on the first half of digit lines when the serial selection circuit selects the second data register and allowing the second transfer circuit to be enabled thereby to transfer data on the second half of digit lines when the serial selection circuit selects the first data register.

According to the present invention, the two transfer circuits and the two data registers are provided as that simultaneous operation of one of the data transfer circuits and access to one of the data registers can be performed. Therefore, data transfer between the half digit lines to one register circuit can be conducted while the data register coupled to the other transfer circuit is serially accessed.

Thus, limitations in controlling the data transfer and the serial access can be decreased, and a high speed operation can be established.

FIG. 1 is a schematic block diagram of a prior art memory circuit;

FIG. 2 is a timing diagram showing the operation of the memory of FIG. 1;

FIG. 3 is a schematic block diagram of the memory according to one embodiment of the invention;

FIG. 4 is a schematic circuit diagram of the control circuit;

FIG. 5 is a timing diagram of the operation of the memory of FIG. 3; and

FIG. 6 is a diagram illustrating operational states of the memory of FIG. 3.

Referring to FIG. 1, a dual port memory according to the prior art is explained.

The memory comprises a memory cell array 10 having a plurality of memory cells MC, word lines arranged in M rows and digit lines such as DL.sub.i, DL.sub.j arranged in N columns, a row address buffer 12, a row decoder 14 for selecting one of the word lines, a column address buffer 11, a column decoder 13 for selecting the column or columns from which read data are extracted, a random I/O circuit 21, and a timing generator 20 for generating timing signals. The above elements are essential to the known random access memory. The dual port memory is featured by a serial access port SAP. The serial access port SAP includes a data register 17 having a plurality of storage bits Q.sub.1 . . . Q.sub.n of the number N, a data transfer circuit 16 for operatively transferring data between the digit lines and the data register 17 in parallel in response to a data transfer signal DT, a serial selection circuit 18 for selectively performing selective data transfer between a serial bus line SB and the data register 17, a serial address counter 15 for controlling the serial section circuit 18 and a serial input/output (I/O) circuit 19 coupled to a serial input/output terminal SI/O.

Referring to FIG. 2, operation of the memory of FIG. 1 is explained.

A row address strobe signal RAS is changed from a high, inactive level to a low, active level at time t.sub.1, then the timing generator 20 generates a timing signal RAS1 and thereafter a timing signal RAS2. Thus, the row address buffer 12 holds signals at address terminals A.sub.0 to A.sub.m as row address signals (R) in response to RAS1 and the row address decoder selects one of the word lines WL in accordance with the held row address signals in response to RAS2. Thus, data stored in the memory cells coupled to the selected word line are read out to the respective digit lines and amplified by sense amplifiers (not shown) in parallel.

While a column address strobe signal CAS is changed from a high, inactive level to a low, active level at time t.sub.2, the timing generator 20 generates timing signals CAS1, CAS2 and CAS3 in sequence.

Therefore, the column address buffer 11 incorporates signals at the terminals A.sub.0 to A.sub.m as column address signals (C) in response to CAS1, and the column selection circuit 13 selects one or more of the digit lines to be connected to a random access bus line RB. Thereafter, the I/O circuit 21 generates a valid data at the terminal I/O, at time t.sub.3. In parallel with the above read cycle, a serial cycle is continued in such manner that data stored in the respective data bits of the data register 17 are sequentially read out by the output of the address counter 15 which is incremented one by one in response to each input of the shift control signal SC, from an initial address determined by the column address signals held by the column address buffer 11 at a data transfer cycle which is described later.

Namely, the counter energizes selection outputs from the above initial address (Y.sub.k) towards the end address Y.sub.n via intermediate addresses, e.g. Y.sub.j, one by one in sequence in response to SC. Thus, data stored in the bit Q.sub.k in the data register 17 is first transferred to SB via a transfer gate Q.sub.sk (not shown) in the circuit 18, and data stored in the bits Q.sub.k+1 -Q.sub.n-2, Q.sub.n-1, Q.sub.n in the data register 17 are sequentially transferred to the bus line SB via the transfer gates Q.sub.sk+1 -Q.sub.sj -Q.sub.sn-2, Q.sub.sn-1, Q.sub.sn of the selection circuit 18 and outputted at the terminal SI/O as O.sub.k, O.sub.k+1, . . . O.sub.n-2, O.sub.n-1 and O.sub.n.

Explanation is now given to the data transfer cycle.

The data transfer control signal DT is raised to a high, active level at time t.sub.4 and the data transfer circuit 16 is enabled, and RAS is activated to the low, active level at time t.sub.5 so that the row address buffer 12 incorporates row address signals (R) and one word line is selected by the row decoder 14. In this cycle, DT is activated before the activation of RAS thereby to identify that the cycle should be the data transfer cycle. Data on the respective digit lines thus obtained are applied to the data register 17 in parallel via the enabled transfer circuit 16. CAS is activated to the low active level and the column address buffer 11 incorporates column address signals (SC) for determining the initial column address to be selected first in the serial access port SAP. Thus, the state of the address counter 15 is determined.

The signal DT is disenabled at time t.sub.7 in synchronism with the rise of SC to terminate the data transfer cycle and a serial access operation is immediately started from the column address Y.sub.i towards the end address Y.sub.n one by one in synchronism with SC so that data N.sub.i, N.sub.i+1 . . . are sequentially produced at the terminal SI/O. However, according to this memory, there is a limitation in applying the signal DT to the memory with respect to RAS and SC. Namely, DT must be enabled before RAS and the falling edge of DT must be in synchronism with SC. Thus, flexibility in control is very small.

Furthermore, the data transfer cycle performed between t.sub.4 to t.sub.7 requires a relatively long time and during the data transfer cycle, the serial access operation must be interrupted (invalidated), resulting in a low effective data rate.

Referring to FIGS. 3 to 6, the memory circuit according to one embodiment of the invention is explained.

The major structure of the embodiment is shown in FIG. 3, in which the same portions or elements as those in FIG. 1 are designated by the same reference numbers.

As shown in FIG. 3, the present embodiment is obtained by replacing the transfer circuit 16 of FIG. 1 with a lower transfer circuit 16L and an upper transfer circuit 16U, and the transfer circuits 16L and 16U are controlled by different control signals DTL and DTU, respectively which are generated by control circuit 22. The control circuit 22 receives the transfer control signal DT, a most significant column address signal ACO and a timing signal RAS3 which is generated by the timing generator 20' after generation of RAS2. In this embodiment, the number N of the columns is assumed to be 128 for the sake of simplicity, and 128 digit lines are classified into a lower group composed of 64 digit lines DL.sub.1 to DL.sub.64 and an upper group composed 64 digit lines DL.sub.65 to DL.sub.128. The lower group is designated by "0" of ACO (ACO=1) while the upper group is designated by "1" of ACO (ACO=0).

An address pointer 23 is provided between the column address buffer 11 and the counter and stores information relating to an initial column address in the serial access operation.

In the case where the serial access operation is always started from the digit line DL.sub.1, then the pointer 23 is not necessary.

The signal RAS3 is the signal which is generated approximately when data on the respective digit lines are amplified by sense amplifiers (not shown) in the known way.

The lower group of the digit lines DL.sub.1 to DL.sub.64 are connected to the lower transfer circuit 16L and the upper group of digit lines DL.sub.65 to DL.sub.128 are connected to the upper transfer circuit 16U. The data register is classified into a lower register 17L and an upper register 17U for the sake of explanation. The lower register 17L includes storage bits Q.sub.1 to Q.sub.64 coupled to the transfer gates QT.sub.1 to QT.sub.64 of the lower transfer circuit 16L respectively. Similarly, the upper register 17U includes storage bits Q.sub.65 to Q.sub.128 coupled to the transfer gates QT.sub.65 to QT.sub.128 of the upper register 16U, respectively. The selection circuit 18 includes transfer gates QS.sub.1 to QS.sub.128 coupled between the bus line SB and the storage bits Q.sub.1 to Q.sub.128, respectively. The transfer gates QS.sub.1 to QS.sub.128 are sequentially enabled one by one by the address counter 15 in response to SC.

When ACO is at logic "0" and a "1" of DTL is generated with DTU of "0", the lower transfer circuit 16L is enabled thereby to apply or write data on the lower half digit lines DL.sub.1 to DL.sub.64 to the lower register 17L. In this instance, the upper register 17U is allowed to be selected by the counter 15 and data stored in the upper register 17U can be serially read out to SI/O. While, when ACO is at logic "1" and the signal DTU is at logic "1" with DTL of "0", the upper transfer circuit 16U is enabled so that data on the upper half digit lines DL.sub.65 to DL.sub.128 are transferred to the upper register 17U. In this instance the lower register 17L is also allowed to be selected by the selection circuit 18 for serial reading.

Therefore, by reading the above operations alternately, one of the lower and upper registers 17L and 17U is subjected to access operations alternately and the remaining register is applied with data alternately. As a result, a continuous serial access operation can be achieved over a plurality of rows e.g. word lines.

One example of the control circuit 22 is shown in FIG. 4. The control circuit 22 includes a delay circuit 30, AND gates AG1 and AG2, and an inverter 31. The inverter 31 and the delay circuit 30 generate an inverted and delayed signal with respect to RAS3. Therefore, RAS3 and the output of the delay circuit 30 condition the gates AG1 and AG2 during a period corresponding to the delay time of the delay circuit 30. Therefore, either signal DTU or DTL has a pulse width of the above period.

Referring to FIGS. 5 and 6, operation of the circuit of FIG. 3 is explained. RAS is changed to the low, active level at t.sub.1 so that the row address of (Row i) is incorporated and one word line of (Row i) is selected. Then, CAS is activated at t.sub.2 and column address (C1) with ACO of "0" is incorporated so that DTL is activated with DTU non-activated. Thus, data on the lower half digit lines DL.sub.1 to DL.sub.64 are written to the lower register 17L via the lower transfer circuit 16L and the initial column address K designated by C1 is set in the pointer 23. This operation is illustrated in .circle.1 of FIG. 6. Then, CAS is deactivated at t.sub.3 and again activated at t.sub.4 and column address C2 with ACO "1" is taken in so that DTU is activated with DTL of "0". Therefore, data on the upper half digit lines DL.sub.65 to DL.sub.128 are transferred to the upper register 17U via the upper transfer circuit 16U. This is illustrated in .circle.2 in FIG. 6. Then, a serial read operation is initiated from time t.sub.5 from the address K by the counter 15 and the register bits Q.sub.k, Q.sub.k+1 . . . are sequentially output as O.sub.k, O.sub.k+1 . . . in synchronism with repetition of SC. This step is illustrated at .circle.3 and .circle.4 of FIG. 6. While the serial access is performed on the upper register 17U, RAS is activated at t.sub.6 and a new row address, e.g. (Row i+1) is incorporated thereby to select the word line of (Row i+1). CAS is also activated at t.sub.7 and the column address C3 with ACO "0" is taken so that data on the lower half digit lines derived from the row (Row i+1) are transferred to the lower register 17L via the enabled lower transfer circuit 16L and the initial column address (K) is set in the pointer 23. The selection circuit 18 selects the storage bits of the upper register 17U serially, in synchronism with SC towards Q.sub.128, as illustrated in 5 and 6 of FIG. 6. Then, when the end storage bit Q.sub.128 is accessed and the output O.sub.128 is generated at SI/O, the content of the pointer is set in the counter 15 and the counter selects the bit of Q.sub.k at t.sub.8 and thereafter Q.sub.k+1, . . . towards Q.sub.64 in synchronism with SC while CAS is again activated at t.sub. 9 and the column address with ACO of "1" is taken and the transfer circuit 16U transfers the data on the upper half digit line DL65 to DL128 to the upper register 17U in parallel with the serial reading of the lower register 17L, as illustrated .circle.6 of FIG. 6.

Thus, by repeating the above operations, data of the digit lines are continuously accessed over a plurality of rows.

As described above, according to the present invention, the data transfer cycle does not affect the serial access operation and it is not seen from outside the RAM. Therefore, there is no limitation in performing the data transfer cycle and a high data rate can be achieved.