Video Signal Processing Apparatus

1. Field of the Invention

The present invention relates to a video signal processing apparatus for processing a video signal to obtain a print image from the video signal.

2. Description of the Prior Art

FIG. 1 shows a block diagram of an example of an arrangement of a conventional video printer for processing a video image. An input video signal 1 is converted to a digital signal by an A/D converter 2 and is processed to become a printing signal by an image processing circuit 3 and is printed by a printer 4.

Next, the case where a print size is switched using this apparatus will be assured. FIG. 2 shows a situation wherein the number of sample points of the image data is doubled as compared with the original image and the print size is doubled (i.e., the area covered is increased four times) and an arrangement block diagram of a video printer suitable for use in this case is shown in FIG. 3. In FIG. 3, the similar (corresponding) components as those shown in FIG. 1 are designated by the same reference numerals. The input video signal 1 is converted to a digital signal by the A/D converter 2 and an interpolation of the data is performed by an interpolating circuit 10. The interpolated data is processed by the image processing circuit 3 to become the printing signal and is printed by the printer 4. The interpolating circuit 10 converts image data 5 and 6 in FIG. 2 to image data 7, 8 and 9, respectively. It is assumed that the image data 7 is the same as the image data 5 and the image data 9 is the identical to the image data 6, while the intermediate image data 8 is the data which is inserted between the image data 5 and 6. In the case of a linear interpolation, the image data 5 and 6 are added and the quotient of the sum was divided by two is used as the image data 8. The interpolation is performed in the foregoing arrangement and the print size of the image is changed over.

However, such an interpolation requires memories, adders and dividers since additions and divisions of at least two pixels are executed in both horizontal and vertical directions of the picture plane, so that there are the drawbacks that the hardware becomes complicated and expensive and that the timings for data processes also become complicated.

It is an object of the present invention to eliminate the above-mentioned drawbacks of the conventional technology.

It is another object of the invention to provide a video signal processing apparatus which enables the sampling number to be changed with a simple arrangement.

Still another object of the invention is to provide a video signal recording apparatus which can change a print size with a simple arrangement. According to the present invention, these objects are attained by providing a video signal processing apparatus having an oscillator or the like with a variable-frequency output, circuitry for sampling a video signal by means of the oscillating signal, and means for instructing a change in the number of samples taken per frame. The oscillator changes its output frequency in accordance with the instruction. This may be done, for example, by means of a delay line. The sampling interval may be changed in either a horizontal scanning direction, or a direction perpendicular thereto, at the least. The size of a recorded image may be changed in association with the change in number of samples.

Other objects and features of the present invention will be apparent from the following detailed description of the preferred embodiments taken in conjunction with the accompanying drawings.

FIG. 1 is a block diagram of an example of an arrangement of a conventional video printer;

FIG. 2 is an explanatory diagram of a case in which the number of sample points of an image data is doubled;

FIG. 3 is a block diagram of an arrangement of a video printer suitable for use in in such a case;

FIG. 4 is an arrangement block diagram of one embodiment of a video printer of the invention;

FIG. 5 is a circuit arrangement diagram of a timing generator;

FIGS. 6 to 9 are timing charts for each of the illustrated signals, respectively;

FIG. 10 is an example of another circuit arrangement of the timing generator; and

FIGS. 11 and 12 are timing charts for each of the illustrated signals for the FIG. 10 arrangement, respectively;

The present invention will now be described hereinbelow with reference to the drawings. FIG. 4 is a block diagram showing an arrangement of one preferred embodiment of the invention, in which the components similar (corresponding) to those shown in FIGS. 1 and 3 are designated by the same reference numerals. The input video signal 1 is converted to the digital signal by the A/D converter 2 and is inputted to a vertical interpolator 11. In the vertical interpolator 11, the presence or absence of vertical interpolation is selected by means of control of a size switching signal 13. The vertical interpolator 11 operates in a manner such that it does not perform interpolation when the print size is small but does interpolate when the print size is large. An output of the vertical interpolator 11 is processed by the image processing circuit 3 to become a printing signal and is printed by the printer 4.

The size switching signal 13 controls a timing generator 12 in a manner such that the sampling number in the horizontal direction decreases in the case of a small print size and increases in the case of a large print size. A sampling timing of the image of the A/D converter 2 is controlled in response to an output of the timing generator 12.

As described above, in case of an ordinary print size, the sampling number in the horizontal direction of the image is few relatively small, and no vertical interpolation is performed. When the print size is large, the horizontal sampling number of the image increases in accordance with the print size and the vertical interpolation is also carried out. Thus, the print size can be switched by the print size switching signal 13.

FIG. 5 shows an example of a circuit arrangement of the timing generator 12. This diagram shows an embodiment suitable for use in the case where the sampling is performed in the horizontal direction, in which a reference numeral 14 denotes a vertical sync signal VD synchronized with the video signal; 18 is a start signal for the A/D conversion; 15 and 17 are D-FF (D type flip-flop) circuits, respectively; 16 and NAND circuit (gate); and 19 an AND gate. As shown in a timing chart for each signals in FIG. 6, the two vertical sync signal 14 (VD) are outputted from the AND gate 19 due to each of those circuits after the leading edge of the A/D conversion start signal 18. Due to this, one frame of a TV signal to perform the interlace is fetched from the A/D conversion signal synchronously with the vertical sync signal.

A numeral 20 is a horizontal sync signal HD synchronized with the video signal; 21 and 25 are AND gates, respectively; 22 a preset circuit to preset M preset values; 23 and 27 presettable down counters; 24 an inverter; and 26 a preset circuit to preset N preset values.

As shown in a timing chart for each signal in FIG. 7, the presettable counter 23 counts M horizontal sync signals HD and sets this count value to the number equal to the vertical blanking. The presettable counter 27 counts N horizontal sync signals HD and sets this count value as the sampling number of the image in the vertical direction. Therefore, with the arrangement of the respective circuits 21 to 27, N horizontal sync signals, as many as the number of samples of the image in the vertical direction, are obtained from the AND gate 25.

In addition, numerals 28 and 34 are inverters, 20 respectively; 29 a NAND circuit; 30 a tapped delay line DL; 31 an OR circuit; and 32 and 33 AND circuits. With this arrangement, as shown in a timing chart for each signal in FIG. 8, an oscillating output synchronized with an output signal of the inverter 28 is derived from the OR gate 31. Namely, a gated oscillator is constituted by the NAND gate 29 and delay line 30. The oscillating frequency is selected by selecting a tap output of the tapped delay line 30 by the size switching signal 13. Namely, in the case of an ordinary print size, the oscillating frequency is made low by selecting a tap T.sub.2. In the case of a large print size, the oscillating frequency is made high by selecting a tap T.sub.1.

Further, numerals 35 and 39 and AND circuits, respectively; 36 a preset circuit to set a preset value L; 37 and 41 presettable down counters, respectively; 38 an inverter; and 40 a preset circuit to set a preset value P. The presettable down counter 37 counts the preset value L. This means that the horizontal blanking time is set from the horizontal sync signal HD and the oscillating frequency varies in dependence upon the print size; therefore, by changing a value of the preset value L of the preset circuit 36, the horizontal blanking time is made constant. On the other hand, the presettable down counter 41 counts the preset value P, thereby setting the sampling number in the horizontal direction. A timing chart for each of those signals is shown in FIG. 9. Namely, by changing the preset value P in association with a change-over of the print size, the sampling number in the horizontal direction is determined.

As described above, when the A/D conversion start signal 18 is inputted, a control signal pulse 42 for sampling the input video signal 1 in the 9 horizontal direction can be generated for the interval excluding the vertical and horizontal blanking intervals during one frame synchronized with the vertical sync signal VD after the input of the start signal 18. Also, by use of the print size switching signal 13, the horizontal sampling number can be changed and the same horizontal video signal can be sampled.

On the other hand, to increase the print size X times, the oscillating frequency may be increased X times and the present values L and P of the counters 37 and 41 in the horizontal direction may be increased X times. (Another Embodiment)

FIG. 10 shows an embodiment of another circuit arrangement of the timing generator 12, in which the components similar (corresponding) to those shown in FIG. 5 are designated by the same reference numerals and their descriptions are omitted.

This embodiment shows the case where the video signal is vertically sampled, in which a numeral 43 denotes an AND circuit; 44 is a preset circuit to set a preset value 2R; and 45 is a presettable down counter.

In the respective circuits 43 to 45, as shown in a timing chart for each signal in FIG. 11, the preset value 2R is counted by the presettable down counter 45 and 2R vertical sync signals are derived from the AND gate 43. The meaning of the number 2R of this preset value represents that assuming that the sampling number in the horizontal direction is R, two fields have to be sampled in order to sample one frame of the television signal and the data for one vertical line can be sampled for two vertical intervals. Therefore, the vertical interval which is twice the interval in the case of R is needed to sample R points in the horizontal direction. A change in print size denotes a change of sample points in the horizontal direction, so that such a change can be performed by changing the preset value 44.

Next, in the circuit arrangement from the AND gate 21 to the presettable counter 27, the vertical sampling is determined similarly to the case of the horizontal sampling in FIG. 5.

In addition, the circuit arrangement from the inverter 28 to the OR circuit 31 also constitutes an oscillator synchronized with the phase of the horizontal sync signal similarly to the case of the horizontal sampling in FIG. 5. A numeral 46 denotes a preset circuit to set a preset value 2Q; 47 is a presettable up counter; and 48 is a presettable down counter. The presettable up counter 47 counts the vertical sync signal and its output is used as a preset value of the presettable down counter 48.

The presettable down counter 48 counts down an oscillating output of an output of the OR gate 31 from the preset value and when the count value becomes 0, the down counter 48 outputs a sampling pulse 42'. As described above, the data for one line can be sampled due to two fields with respect to the vertical sampling; therefore, 1/2 of an output of the presettable up counter 47, namely, a value of which the LBS (least significant bit) was eliminated is used as a preset value of the presettable down counter 48. Also, the preset circuit 46 of the presettable up counter 47 sets the preset value of 2Q, which is twice the number Q. A timing chart for each of those signals is shown in FIG. 12.

Assuming that the number of vertical sync signals after the A/D start signal 18 was inputted is S, the sampling pulse 42' is generated when (Q+S/2) oscillating outputs of the output of the OR gate 31 are counted after the horizontal sync signal from the AND gate 25 has been inputted, in which the number S has a value within a range of Q.ltoreq.S<R.

As described above, the vertical sampling can be likewise performed by changing the horizontal sampling number by means of control of the print size.

As described in the above with respect to each embodiment, according to the present invention, in an image processing apparatus for printing a video signal, in the case of switching a print size, the data in the vertical direction is increased by means of interpolation; however, the data in the horizontal direction is increased by increasing the number of sampling points. Therefore, memories, adders, dividers, etc., in association with the horizontal interpolation as in a conventional apparatus becomes unnecessary, so that the system arrangement can be simplified and an increase in cost of the hardware can be avoided.

On the other hand, in the case where the print size is switched, the start point of the horizontal samples and the sampling number can be preset; consequently, even if the print size is changed, the range of data where the video signal can be taken in can be made constant.

The present invention is not limited to the foregoing embodiments but many modifications and variations are possible within the spirit and scope of the invention as set out in the appended claims.