NMOS Source/Drain Doping With Both P and As

The present invention relates to a method for forming MOS transistors, and to transistors formed by this method.

A difficulty in the fabrication of small-geometry MOS devices is the following quandary: If the source/drains are doped to a level high enough to give reasonably low series resistance, the magnitude of the electric field in the channel adjacent to the drain during the on-state will be tremendous, and hot carriers and impact ionization effects will become a nuisance.

As the MOSFET channel becomes shorter, the electric field along the channel becomes more important. That is, the potential distribution becomes two dimensional, and the effect of the electric field along the channel can no longer be ignored while considering the effects of the electric field normal t o the channel. In particular, where the electric field along the channel is high, as it is likely to be in short-channel MOS devices, impact ionization is likely to occur near the drain. The resulting substrate current greatly increases the likelihood of latch-up. In addition, hot carriers are also likely to be generated by the strong electric field magnitude near the drain, and some of these carriers may be injected into the oxide, leading to threshold shift.

Thus, it is an object of the present invention to reduce the magnitude of electric field seen along the channel near the drain of an MOS device.

A difficulty in fabricating MOS devices with reasonably shallow source/drain diffusions is that the sharp curvature of the junction will cause a locally increased electric field, and therefore a reduced breakdown voltage. This causes great difficulty when high-voltage devices with reasonably small geometry are desired. If an arsenic implanted drain junction is to have a reasonable curvature, a very long drive-in time is required, causing undesired thermal effects in the other parts of the device.

Thus, it is a further object of the present invention to provide a method for forming source/drain regions having low series resistance and a large junction radius.

It is a further object of the present invention to provide a method for forming source/drain regions having a low contact resistance and a large junction radius.

It is a further object of the present invention to provide a process, satisfying the above-stated objects, which does not require additional masking or heating steps.

Both arsenic and phosphorus are implanted to form the drain of an N-channel transistor. Preferably the phosphorus is implanted in a dose no larger than the arsenic. Since the two implants are identically masked, the greater diffusivity of the phosphorus means that it will diffuse laterally in advance of the arsenic during annealling of the implant. Thus, the arsenic provides low contact resistance, while the phosphorus provides reasonably gentle junction curvature. Moreover, a region of graduated doping will exist at the boundary between the drain and channel, so that the potential distribution in this area is smoothed out, and the peak electric field magnitude is reduced. Thus, the effects caused by highly-accelerated carriers are reduced. Not only is impact ionization and hot carrier generation reduced, but other short-channel effects, such as loss of current saturation effects, variable threshold voltage, and degradation of subthreshold behavior, are reduced.

According to the present invention there is provided a method for forming MIS source/drain regions, comprising the steps of:

providing a semiconductor substrate;

masking said substrate except where said source/drain regions are to be implanted;

implanting dopant atoms of first and second species in said respective source/drain regions, both said dopant species having the same conductivity type in said substrate, and said first species having a higher diffusivity than said second species; and

annealing said implanted dopants;

whereby said implanted first species diffuses beyond said implanted second species during said annealing step.

The present invention will be described with reference to the accompanying drawings, wherein:

FIG. 1 shows ion implantation of the source/drain regions in an N-channel device, during CMOS processing;

FIG. 2 shows schematically the dopant distribution in an NMOS drain region, after annealling of a double implant; and

FIG. 3 shows approximately the electric potential distribution along the channel of an NMOS device with double-implanted source/drains according to the present invention.

The present invention applies to the formation of source/drain regions in MIS devices. It is of particular importance in optimizing the characteristics of the drain region. The presently preferred embodiment is in the fabrication of NMOS devices within a CMOS structure.

FIG. 1 shows implantation of N-type source/drains within CMOS processing. In the present invention, both phosphorus and arsenic are implanted at this step. Moreover, the implant energies are preferably selected so that the depth profiles of concentration as implanted are approximately the same for the two impurities. Thus, for example, implant energies of 120 keV for arsenic and 50 keV for phosphorus 31 would give similar as-implanted profiles for the two impurities. After annealling, the implanted phosphorus will have diffused slightly in advance of the implanted arsenic, so that, behind the drain/channel junction, a gradation in conductivity will exist, as shown in FIG. 2.

The effect of this is shown in FIG. 3. The solid line at FIG. 3 schematically shows sample on-state electric potential profiles along the channel, where source/drain regions have been formed according to the present invention. The dashed line of FIG. 3 schematically shows the potential distribution which would exist under the same conditions of gate, source, and drain voltage, where the device geometry is the same except that the sources and drains are of uniform conductivity. As may easily be seen from this figure, the effect of the present invention is to greatly reduce the gradient of the electric potential near the drain, and therefore to greatly reduce the peak electric field.

It will be obvious to those skilled in the art that the present invention may be applied in a wide variety of processes and contexts. In particular, it is applicable to formation of N-channel devices in either CMOS or NMOS technology.

Moreover, the present invention can also be applied to other combinations of dopants. The key requirement is that two dopants of the same type, having different diffusivities, be used; for example, boron and gallium can be used to form P-channel devices, as can boron and indium.

A sample application of the present invention implants 1.times.10.sup.16 .sub.cm.sup. -2 of arsenic at 120 keV, and 2.times.10.sup.15 cm.sup.-2 of phosphorus at 50 keV, into the regions exposed by the N-type source/drain mask, during CMOS processing. A single annealing step follows. Further background on integrated circuit processing is found in, e.g., A. Glaser & G. Subak-Sharpe, Integrated Circuit Engineering, which is hereby incorporated by reference.

The anneal is performed with parameters well known in the art. For example: 50 nm of plasma-assisted CVD oxide is first deposited. The oxide is densified at 700.degree. C., with 10 minutes in 0.sub.2, 30 minutes in steam, and 10 minutes in argon. The temperature is then raised to 1000.degree. C. in Ar, and held at 1000.degree. C. for 20 minutes. The temperature is then lowered to 800.degree. C. , and held there for 30 minutes, still in argon. Next 650 nm of phospho-silicate glass (PSG) is deposited, and the PSG is reflowed at 975.degree. C., with 14 minutes in 0.sub.2 + N.sub.2, 2 minutes in 0.sub.2 + N.sub.2 with POC1.sub.3 doping, and 3 minutes in 0.sub.2 + N.sub.2 again. These annealing times represent only one choice within a broad range of parameters, and longer times at lower temperatures, or higher temperatures at lower times, may also be used. In addition, the annealing time at a given temperature may also be increased (or decreased), in which case the diffusion length of the phosphorus implant beyond the arsenic implant will also increase (or decrease). The oxide and PSG deposition steps are detailed here because the high-temperature PSG reflow further contributes to annealing the source/drain implants. However, the implant annealing (drive-in) is affected only by time and temperature, and not by the surface depositions. This annealing process results in about a 0.3 micron band at the edge of the source/drain region where the phosphorus has diffused beyond the arsenic. Thus, a source/drain formed by the inventive double-implant process has (1) a central core having a high concentration of both arsenic and phosphorus, surrounded by (2) a peripheral band, within the junction at the sides of the source/drain region, where the total dopant concentration is much lower, and is largely composed of phosphorus.

The maximum thickness of the peripheral band is determined merely by the desired size of the source/drain junction boundary. (Excessive drive-in time will shorten channel length, may infringe the lateral spacings which avert latch-up, or may conduce to punch-through in the P-well technology.) There is no specific minimum thickness for the peripheral band, but the advantages of the invention are less well obtained with shorter drive-in time. However, the thickness of the peripheral band is preferably at least one-tenth of the source/drain junction depth.