Image Processing Method and Apparatus Therefor

1. Field of the Invention

The present invention relates to an image processing method for rotation or size change of an image and an apparatus therefor.

2. Related Background Art

In a conventional apparatus for rotation, enlargement or reduction of a digital image, such process has been conducted after input image data are once stored in a memory. The amount of information of the input image is generally larger than the corresponding amount processed image data, so that storage of the former requires a larger memory than the storage of the latter. Consequently the method of storing the input image information in a memory is inferior, in terms of memory cost and magnitude of circuitry, to a method of processing the input data in synchronization with a synchronization signal and storing the processed data in succession in an output memory.

On the other hand, the method of processing the input image data in consecutive manner for image rotation, enlargement or reduction in synchronization with a synchronization signal has a drawback of image quality deterioration because the processed data are sometimes not synchronized with the desired pitch of output signals, resulting in missing image data or in a misalignment of the image. FIGS. 1A and 1B illustrate such an example, wherein FIG. 1A shows the pitch of an original image, while, in FIG. 1B, broken lines indicate the pitch of an output image and solid lines indicate the pitch of an image obtained by a rotation of 35.degree. of the original image. Each rectangle corresponds to a pixel, and the value of each pixel of the rotated image is given to an output pixel, or broken-lined rectangle, in which the center of said rotated image pixel is positioned. In such image processing, the hatched output pixels become missing pixels, i.e., pixels to which no corresponding image data is assigned. FIG. 1C shows similar missing pixels in an image processing of a rotation of 38.degree. combined with image size variations of 80% in the main scanning direction and 120% in the sub scanning direction.

Also in such conventional apparatus, for example in the case of an image rotation of 30.degree. as shown in FIG. 1D, the outputting of the processed result image is started from a pixel on a line 215 in the sub-scanning direction of the original image, and the addresses of pixels 212, 213 for starting the outputting of processed image are obtained by complicated calculations. Such method, when applied to an apparatus requiring a high image quality such as in a color image processing or a high speed, requires a long time, or requires a large amount of hardware for achieving such process, or eventually results in a deteriorated image quality.

An object of the present invention is to provide an image processing method and an apparatus therefor, not associated with such drawbacks as mentioned above.

Another object of the present invention is to provide an image processing method and an apparatus therefor, capable of image rotation or image size variation on scanned input image data (source data) in successive manner in synchronization with a scanning synchronization signal.

Still another object of the present invention is to provide an image processing method and an apparatus therefor, capable, in image rotation or image size variation on input image data in successive manner, of providing an output image without missing pixels or misalignment in pixels.

Still another object of the present invention is to provide an image processing method and an apparatus therefor, capable of image rotation of an arbitrary angle.

Still another object of the present invention is to provide an image processing method and an apparatus therefor, capable of preventing image quality deterioration in image rotation or image size variation.

The foregoing and still other objects and features and advantages of the present invention will become fully apparent from the following description of the preferred embodiments to be taken in conjunction with the attached drawings.

FIGS. 1A, 1B, 1C and 1D are schematic views showing drawbacks in the prior art;

FIG. 2 is a schematic diagram of a first embodiment of the present invention;

FIG. 3A is a block diagram of the front half of said embodiment;

FIG. 3B is a block diagram of the rear half of said embodiment;

FIG. 4 is a more detailed block diagram of a circuit for calculating coordinates after rotation shown in FIG. 3A;

FIGS. 5A and 5B are more detailed block diagrams of an in-area lattice point detection circuit shown in FIG. 3A;

FIG. 5C is a wave form chart showing a main-scan synchronization signal and a main-scan operation synchronization signal;

FIG. 5D is a wave form chart showing the main-scan operation synchronization signal and a sub-scan operation synchronization signal;

FIG. 6 is a more detailed block diagram of a coordinate inverse conversion circuit shown in FIG. 3B;

FIG. 7 is a more detailed block diagram of an interpolation circuit shown in FIG. 3C;

FIG. 8 is a schematic view of image scanning state;

FIG. 9 is a wave form chart showing a page synchronization signal and a sub-scan synchronization signal;

FIG. 10 is a wave form chart showing a sub-scan synchronization signal and a main-scan synchronization signal;

FIG. 11A is a schematic view of a raster memory;

FIGS. 11B and 11C are schematic views showing the relationship of the raster memory of FIG. 11A and scanned data;

FIG. 12 is a view showing the mode of interpolation;

FIGS. 13A, 13B and 13C are views showing a method of obtaining interpolated output image data from scanned input image data subjected to image rotation and image size variation;

FIG. 14 is a block diagram showing a variation of the circuit shown in FIG. 5A;

FIGS. 15A and 15B are block diagrams showing a variation of the first embodiment;

FIG. 16 is a block diagram of a circuit 22' for calculating coordinates after rotation, shown in FIG. 15A;

FIG. 17 is a detailed block diagram of a lattice point calculating circuit 24' shown in FIG. 15A;

FIG. 18 is a detailed block diagram of a coordinate inverse conversion circuit 28' shown in FIG. 15B;

FIGS. 19A, 19B and 19C are schematic views showing the relationship between the raster memory and scanned data;

FIGS. 20A and 20B are schematic views showing the mode of interpolation;

FIGS. 21A, 21B and 21C are schematic views showing a method of obtaining interpolated output image data from scanned input image data subjected to image rotation;

FIGS. 22A and 22B are block diagrams of a second variation of the first embodiment;

FIG. 23 is a detailed block diagram of a coordinate calculating circuit 22" shown in FIG. 22A;

FIGS. 24A and 24B are detailed block diagrams of a lattice point calculating circuit 24" shown in FIG. 22A;

FIG. 25 is a detailed block diagram of a coordinate conversion circuit 28" shown in FIG. 22B;

FIGS. 26A, 26B and 26C are schematic views showing a method of obtaining interpolated output image data from scanned input image data subjected to image rotation or image size variation according to said second variation;

FIG. 27 is a block diagram of a variation of the circuit shown in FIG. 24A;

FIGS. 28A, 28B and 28C are schematic views showing comparison of density in output lattice points in the prior art and in this embodiment;

FIG. 29 is a block diagram of a front half of an address generating circuit of this embodiment;

FIG. 30 is a timing chart showing signals in the circuit shown in FIG. 29;

FIG. 31 is a block diagram of a rear half of the address generating circuit;

FIG. 32 is a timing chart showing signals in the circuit shown in FIG. 31;

FIG. 33 is a schematic chart showing the method of weighted averaging;

FIG. 34 is a schematic block diagram of an image processing apparatus;

FIG. 35 is a schematic chart showing the method of weighted averaging in such apparatus;

FIG. 36 is a chart of an approximated linear trajectory obtained by the circuit shown in FIG. 29;

FIG. 37 is a schematic block diagram of an example of a conversion circuit of FIG. 35;

FIGS. 38A and 38B are a schematic view and a chart for explaining coordinate conversion;

FIG. 39 is a block diagram of a second embodiment of the present invention, for determining the addresses of start pixels;

FIG. 40 is an enlarged view of the trajectory of start pixels;

FIG. 41 is a schematic view showing the method of start address determination;

FIG. 42 is a block diagram of a circuit for determining a line in the main scan direction of the processed image;

FIG. 43 is a schematic view showing the method of determining the address of start pixels;

FIG. 44 is a view showing the trajectory of start pixels obtained according to the method of FIG. 43;

FIG. 45 is a block diagram of the entire apparatus;

FIG. 46 shows scanning directions of an image;

FIG. 47 is a schematic view showing the relationship of input and output data in image enlargement or reduction;

FIG. 48 is a circuit diagram for preparing interpolation data;

FIG. 49 is a more detailed view of the circuit shown in FIG. 48;

FIGS. 50 and 51 are further detailed views of the circuit shown in FIG. 49;

FIGS. 52 and 53 are a circuit diagram and a timing chart for interpolation ratio generation;

FIG. 54 is a circuit diagram for address calculation in a fine reduction circuit;

FIG. 55 is a schematic view showing the relation of input and output data of the fine reduction circuit;

FIG. 56 is a schematic view showing the interpolation in the fine reduction circuit; and

FIG. 57 is a block diagram of an address calculating circuit for inverse conversion in the fine reduction circuit.

FIG. 2 and the ensuing drawings illustrate a first embodiment of the present invention, wherein FIG. 2 is a basic block diagram of said embodiment while FIG. 3A is a block diagram of a front half thereof and FIG. 3B is a block diagram of a rear half thereof. FIG. 4 is a detailed block diagram of a circuit for coordinate detection after image rotation or image size variation shown in FIG. 3A, FIG. 5A is a detailed block diagram of an in-area lattice point detection circuit after rotation or size variation shown in FIG. 3B, FIG. 6 is a detailed block diagram of a coordinate inverse conversion circuit shown in FIG. 3B, FIG. 7 is a detailed block diagram of an interpolation circuit shown in FIG. 3B, FIG. 8 is a schematic view of image scanning state, FIG. 9 shows a relation between a page synchronization signal and a sub-scan synchronization signal, FIG. 10 shows a relation between sub-scan synchronization signal and a main-scan synchronization signal, FIG. 11 shows the structure of a raster memory and its relation to scanned data, FIG. 12 shows the mode of interpolation, and FIG. 13 shows a method of obtaining interpolated output image data from scanned input image data after image rotation.

Let the main-scan direction and sub-scan direction of the original image be respectively called the x-axis and the y-axis. Coordinates 1, 2, 3, . . . in the x-direction correspond to the main-scan synchronization signal starting from a sub-scan synchronization signal, and coordinates 1, 2, 3, . . . in y-direction correspond to the sub-scan synchronization signal, starting from a page synchronization signal. Thus a coordinate (x0, y0) corresponds to an x0-th dot in a y0-th raster in the original image (cf. FIGS. 7, 9 and 10).

When a point (x,y) in an orthogonal coordinate system is moved to a point (x', y') by a rotation of an angle .theta. about a point (x.sub.c, y.sub.c), there obtain the following relationship: ##EQU1##

Also when a point (x', y') is moved to a point (x", y") by an independent image size variation of .alpha. and .beta. times, respectively, in the main-scanning and sub-scanning directions about a center of size variation (x.sub.z, y.sub.z), there obtain the relationships: ##EQU2##

Thus, in the case where a point (x, y) is brought to (x", y") by a rotation of an angle .theta. about a point (x.sub.c, y.sub.c) followed by an independent size variation of .alpha. and .beta. times, respectively, in the main-scanning and sub-scanning directions about a center of size variation (x.sub.z, y.sub.z), there is obtained an equation: ##EQU3## This equation can be transformed into: ##EQU4##

FIG. 11B shows a scanned input image while FIG. 11C shows an image after rotation and independent image size variation, wherein x indicates the center of rotation and of image size variation.

As .alpha. and .beta. in equation (3) are generally rational numbers but cos .theta. and sin .theta. are generally irrational numbers, x" and y" are generally irrational numbers even when x, y, x.sub.c, y.sub.c, x.sub.z and y.sub.z are natural numbers. Thus the dots of the image after rotation and independent image size variation are displaced from the dots defined by the input-output synchronization signal.

The value of each pixel in the image after rotation and independent image size variation is determined by the data of three consecutive rasters. There is assumed a rectangle of which the center (hereinafter, "center" is used in the sense of "geometric center") is positioned at the center of a contemplated pixel on the second (central) raster and of which the length is defined by .alpha.(.vertline.sin .theta..vertline.+.vertline.cos .theta..vertline.) in the main scanning direction and by .beta.(.vertline.sin .theta..vertline.+.vertline.cos .theta..vertline.) in the sub-scanning direction, and there is detected an output pixel having its center in said rectangle. In FIG. 13A, circles A and B indicate the detected pixels, and the value of each pixel is determined by the four data of rotated rasters surrounding said pixel. FIG. 13B shows the pixel A of which the value is determined by the values of four surrounding pixels a, b, c and d according to a method shown in FIG. 13C. It is assumed that a line segment bd, connecting the centers of pixels b and d, is divided with an interior division ratio of .delta.:1-.delta. by a line passing through the center of pixel A and parallel to a line segment cd connecting the centers of pixels c and d. Likewise it is assumed that said line segment cd is divided with an interior division ratio of .epsilon.:1-.epsilon. by a line passing through the center of pixel A and parallel to the line segment bd. The value V(A) of the output pixel A is determined by the values V(a), V(b), V(c) and V(d) of the pixels a, b, c and d according to the following equation:

The value V(B) for the pixel B can also be determined in a similar way.

In the following there will be explained the function of the above-explained embodiment.

In response to an instruction for image rotation given by an operator, an operation indication unit 2 shown in FIG. 2 sets information corresponding to the instructed angle of rotation in a process circuit 10. Also, in response to an instruction for image enlargement or reduction, the process circuit 10 is given information corresponding to the proportions of image size variation in the main-scanning and sub-scanning directions.

Then in response to a start instruction from the operator, the operation unit 2 activates a synchronization control unit 6 which executes the required operation by giving synchronization signals to a scan data source 4 and the process circuit 10. The image data are scanned as shown in FIG. 8. The start of image in a page is defined by the down shift of a page synchronization signal, while the start of each scan line in a page is defined by the down shift of a sub-scan synchronization signal, and the fetch timing of each pixel data is defined by the down shift of a main scan synchronization signal (cf. FIGS. 9 and 10).

Now reference is made to FIGS. 3A and 3B for explaining the operations of image rotation and independent image size variation executed by the process circuit 10 shown in FIG. 2. According to the rotation angle .theta. instructed by the operator, values of sin .theta., -sin .theta. and cos .theta. are set in a processed coordinate calculating circuit 22 and in a coordinate inverse conversion circuit 28, and values of .vertline.sin .theta..vertline. and .vertline.cos .theta..vertline. are set in an in-area lattice point detection circuit 24. Also, according to the center of rotation instructed by the operator, values of main-scan offset (rotation) and sub-scan offset (rotation) are set in the processed coordinate calculating circuit 22 and the coordinate inverse conversion circuit 28. Furthermore, according to the proportions of image size variation instructed by the operator, values .alpha., .beta. of proportions of image size variations in the main-scanning and sub-scanning directions are set in the processed coordinate calculating circuit 22 and the in-area lattice point detection circuit 24, and the corresponding reciprocals 1/.alpha., 1/.beta. are set in the coordinate inverse conversion circuit 28. Also, according to the center of image size variation instructed by the operator, values of main-scan offset (image size variation) and sub-scan offset (image size variation) are set in the processed coordinate calculating circuit 22 and the coordinate inverse conversion circuit 28.

In response to the synchronization signal released by the synchronization control unit 6, the scan data source supplies image data in the form of scan data to a raster memory 8 of which the structure is shown in FIG. 11A. It is composed of four line memories 8-1-8-4 corresponding to four scan lines, of which one is used for receiving image data from the scan data source 4 while the other three are used, with already received data, for effecting the processes of rotation, image size variation and interpolation. During the input of scan data for scan line, data are released from one of the scan lines already received.

As shown in FIG. 3, for the scan data already entered, the processed coordinate calculating circuit 22 calculates the coordinates obtained by image rotation and/or image enlargement or reduction of the input coordinates. The in-area lattice point detection circuit 24 detects the lattice points of the output image, present in a rectangle having the its center at the processed coordinate and having lengths .alpha.(.vertline.sin .theta..vertline.+ .vertline.cos .theta..vertline.) in the main scanning direction and .beta.(.vertline.sin .theta..vertline.+.vertline.cos .theta..vertline.) in the sub-scanning direction. Based on the thus detected lattice point, the coordinate inverse conversion circuit 28 successively determines the coordinates of said lattice points in a coordinate system after said system itself is subjected to rotation and independent size variation. From said coordinates there are determined input pixels to be employed in the interpolation and the coefficients to be employed in the interpolation, respectively, from the integer part and the fractional part of said coordinates. In this manner the value corresponding to the output lattice point is determined and released.

Now reference is made to FIG. 4 for explaining the processed coordinate calculating circuit 22, for effecting the calculation of the aforementioned equation (1). The circuit functions in response to read-out synchronization signals 4-a, 4-b and 4-c employed in the scan data source 4. In response to the page synchronization signal 4-c, a sub-scan counter 41 is reset and loaded with an initial value "-2", in order that the circuit starts to function with a delay of two scan lines from the scan data source 4. Also, in response to the sub-scan synchronization signal 4-a, a main scan counter 42 is reset and loaded with an initial value "0". The values x, y in said equation (1) are respectively given by the outputs of the main-scan counter 42 and the sub-scan counter 41, and values x.sub.c, y.sub.c are respectively given by the main-scan offset (rotation) 43 and sub-scan offset (rotation) 44 defining the coordinate of the center of rotation. Also, according to the rotation angle .theta., values of sin .theta., cos .theta. and -sin .theta. are set as constants. By addition, subtraction and multiplication of these data there are obtained the coordinates (x', y') after rotation, in fractional numbers. Then the main-scan offset (size variation) x.sub.z and sub-scan off (size variation) y.sub.z are subtracted respectively from x and y, and the obtained results are respectively multiplied by the proportions .alpha., .beta. of size varration in main-scanning and sub-scanning directions, and added with x.sub.z, y.sub.z to obtain the coordinate x", y" after image rotation and image size variation.

Now the in-area lattice point detection circuit 24 will be explained, with reference to FIG. 5A. This circuit defines a rectangle having its center at the coordinates after processing, and having lateral lengths of .alpha.(.vertline.cos .theta..vertline.+.vertline.sin .theta..vertline.) and .beta.(.vertline.cos .theta..vertline.+.vertline.sin .theta..vertline.) respectively, in the main-scanning and sub-scanning directions, and releases coordinates of lattice points, which are points having integral coordinates both in the main-scanning and sub-scanning directions, present in said rectangle. As the output of coordinate in the main scanning direction, it releases the integer part, after truncation of the fractional part, of a value obtained by adding .alpha.(.vertline.cos .theta..vertline.+.vertline.sin .theta..vertline.)/2 to x", and the integer part z, after truncation of fractional part, of a value obtained by subtracting .alpha.(.vertline.cos .theta..vertline.+.vertline.sin .theta..vertline.)/2 and adding 1 to x". As output of coordinate in the sub-scanning direction, it releases the integer part, after truncation of the fractional part, of a value obtained by adding .beta.(.vertline.cos .theta..vertline.+.vertline.sin .theta..vertline.)/2 to y", and the integer part, after truncation of the fractional part, of a value obtained by subtracting .beta.(.vertline.cos .theta..vertline.+.vertline.sin .theta..vertline.)/2 and adding 1 to y". These two sets of integers the are x-coordinates and y-coordinates of the desired lattice points, which are represented by A, B in FIG. 13A.

Coordinates of said lattice points in a coordinate system which is itself subjected to rotation and size variation are determined by a coordinate conversion circuit shown in FIG. 6, which effects an inverse conversion of the process executed by the processed coordinate calculating circuit 22 shown in FIG. 4, through independent size variation by 1/.alpha. and 1/.beta., respectively, in the main-scanning and sub-scanning directions and through rotation by -.theta..

The values of the integer part and integer+1 of thus inversely converted coordinates are used to determine four pixels (a, b, c and d in FIG. 13B) in the raster buffer, and the corresponding fractional parts are used to determine the interpolation coefficients (.alpha., .beta. in FIG. 13C). Thus an interpolation calculating circuit shown in FIG. 7 executes a calculation according to equation (2) to obtain correction values. The circuit shown in FIG. 7 effects interpolation for all the lattice points present in the aforementioned imaginary rectangle in the processed coordinate system, in response to a main-scan synchronization clock signal.

Based on the maximum and minimum coordinates in the main-scan direction (main-scan outputs 1 and 2) and maximum and minimum coordinates in the sub-scan direction (sub-scan outputs 1 and 2) of the lattice points present in said rectangular area, the circuit shown in FIG. 5B releases the main-scan and sub-scan coordinates of all the lattice points present in said area, in synchronization with a main-scan operation synchronization clock signal which is faster than the main-scan synchronization signal and with a sub-scan operation synchronization clock signal which is faster than said main-scan operation synchronization signal. In comparison with the main-scan synchronization signal, the main-scan operation synchronization signal is faster at least by a factor of (integer part of proportion of size variation.times..sqroot.2+1). In the present embodiment it is 4 times faster (cf. FIG. 5C). Also in comparison with the main-scan operation synchronization signal, the sub-scan operation synchronization signal is faster at least by a factor of (integer part of proportion of size variation.times..sqroot.2+1) (cf. FIG. 5D). In the present embodiment, wherein said proportion is 1.6 times, the latter should be faster by [1.6.times..sqroot.2]+1=3 times. One-shot down counters 101, 102 shown in FIG. 5B release high-level signals during a counting operation, and release low-level signals when the count reaches zero. There are further provided down counters 103, 104 in FIG. 5B. The interpolation process circuit shown in FIG. 7 executes the calculation of equation (2) by at first obtaining:

and

and then calculating ##EQU5##

The lattice point detection circuit 24 shown in FIG. 5A determines the lengths of the rectangle by the values .vertline.sin .theta..vertline. and .vertline.cos .theta. .vertline. determined according to the rotation angle .theta., but there may also be employed a constant K=.sqroot.2 of the rotation angle .theta., as shown in FIG. 14. In this case it is rendered possible to dispense with the setting of said values and therefore to reduce the magnitude of circuit. In this case the sides of the rectangle are .alpha..sqroot.2 and .beta..sqroot.2 respectively in the main-scanning and sub-scanning directions.

In the foregoing there has been explained an embodiment of an image rotation combined with an image size variation of .alpha. times and .beta. times, respectively, in the main-scanning and sub-scanning directions.

In the following there will be explained a variation in which the image is rotated in the same size.

Said variation is schematically shown in FIGS. 15A and 15B, wherein components of equivalent functions as those in FIGS. 3A and 3B are represented by the same numbers or symbols.

FIG. 16 is a detailed block diagram of a rotated coordinate calculating circuit 22' shown in FIG. 15A. FIG. 17 is a detailed block diagram of an in-area lattice point calculating circuit 24' shown in FIG. 15A, and FIG. 18 is a detailed block diagram of a coordinate inverse conversion circuit 28' shown in FIG. 15B. These circuits are simpler than those shown in FIGS. 4, 5A, 5B and 6, due to the absence of the size variation process. FIGS. 19A to 19C show the structure of a raster memory and its relation to the scan data, while FIGS. 20A and 20B show the mode of interpolation, and FIGS. 21A to 21C illustrate a method of obtaining interpolated output image data.

Let the main-scan direction and sub-scan direction of the original image be respectively called the x-axis and the y-axis. Coordinates 1, 2, 3, . . . in x-direction correspond to the main-scan synchronization signal starting from a sub-scan synchronization signal, and coordinates 1, 2, 3, . . . in the y-direction correspond to the sub-scan synchronization signal, starting from a page synchronization signal. Thus coordinates (x0, y0) corresponds to an x0-th dot in a y0-th raster in the original image (cf. FIGS. 7, 9 and 10).

When a point (x, y) in an orthogonal coordinate system is moved to a point (x', y') by a rotation of an angle .theta. about a point (x.sub.c, y.sub.c), there obtains the relationship: ##EQU6##

The relation between an input scan image and a rotated scan image is shown in FIGS. 19B and 19C, respectively indicating an original image and a rotated image, wherein a mark x indicates the center of rotation.

Since cos .theta. and sin .theta. in the equation (1) are generally irrational numbers, x' and y' are also irrational even if x, y, x.sub.c are natural numbers. Thus the dots of the image after rotation are displaced from the dots defined by the input-output synchronization signal.

The value of each pixel in the image after rotation is determined by the data of three consecutive rasters. There is assumed a square of which center is positioned at the center of a contemplated pixel on the second (central) raster and of which size is defined by .vertline.sin .theta..vertline.+.vertline.cos .theta..vertline., and there are detected output pixels having their centers in said square. In FIG. 21A, circles A, B, C and D indicate the detected pixels, and the value of each pixel is determined by the four data of rotated rasters surrounding said pixel. FIG. 21B shows the pixel A of which value is determined by the values of four surrounding pixels a, b, c and d according to a method shown in FIG. 21C. It is assumed that line segment ac, connecting the centers of pixels a and c, is divided with an interior division ratio of .epsilon.:1-.epsilon. by a perpendicular line passing through the center of pixel A. Likewise it is assumed that a line segment ab, connecting the centers of pixels a and b, is divided with an interior division ratio of .delta.:1-.delta. by a perpendicular line passing through the center of pixel A. The value V(A) of the pixel A is determined by the values V(a), V(b), V(c) and V(d) of the pixels a, b, c and d according to the following equation:

The values V(B), V(C), V(D) for the pixels B, C, D can also be determined in a similar way.

In the following there will be explained the function of the above-explained embodiment.

In a similar manner as in the first embodiment, in response to an instruction for image rotation given by an operator, an operation indication unit sets information corresponding to the instructed angle of rotation in a process circuit. Then, in response to a start instruction from the operator, the operation unit activates a synchronization control unit which executes required operation by giving synchronization signals to a scan data source and the process circuit (cf. FIG. 2).

The image data are scanned as shown in FIG. 8. The start of image in a page is defined by the down shift of a page synchronization signal, while the start of each scan line in a page is defined by the down shift of a sub-scan synchronization signal, and the fetch timing of each pixel data is defined by the down shift of a main scan synchronization signal (cf. FIGS. 9 and 10).

In the following there will be explained the operation of image rotation and interpolation. According to the rotation angle .theta. instructed by the operator, values of sin .theta., -sin .theta. and cos .theta. are set in a rotated coordinate calculating circuit 22' and in a coordinate inverse conversion circuit 28', and values of .vertline.sin .theta..vertline. and .vertline.cos .theta..vertline. are set in an in-area lattice point detection circuit, through an unrepresented CPU. Also, according to the center of rotation instructed by the operator, values of main-scan offset and sub-scan offset are set in the rotated coordinate calculating circuit 22' and the coordinate inverse conversion circuit 28', again through the unrepresented CPU.

In response to the synchronization signal released by the synchronization control unit, the scan data source supplies image data in the form of scan data to a raster memory, of which structure is shown in FIG. 19A. It is composed of four line memories corresponding to four scan lines, of which one is used for receiving image data from the scan data source while other three are used, with already received data for effecting the processes of rotation and interpolation. During the input of scan data for a scan line, data are released from one of the scan lines already received.

As shown in FIG. 15, for the scan data already entered, the rotated coordinate calculating circuit calculates the coordinates obtained by image rotation of the input coordinates. The in-area lattice point detection circuit 24' detects the lattice points of the output image, present in a square having the center at the rotated coordinate and having a size of .vertline.sin .theta..vertline.+.vertline.cos .theta..vertline.. Based on thus detected lattice points, the coordinate inverse conversion circuit 28' successively determines the coordinates of said lattice points in a coordinate system after said system itself is subjected to rotation. From said coordinates there are determined input pixels to the employed in the interpolation and the coefficients to be employed in the interpolation, respectively from the integer part and the fractional part of the values of said coordinates. In this manner the value corresponding to the output lattice point is determined and released.

Now reference is made to FIG. 16 for explaining the rotated coordinate calculating circuit 22, for effecting the calculation of the aforementioned equation (1). The circuit functions in response to synchronization signals employed in the scan data source. In response to the page synchronization signal, a sub-scan counter is reset and loaded with an initial value "-2", in order that the circuit starts to function with a delay of two scan lines from the scan data source. Also in response to the sub-scan synchronization signal, a main scan counter is reset and is loaded with an initial value "0". The values x, y in said equation (1) are respectively given by the outputs of the main-scan counter and sub-scan counter, and values x.sub.c, y.sub.c are respectively given by the main-scan offset and sub-scan offset defining the coordinate of the center of rotation. Also according to the rotation angle .theta., values sin .theta., cos .theta. and -sin .theta. are set as constants. By addition, subtraction and multiplication of these data there is obtained the coordinate (x', y' ) after rotation, in fractional numbers.

In the following the in-area lattice point detection circuit will be explained, with reference to FIG. 17. It defines a square having the center at the coordinate after rotation, and having a side of .vertline.cos .theta..vertline.+.vertline.sin .theta..vertline. and releases coordinates of lattice points, which are points having integer coordinate both in the main-scanning and sub-scanning directions, present in said square (cf. square in FIG. 21A). As coordinate output, it releases the integer parts, after truncation of fractional parts, of values obtained by adding (.vertline.cos .theta..vertline.+.vertline.sin .theta..vertline.)/2 respectively to x' and y', and the integer parts, after truncation of fractional parts, of values obtained by subtracting (.vertline.sin .theta..vertline.+.vertline.cos .theta..vertline.)/2 and adding 1 to x' and y' (cf. A, B, C and D in FIG. 21A).

Integer coordinates of said lattice points in a coordinate system which is itself subjected to rotation are determined by a cordinate conversion circuit shown in FIG. 18, which effects an inverse conversion (rotation of -.theta.) of the process of calculating coordinates after rotation shown in FIG. 16.

The values of the integer part and the integer part plus one of the thus inversely converted coordinates in the main-scanning and sub-scanning directions are used to determined four pixels (a, b, c and d in FIG. 21B) in the raster buffer, and the corresponding fractional parts are used to determine the interpolation coefficients (.alpha., .beta. in FIG. 21C). Thus an interpolation calculating circuit shown in FIG. 7 executes a calculation according to the equation (2) to obtain correction values. The circuit shown in FIG. 7 successively releases correction values for four lattice points (which can eventually be a same point), in response to a main-scan synchronization clock signal.

FIG. 20 shows the movement of scan point by the main-scan clock. Interpolations for 4 pixels are conducted for each main-scan synchronization signal However, the main-scan outputs 1 and 2, released from the in-area lattice point detection circuit shown in FIGS. 15A or 17 may eventually become equal, and the sub-scan outputs 1 and 2 may also become equal. In the case where they are all different, the interpolation is conducted for different four pixels. On the other hand, if the outputs in the main or sub-scanning direction are the same, the interpolation is conducted for four pixels which are mutually the same in pairs. Also if said outputs are same both in the main and sub-scanning directions, the interpolation is conducted for the 4 same pixels. These cases correspond respectively to the presence of 4, 2 or 1 output pixel in the square shown in FIG. 20B. The calculation conducted by the interpolation process circuit is the same as explained in the first embodiment.

In the foregoing there has been explained a case of image rotation in the same size. In the following there will be explained a second variation for an image rotation combined with an image size variation in a same proportion in the main and sub-scanning directions.

This variation is schematically shown in FIGS. 22A and 22B, wherein components of same functions as those in FIGS. 3A and 3B are represented by same numbers or symbols.

FIG. 23 is a detailed block diagram of a rotated coordinate calculating circuit 22" shown in FIG. 22A, and FIGS. 24A and 24B are detailed block diagrams of an in-area lattice point detection circuit 24". Also FIG. 25 is a detailed block diagram of a coordinate inverse conversion circuit 28" shown in FIG. 22B.

In the following there will be explained the function of the above-mentioned variation.

In response to an instruction for image rotation given by an operator, an operation indication unit sets information corresponding to the instructed angle of rotation in a process circuit. Also in response to an instruction for image enlargement or reduction, the process circuit is given information corresponding to the proportion of image size variation. Then in response to a start instruction from the operator, the operation unit activates a synchronization control unit which executes required operation by giving synchronization signals to a scan data source and the process circuit (cf. FIG. 2).

The image data are scanned as shown in FIG. 8. The start of image in a page is defined by the down shift of a page synchronization signal, while the start of each scan line in a page is defined by the down shift of a sub-scan synchronization signal, and the fetch timing of each pixel data is defined by the down shift of main scan synchronization signal (cf. FIGS. 9 and 10).

In the following there will be explained the operations of image rotation, enlargement, reduction and interpolation. According to the rotation angle .theta. instructed by the operator, values of sin .theta., -sin .theta. and cos .theta. are set in a processed coordinate calculating circuit and in a coordinate inverse conversion circuit, and values of .vertline.sin .theta..vertline. and .vertline.cos .theta..vertline. are set in an in-area lattice point detection circuit, both by means of an unrepresented CPU. Also according to the center of rotation instructed by the operator, values of main-scan offset and sub-scan offset are set in the processed coordinate calculating circuit and the coordinate inverse conversion circuit. Furthermore, the proportion .alpha. of image size variation is set in the processed coordinate calculating circuit and the in-area lattice point detection circuit, and the corresponding reciprocal 1/.alpha. is set in the coordinate inverse conversion circuit.

In response to the synchronization signal released by the synchronization control unit, the scan data source supplies image data in the form of scan data to a raster memory, of which the structure is shown in FIG. 11A. It is composed of four line memories corresponding to four scan lines, of which one is used for receiving image data from the scan data source, while other three are used, with already received data, for effecting the processes of rotation, enlargement, reduction and interpolation. During the input of scan data for a scan line, data are released from one of the scan lines already received.

As shown in FIG. 22, for the scan data already entered, the processed coordinate calculating circuit calculates the coordinates obtained by image rotation and image enlargement or reduction of the input coordinates. The in-area lattice point detection circuit detects the lattice points of the output image, present in a square having the center at the processed coordinate and having a side of .alpha.(.vertline.sin .theta..vertline.+.vertline.cos .theta..vertline.). Based on thus detecte lattice points, the coordinate inverse conversion circuit successively determines the coordinates of said lattice points in a coordinate system after said system itself is subjected to enlargement or reduction and rotation. From said coordinates there are determined input pixels to be employed in the interpolation and the coefficients to be employed in the interpolation, respectively from the integer part and the fractional part of said coordinates. In this manner the value corresponding to the output lattice point in determined and released.

Now reference is made to FIG. 23 for explaining the processed coordinate calculating circuit for effecting the calculation of the aforementioned equation (1). The circuit functions in response to the synchronization signals employed in the scan data source. In response to the page synchronization signal, a sub-scan counter is reset and loaded with an initial value "-2", in order that the circuit starts to function with a delay of two scan lines from the scan data source. Also in response to the sub-scan synchronization signal, a main scan counter is reset and loaded with an initial value "0". The values x, y in said equation (1) are respectively given by the outputs of the main-scan counter and the sub-scan counter, and values x.sub.c, y.sub.c are respectively given by the main-scan offset and sub-scan offset difining the coordinate of the center of rotation. Also according to the rotation angle .theta., values of sin .theta., cos .theta. and -sin .theta. are set, and the proportion of image size variation is also set. By addition, subtraction and multiplication of these data there are obtained the coordinates (x', y') after rotation, in fractional numbers.

Now the in-area lattice point detection circuit will be explained, with reference to FIG. 24A. It defines a square having the center at the coordinate after processing, and having a side of .alpha.(.vertline.cos .theta..vertline.+.vertline.sin .theta..vertline.), and releases main and sub-scanning coordinates of lattice points, which are points having integer coordinates both in the main and sub-scanning directions, present in said square (cf. square in FIG. 26A). As the outputs it releases the integer parts, after truncation of fractional parts, of values obtained by adding .alpha.(.vertline.cos .theta..vertline.+.vertline.sin .theta..vertline.)/2 respectively to x' and y', and other integer parts, after truncation of fractional parts, of values obtained by subtracting .alpha.(.vertline.cos .theta..vertline.+.vertline.sin .theta..vertline.)/2 and adding 1 to x' and y' (cf. A, B, C, D, E, F, G, H and I in FIG. 26A).

Integer coordinates of said lattice points in a coordinate system which is itself subjected to rotation are determined by a coordinate conversion circuit shown in FIG. 25, which effects an inverse conversion (rotation of -.theta.) of the process of calculating coordinates after processing.

The values of integer part and integer part plus one of thus inversely converted coordinates are used to determine four pixels (a, b, c and d in FIG. 26B) in the raster buffer, and corresponding fractional parts are used to determine the interpolation coefficients (.alpha., .beta. in FIG. 26C). Thus an interpolation calculating circuit shown in FIG. 7 executes a calculation according to the equation (2) to obtain correction values in the same manner as in the first embodiment. The circuit shown in FIG. 7 effects interpolation for all the lattice points present in the aforementioned imaginary square in the processed coordinate system, in response to each main-scan synchronization clock signal.

Based on the maximum and minimum coordinates in the main-scan direction (main-scan outputs 1 and 2) and maximum and minimum coordinates in the sub-scan direction (sub-scan outputs 1 and 2) of the lattice points present in said square area, the circuit shown in FIG. 24B releases the main-scan and sub-scan coordinates of all the lattice points present in said area, in synchronization with a main-scan operation synchronization clock signal which is faster than the main-scan synchronization signal and with a sub-scan operation synchronization clock signal which is faster than said main-scan operation synchronization signal. In comparison with the main-scan synchronization signal, the main-scan operation synchronization signal is faster at least by a factor of (integer part of proportion of size variation.times..sqroot.2+1). In the present embodiment it is 4 times faster (cf. FIG. 5C). Also in comparison with the main-scan operation synchronization signal, the sub-scan operation synchronization signal is faster at least by a factor of (interger part of proportion of size variation.times..sqroot.2+1)(cf. FIG. 5D). In the present embodiment, wherein said proportion is 1.6 times, the latter should be faster by [1.6.times..sqroot.2+ 1=3 times. One-shot down counters 1, 2 shown in FIG. 24B release high-level signals during a counting operation, and releases low-level signals when the count reaches zero. There are further provided down counters 3, 4 in FIG. 24B. The interpolation process circuit executes the calcuation in the same manner as explained in the first embodiment.

The lattice point detection circuit shown in FIG. 24A utilizes the values .vertline.sin .theta..vertline. and .vertline.cos .theta..vertline. determined according to the rotation angle .theta., but there may also be employed a constant K=.sqroot.2 independent of the rotation angle .theta., as shown in FIG. 14. In this case it is rendered possible to dispense with the setting of said values and therefore to reduce the magnitude of circuit.

Also the detection of output lattice point, for which the interpolation data are to be determined, can be effected by determining the address of main scan line in the converted coordinate system through a digital differential analysis and then determining the lattice points close to said line, one by one.

This process will be clarified in more detail in the flollowing, and, for the purpose of simplicity there will be considered an example of rotation of a line segment by 30.degree. without size change, about the original point of the coordinate system.

FIGS. 28A, 28B and 28C illustrate the mode of conversion of image data in this process, wherein the abscissas 120, 121, 122 indicate respective main scanning directions, circles indicate sampling points, and the ordinates indicate the value of multi-level data, for example image density. FIG. 28A shows an original image, while FIG. 28C shows a digital output image obtained by this process, and FIG. 28B shows an example conventional technology in which the original image is rotated without interpolation. In the following there will be explained an example of obtaining the value of multi-level data at a sampling point 123 in FIG. 28C.

FIG. 29 shows an example of the circuit for providing the address of a main scan line 122 of the output image shown in FIG. 28C. In the present example, for a rotation of 30.degree. about the original point, values "0" are set in the integer portion 133 and the fractional portion 132 of a result register 130, while a value of tan 30.degree.=0.577350 is set in an incremental register 134. Also the number of pixels in the main scan line of the output image is set in a count register 135. These values are calculated and set by unrepresented hardware or software. By supplying clock signals the same as synchronization signals 137, 138, the content of the incremental register 134 and the content of the fractional portion 132 of the result register are added, and the content 139 of the integer portion 132 of said result register 130 is released in the order of 0, 1, 2, 3, . . . as the y-axis address of the main-scan line 122, as shown in FIG. 30.

As indicated by 100 in FIG. 36, the approximated line obtained in this manner always has a y-address for each x-address.

This logic circuit, composed solely of adding circuit, is inexpensive and can achieve a sufficiently high speed.

FIG. 31 shows a circuit for determining coordinates corresponding to the centers of pixels of the converted image, in the coordinate system of the original image, in response to a carry signal 131 shown in FIG. 29. X and Y values corresponding to a carry signal 131 "0", i.e., in a case of no change in the Y-address are calculated in the following manner:

by unrepresented means and stored respectively in incremental registers 510, 530, while those corresponding to a carry signal "1", i.e., to a case of one increment of the Y-address are calculated in the following manner:

and stored respectively in incremental registers 520, 540. These values are calculated and set by hardware or software not shown in FIG. 31. X- and Y-result registers 550, 560 store "0" since the present example involves a rotation about the original point only. Then, same clock signals as synchronization signals 37, 38 shown in FIG. 29 are supplied to the circuit in this state, and, in response to the carry signal 131 shown in FIG. 29, the contents of the X- and Y-incremental registers are added respectively to those of the result registers to release the values of X and Y coordinates of the original image through signal lines 590, 591, as shown in a timing chart in FIG. 32. This logic circuit, solely composed of adding circuits, can be made inexpensive and can achieve a sufficiently high speed.

Finally FIG. 33 shows the concept of calculating a weighted average of two close points from the values 590, 591 of the X- and Y-coordinates obtained from the X- and Y-result registers shown in FIG. 31. In FIG. 33, m indicates the fractional portion of X-coordinate 590 shown in FIG. 31. The multi-level digital value Y of the coordinate 70 can be determined by:

wherein X.sub.71 and X.sub.72 are multi-level digital values of pixel centers 71, 72 of the original image. Thus the multi-level digital value of the pixel 123 in FIG. 28C can be determined by introducing the multi-level digital values 124, 125 in FIG. 28A respectively into X.sub.71 and X.sub.72.

Though the foregoing explanation is related to rotation of a line segment without size change, it is also possible to rotate image data by employing three line buffers in the main scanning direction of the original image as shown in FIG. 34, also employing a circuit for determining an approximation for a line of the main scanning direction after conversion as shown in FIG. 37, saving a carry signal 110 released from a result register 113 in an address of a memory 112, designated by an address signal 111 from a count register 114, and supplying thus saved carry signal to a circuit shown in FIG. 31, thereby achieving interpolation for the output digital image in two-dimensional method as shown in FIG. 35, according to the following equation:

In fact it can be easily achieved by repeating the steps of determining the coordinates in the original image and effecting an interpolation a number of times corresponding to the number of pixels in the sub-scan direction of the converted image.

A rotation angle in a range of 45.degree. to 360.degree. can be regarded as a variation of rotation of 0.degree. to 45.degree. according to a method shown in FIG. 38B. It is therefore possible also to increase the processing speed, by having a memory table of bit trains of the carry signals generated in the circuit shown in FIG. 37.

Though the foregoing example has been limited to an image rotation without size variation, it is also possible to achieve an image enlargement by slowing the input timing of the original image data according to the proportion of image enlargement, or an image reduction by increasing the number of line buffers shown in FIG. 34.

The object of a second embodiment is, in a case where the coordinates of the output pixels of a processed digital image are irrational numbers including fractional portions, namely for a rotation of an arbitrary angle combined with enlargement or reduction of an arbitrary proportion, to match the addresses of the output pixels of the processed digital image with the input timing of the original digital image, or to determine the addresses of said output pixels in synchronization with the signal of the original digital image in the sub-scanning direction. The addresses of the output pixels of the processed digital image can be determined in various methods, but, in the present embodiment, digital differential analysis is employed to determine an address of the output pixel minimizing the distance from a line in the sub-scanning direction of the processed digital image to the address of the output pixels, and then to determine the address of a line in the main-scanning direction of the processed image, based on thus determined address of the above-mentioned output pixel as an initial value. This process will be explained in more detail in the following, wherein, for the purpose of simplicity, is considered a rotation of 30.degree. about the original point without size change. FIG. 40 is an enlarged view of FIG. 1D around the original point therein, wherein circles indicate centers of pixels and double circles 223, 224, 225 indicate centers of starting pixels of rasters 220, 221, 222.

FIG. 41 shows the schematic process of determing the address of the center of a starting pixel, wherein 236 indicates a line of the sub-scanning direction of the processed image in FIG. 40. .theta. in FIG. 41 is equal to 30.degree. in present example. 233 and 234 repectively indicate distance from the line 236, when pixel center moves from 230 to 231, or to 232. A thick line 227 in FIG. 40 indicates an address of the pixel center on each raster closest to the line 226, and FIG. 39 shows a circuit for determining each address.

In the following there will be explained a case of determining the address of the starting pixel 224, shown in FIG. 40. In FIG. 39, a latch retains the address increment "0" in the Y-direction of a pixel center 228 succeeding to the starting pixel 223 of an immediately preceding raster, or the raster 220 in FIG. 40, while an incremental register A 245 stores a value 233 in FIG. 41 or a value of cos 30.degree.=0.8660, then an incremental register B 243 retains a value 234 in FIG. 41 or -sin 30.degree.=-0.5, and a result register 248 retains the distance from the starting pixel of an immediately preceding raster to the line in the sub-scanning direction of the processed image or the distance "0" from the starting pixel 223 to the line 226 in FIG. 41. These values are calculated and stored by unrepresented hardware or software. A comparator 240 discriminates whether the content of the result register 248 is equal to zero or smaller. The result of the comparison is transferred to a comparator B 241, which discriminates whether the value in a latch 242 is zero when the value of the result register 248 is zero or less. These signals are transferred to a selector 246 which selects the value "-0.5" of the incremental register B 243 if the value of the result register 248 is larger than zero, or the value "0.8160" of the incremental register A 245 if the value of the result register 248 is zero or less and if the value of the latch 242 is one, or a value "0.366" which is equal to the sum of the values of registers 243, 245 if the value of the result register 248 is zero or less and if the value of the latch 242 is zero, and adds the thus selected value to the result register 248. Simultaneously it indicates the selected state by a signal 249. Also there is conducted step, by a hardware or software not shown in FIG. 41, of subtracting "1" from the Y-address of the starting pixel if the value of the result register 248 is larger than zero, or adding "1" to the X-address of the starting pixel if the value of the result register 248 is zero or less and if the value of the latch 242 is one, or adding "1" to the X-address and subtracting "1" from the Y-address if the value of the result register 248 is zero or less and if the value of the latch 242 is zero. In this manner there is determined the address of the starting pixel of each raster. The above-explained circuit, being composed of comparators and selectors, can be realized inexpensively and can achieve a sufficiently high speed.

Then, by hardware or software not shown in FIG. 42, the X- and Y-addresses of the output starting pixels determined above are respectively set in an X-address register 250 and a Y-address register 254 shown in FIG. 42, and a value of tan 30.degree.=0.57735 is set in an incremental register 251. Subsequently a pixel clock signal is supplied as the synchronization signal 256, whereby the addresses of pixel centers of a line 221 which constitutes, as shown in FIG. 40, an approximated main-scan line, starting from the starting pixel, of the output image.

Simultaneously with the determination of the address of the center of each output pixel, there is conducted by hardware or software not shown in FIG. 42, steps of determining the pixels of the original image corresponding to the address of each output pixel and determining the pixel data of said output pixel from said pixels of the original image.

In the foregoing embodiment the address of the starting pixel of the output image is determined by selecting two increments, and by minimizing the distance from a line of the sub-scan direction of the output image, calculated from said increments. It is also possible, however, to determine the address of the starting pixel, as shown in FIG. 43, utilizing an expansion of the trigonometrical function tangent ##EQU7## wherein a, b, c, . . . are integers. For example, for .theta.=30.degree., there can be employed: ##EQU8## FIG. 43 shows the process of determining the address of the starting pixel of a fourth raster of the output image, utilizing the above-mentioned expansion. There is considered a triangle containing a fourth point 261 from the original point on a vertical line 264 and a line 265 forming an angle of 30.degree. to said line at the original point 260, and the X-address of a point 262 is determined in the following manner from the values of denominators:

wherein symbols indicates the truncation of fractional portion.

Then, the Y-address of an apex point 263 forming an angle 266 of 30.degree. to a line between the points 261 and 262 is similarly determined by:

in this manner the X- and Y-addresses of the starting pixel 63 can be determined. FIG. 44 shows an example of the starting pixels determined in this process, wherein white circles indicate starting pixels.

Consequently a rotation of an arbitrary angle can be realized by storing the values of denominators of the equation (2) for an arbitrary angle in a memory. Also the precision of the expansion, or the magnitude of denominator can be limited by the maximum magnitude of the rotation. For example for a rotation corresponding to a resolution of 16 pels/mm on an A4 - sized sheet, the denominator can be limited to 4752.

As explained in the foregoing, addition of an image processing apparatus containing a circuit for generating the addresses of output start pixels allows easy processing of a high-quality image in synchronization with input image data.

FIGS. 45 to 57 illustrate a third embodiment of the present invention.

FIG. 46 shows a scan image as input data source, with main and sub-scanning directions, wherein arrows indicate scan lines.

FIG. 45 is a block diagram of an entire image processing apparatus. Scan data of two lines are entered via a pre-stage buffer 291, from which data interpolated for an image enlargement of 2.sup.n times are supplied in succession to an intermediate buffer 292. It stores data of 3 lines from which there are obtained final enlarged or reduced data for fine reduction.

Now reference is made to FIG. 46. According to an instruction given by the operator, a proportion of image enlargement is set in a 2.sup.n image enlarging circuit 422, and a proportion of image reduction is set in a fine reduction circuit 423. Also a synchronization control unit 424 is so set to slow the main-scan synchronization clock signal according to the areal image magnification, which is the product of the proportions of image enlargement in the main and sub-scanning directions set in the circuit 422. The scan data are fetched in three prestage buffers 291 which are switched in synchronization with the sub-scanning. The 2.sup.n enlarging circuit 422 receives the scan data of two lines already stored in two pre-stage buffers 291, and scan data are fetched in the remaining prestage buffer while said circuit 422 conducts image enlarging process on the scan data from two pre-stage buffers.

FIG. 47 shows an example of enlarging the input image 4 times in the main scanning direction and 2 times in the sub-scanning direction. In FIG. 47, A, B, C and D correspond to the pixels of the original image, with respective image data V(A), V(B), B(C) and V(D). The The pixels A and B are on a same raster, while the pixels C and D are on another raster. Dots 311-314 and 321-324 are output dots to be obtained by image enlargement, wherein 311-314 are on a same output raster while 321-324 are on another output raster. value V(Q) of a dot Q in said dots 311-314, 321-324 is defined by:

wherein .alpha. (0.ltoreq..alpha.) is an interior division ratio of a line segment AB intersected by a line parallel to a line segment AC, and .beta.(.beta..ltoreq.1) is an interior division ratio of a line segment AC intersected by a line parallel to a line segment AB. FIG. 48 is a block diagram of a circuit for calculation of the equation (1), wherein a block 441 calculates (1-.alpha.)V(A)+.alpha.V(B), while a block calculates (1-.alpha.)V(C)+.alpha.V(C), and a block 443 calculates (1-.beta.){(1-.alpha.)+.alpha.V(B)}+.beta.{(1-.alpha.)V(C)+.alpha.V(D)}=(1 -.alpha.) (1-.beta.)V(A)+.alpha.(1-.beta.)V(B)+(1-.alpha.).beta.V(C)+.alpha..beta.V( D)=V(Q). FIG. 49 is a block diagram of the circuit block 441, 442 or 443, which are of a similar structure, which calculates (1-k)V(X)+kV(Y) from input image data V(X) and V(Y) and an interior division ratio k. A circuit 453, of which details are shown in FIG. 50, calculates 1-k from k. The ratio k is a fractional number expressed in four bits and is selected from 0, 1/8, 1/4, 3/8, 1/2, 5/8, 3/4, 7/8 and 1. More specifically k is represented by 4-bit signals x.sub.0, x.sub.-1, x.sub.-2 and x.sub.-3 (each 0 or 1) as follows:

so that 1-k can be represented by a complement of k to 2. The circuit shown in FIG. 50 calculates 1-k by determining a complement of k to 2. This calculation is achieved by inverting respective bits by inverters 461-464 and adding 1 to the lowest bit wherein the highest bit assumes a value 1 only when k is zero, i.e. only when x.sub.0, x.sub.-1, x.sub.-2 and x.sub.-3 are all zero. FIG. 51 shows the details of the circuit 451 or 452, which are constructed the same. The circuit 451 or 452 generates data A by extracting, from the input image data, the upper 7 bits thereof shifting them to lower bits respectively by one bit, and data C by-extracting upper 6 bits and shifting them to lower bits respectively by one bit. Among the aforementioned 4-bit fractional number, the bit of a digit of 1/8 is used as a gate signal for the data C, that of a digit of 1/4 as a gate signal for the data B, and that of a digit of 1/2 as a gate signal for the data A. Each gate releases the input data if a corresponding gate signal is of high level, but releases zero if said gate signal is of low level. The sum of the outputs of the gates or the signal V(Y) is selected by the signal of a digit of 1 to obtain a product of the image data and the interior division ratio. The above-described operations are executed with the duration of an input-scan synchronization clock, so that said operations require a clock signal faster than said synchronization signal by the areal image magnification. FIG. 52 shows a circuit for successively generating .alpha. and .beta., which is composed an octanary up-counter 481, a clock signal 8 times faster than the 2.sup.n enlarging circuit, a flip-flop 482 for dividing said clock signal into a half frequency, another flip-flop 483 for dividing the output of the flip-flop 482 into a half frequency, and a selector 484. The increment in .alpha. or .beta. is determined by selecting a clock signal, in response to a 2-bit selection signal supplied to the selector. Said selection signal is set in advance in a CPU according to the proportion of image enlargement. FIG. 53 is a timing chart showing the relation of clock signals in the circuit shown in FIG. 52. The increment of .alpha., .beta. is determined by employing the circuit shown in FIG. 52 for each of .alpha. and .beta.. In this manner the enlarged data are prepared in succession and supplied, as scan data, to the intermediate buffer through a buffer control unit (3) 427.

In the following there will be explained the fine reduction circuit. In the image data prepared by the 2.sup.n enlargement circuit, the main scanning direction and the sub scanning direction are respectively defined by x-axis and y-axis, and each pixel is defined by an address (x.sub.s, y.sub.s). The proportion of image reduction in the main scanning direction is represented by .delta. (1/2.ltoreq..delta..ltoreq.1) and that in the sub-scanning direction is represented by .epsilon. (1/2.ltoreq..epsilon..ltoreq.1). The output address (x.sub.D, y.sub.D) is given by:

wherein x.sub.m and y.sub.m indicate the amounts of parallel displacement along the main-scanning and sub-scanning directions. The coordinate (x.sub.s, y.sub.s) indicates a pixel on a central one of three consecutive rasters of the intermediate buffer 292. The values x.sub.D and y.sub.D are generally not integers but have fractional portions. The image data are relased to an integer address in the vicinity of a position defined by said x.sub.D and y.sub.D. Such integer address in the vicinity can be determined by a circuit shown in FIG. 54, and FIG. 55 illustrates the vicinity of the point (x.sub.D, y.sub.D). A point E corresponds to (x.sub.D, y.sub.D), while broken lines indicate the reduced state of the data in the intermediate buffer, while and solid lines indicate a lattice of integer address space of the output data. The vicinity of the point E is defined by a rectangle of lengths of l and m. In said vicinity area there exists an integer address point a. In the present example there are assumed conditions l=.delta. and m= .epsilon., and the point E is positioned at the center of said rectangle. The coordinate (x.sub.R, y.sub.R) of a point R and the coordinate (x.sub.T, y.sub.T) of a point T shown in FIG. 55 are obtained by a circuit shown in FIG. 58. The initial values and increments are selected in the following manner:

For x.sub.R and y.sub.R, the initial value includes "1" in order to obtain an integer address by truncation afterwards.

In the following there will be explained a process of calculating the output value. From an integer address (x.sub.D, y.sub.D) in the vicinity there can be determined a corresponding input address (x.sub.s, y.sub.s) by the following equations:

wherein x.sub.D and y.sub.D are integers, and x.sub.s and y.sub.s are real numbers containing fractional portions. Output data are obtained by an interpolation in the same manner as explained before, with an interpolation ratio p:q based on the fractional portions of x.sub.s and y.sub.s, on the input image data of points corresponding to the integer parts of said x.sub.s and y.sub.s and to said integer plus one.

More specifically, p is equal to the fractional portion of x.sub.s while q is equal to the fractional portion of y.sub.s, and, for the foregoing example of the point a, integer points D, E, G and H are determined from x.sub.s and y.sub.s as shown in FIG. 56.

Consequently the value of the point (x.sub.D, y.sub.D) is given by:

For the calculations of equation (4) and (5) there is employed a circuit similar to that shown in FIG. 54. When at least one of the integer portions of the outputs x.sub.R, x.sub.T and outputs y.sub.R, y.sub.T of FIG. 54 is charged and the integer portions become equal to each other, a pulse is generated as a clock of FIG. 55 from a not-shown circuit.

In these calculations the initial values and increments are selected as follows:

As explained in the foregoing, the present invention provides an advantage of enabling an image rotation and/or an image size variation of a scan digital image synchronization with the scanning operation, without the use of a memory in the input side and with a minimized deterioration of image quality resulting from massing or misalignment of pixels of the image. Also the present invention enables an image rotation and/or image size variation in real-time basis on input scan data.

The present invention is not limited to the foregoing embodiments but is subject to various modifications and variations within the scope and spirit of the appended claims.