US 4,849,965 AGrant
Asynchronous Digital Time-Division Multiplexing System With Distributed Bus
Issue Date:1989-07-18
•10 Claims
•6 Drawing Sheets
Abstract
The system comprises a first unidirectional packet bus having a bit rate D, each packet including an e-bit identifier and a b-bit package, sources having differing bit rates d.sub.i such that d.sub.m .ltoreq.d.sub.i .ltoreq.d.sub.M <D, and access means for introducing packets from the sources into the first bus. An allocator located at the receiving end of the first bus builds up frames of identifiers identifying active sources. Each frame has a length T=b/d.sub.m and is shared into N=d.sub.M /d.sub.m time slots. Each time slot has a period .theta.=b/d.sub.M and includes a source identifier. The identifier for a same active source having a bit rate d.sub.i is repeated in the frame n.sub.i times such that n.sub.i =d.sub.i /d.sub.m when d.sub.i /d.sub.m is an integer, or such that n.sub.i =1+ integer part of (d.sub.i /d.sub.m) otherwise. The identifier frames are transmitted from the allocator into a second unidirectional bus distributed to all the access means. The access means of each source transmits a packet in the first bus whenever a b-bit package delivered from the source is received and an identifier of the source is detected in the second bus after package reception.
Metadata
Inventors
- Denis Chomel
- Michel Devault
- Herve Le Bris
- Yvon Rouaud
Application Information
Application Number:US 0732931
Filing Date:1987-07-07
Priority Date:1983-10-14
Art Unit:263
Classifications
IPC:
H04J 302
Patent Drawings (6 sheets)
Description
Brief Description of the Drawing
The invention will be more explained from the following description of a preferred embodiment of the invention with reference to the appended corresponding drawings in which:
FIG. 1 is a schematic block diagram of the asynchronous digital time-division multiplexing system with distributed bus according to the invention;
FIG. 2 shows the identifier frame structure;
FIG. 3 shows packet propagation charts for the first packet transmission bus;
FIG. 4 is a block diagram of the system allocator;
FIG. 5 shows time charts of various signals derived in the allocator;
FIG. 6 is a block diagram of a packetizer-multiplexer linking a source to the two system buses; and
FIG. 7 shows time charts of various signals derived in the packetizer-multiplexer.
Description of the Preferred Embodiments
With reference to FIG. 1, an asynchronous digital time-division multiplexing system comprises a unidirectional bus 1 for the distributed transmission of data packets from data sources 2.sub.1 to 2.sub.I towards a data concentrator 3 connected to an asynchronous time switching network. Each source is connected to bus 1 across a packetizer-multiplexer 4.sub.1 to 4.sub.I. Each packetizer-multiplexer 4.sub.1 to 4.sub.I is authorized to transmit a data packet in bus 1 under the control of an allocator 5 included in concentrator 3 via a unidirectional bus 6 distributed over each of the packetizers-multiplexers.
Sources 2.sub.1 to 2.sub.I respectively transmit data to packetizers-multiplexers 4.sub.1 to 4.sub.I through digital paths 7.sub.1 to 7.sub.I having bit rates d.sub.1 to d.sub.I. The rates d.sub.1 to d.sub.I differ from one to the other generally speaking, and lie between a minimum rate value d.sub.m and a maximum rate value d.sub.M. Sources 2.sub.1 to 2.sub.I are respectively associated with control processors 8.sub.1 to 8.sub.I that make it possible to tell a central processor 9 included in concentrator 3 when the sources are activated. Central processor 9 is connected to processors 8.sub.1 to 8.sub.I through a star structure of bidirectional links 90.sub.1 to 90.sub.I in which are carried various signalling signals between each source and the processor 9 so that the source may request access to bus 1 in order to transmit data and thus indicates its activation at the start of a communication or so that the source may advise its deactivation at the end of a communication. The signalling signals are transmitted for example in accordance with a known packet exchange protocol such as a high level data link control procedure (HDLC) via the star structure. In what follows, consideration is lent to the operation of active sources after the exchange of signalling signals at the start of a communication. At a given time, some sources are active and some sources are inactive. Each of packetizer-multiplexers 4.sub.1 to 4.sub.I connected to an active source 2.sub.1 to 2.sub.I the digital signal transmitted by digital path 7.sub.1 to 7.sub.I from respective active source 2.sub.1 to 2.sub.I in the form of packets P.sub.1 to P.sub.I. Each packet P.sub.1 to P.sub.I to be transmitted in bus 1 is made up of a data package having a predetermined number of bits b=k.e, where k is an integer, and a source identifier E.sub.1 to E.sub.I having e bits preceding the package. An identifier E.sub.i is a binary word representing the number i of the source S.sub.i, where i is an integer varying between 1 and I. Bus 1 carries in asynchronous mode the time-division multiplexed packets delivered from packetizers-multiplexers associated with several simultaneously active sources having received an authorization to transmit from allocator 5 via allocation bus 6.
As depicted in FIG. 2, bus 6 carries a periodic frame having a length T and split into N time slots IT.sub.1 to IT.sub.N each having a length .theta.. Each time slot IT is intended for transmitting an identifier E. The identifiers E are multiplexed in the frame T in allocator 5 in terms of the active source bit rates d.sub.1 to d.sub.I.
The source minimum and maximum bit rates d.sub.m and d.sub.M, together with time frame parameters .theta. and T are determined in terms of the transmission characteristics of packet transmission bus 1 and the numbers of bits e and b. The characteristics of bus 1 are as follows:
length L of buses 1 and 6 between packetizer-multiplexer 1 nearest concentrator 3 and packetizer-multiplexer 4.sub.I farthest from concentrator 3;
real bit rate D of bus 1 decidedly higher than the maximum bit rate d.sub.M such that bus 1 may carry packets from at least one source having the maximum bit rate d.sub.M ;
.tau.=propagation time per length unity in buses 1 and 6.
FIG. 3 depicts the propagation chart for packets from four packetizer-multiplexer 4.sub.i, 4.sub.i+3, 4.sub.I and 4.sub.l that are authorized to insert packets in bus 1 in the order indicated in the identifier frame formed by allocator 5 and shown in FIG. 2. The order of the authorizations is as follows: . . . i, i+3, I, 1. . . . If x.sub.i denotes the distance between allocator 5 and packetizer-multiplexer 4.sub.i, a transmission procedure for a packet P.sub.i from packetizer-multiplexer 4.sub.i commences with the transmission of the identifier E.sub.i into bus 6 for a propagation time .tau.x.sub.i and then finishes with the transmission of the packet P.sub.i delivered by packetizer-multiplexer 4.sub.i into bus 1 for a propagation time .tau.x.sub.i.
For allocator 5 to authorize successively the transmission of packets from any packetizer-multiplexer with no packet overlap, the packet allocation and transmission duration .theta. is selected for the least favorable case in which the transmission of a packet P.sub.I from packetizer-multiplexer 4.sub.I farthest (distance x.sub.I) from concentrator 3 is followed by the transmission of a packet P.sub.1 from packetizer-multiplexer 4.sub.1 nearest (distance x.sub.1) concentrator 3. To receive the packets P.sub.I and P.sub.1 successively without any dead time or overlap, the following relationship must be satisfied:
The above relationship is deduced by analysis from the right hand side of the chart in FIG. 3. The above relationship may also be expressed as:
The time .theta. depends therefore not on the total length of buses 1 and 6 but rather on the distance L=x.sub.I -x.sub.1 between packetizer-multiplexer 4.sub.1 and 4.sub.I at the ends.
The dead time 2.tau.L included in the allocation duration, during which time a packetizer-multiplexer transmits no digital signals, is independent of the real bit rate D in bus 1, whereby distributed packetizer-multiplexer may be conceived with a very high bit rate and using short packets. The shortness of the packets makes it possible to use a low-capacity buffer memory.
Granted that just one packet can be transmitted in a slot .theta., the maximum bit rate d.sub.M of the sources is therefore equal to b/.theta.. On the contrary, for a packetizer-multiplexer to deliver just one packet in the frame time T, the minimum bit rate d.sub.m of the corresponding source must be equal to b/T=b/(N.theta.). When a source has a bit rate d.sub.i between the minimum rate d.sub.m and the maximum rate d.sub.M, the corresponding label E.sub.i is repeated periodically or otherwise in the frame T a number n.sub.i of times such that:
n.sub.i =d.sub.i /d.sub.m if the ratio d.sub.i /d.sub.m is an integer or n.sub.i =(integer part of (d.sub.i /d.sub.m))+1 if the ratio d.sub.i /d.sub.m is not an integer.
Should the ratio d.sub.i /d.sub.m not be an integer, the last packet authorized to be transmitted in the frame T of bus 1 from the corresponding packetizer-multiplexer comprises a bit number less than p=e+b and can be transmitted such as with filling bits as per a known procedure, or can be transmitted with a part of the following package at the start of the following frame as will be seen through the description of a packetizer-multiplexer.
With reference to FIG. 4, allocator 5 comprises a random access memory RAM 50. Memory 50 contains N cells, each having e bits, for memorizing the N identifier words included in a frame T. Allocator 5 further comprises a time-base 51 as well as means under the control of central processor 9 for writing the identifiers associated with the packetizer-multiplexers that are authorized to transmit packets into bus 1, and means under the control of the time-base for reading the identifiers written in memory 50 to transmit an identifier frame of identifiers into allocation bus 6. Bus 6 is made up of three digital lines 60, 61 and 62. Line 60 carries the label frames. Line 61 carries an allocation presence signal synchronous with the frame identifiers. Line 62 carries a clock signal corresponding to the rate of the identifier bits in line 60.
Time base 51 includes a clock 510, a divide-by-2e frequency divider 511 and a logic circuit 512.
Output 513 of clock 510 supplies a clock signal having identifier bit frequency 2e/.theta. in transmission line 60. Clock output 513 is connected to an input of frequency divider 511 and to an input of logic circuit 512. Output 514 from frequency divider 511 delivers a signal at the allocation frequency 1/.theta.. Signals at outputs 513 and 514 are respectively shown in the first two time charts in FIG. 5. A first half-period of each signal period .theta. at output 514 is intended systematically for reading addressing of memory 50 and the transfer of available information into an output register 54 at the end of the first half-period. A second half-period of each period .theta. is intended, where applicable, for writing and reading addressing an identifier in memory 50. The access to memory 50 is for this purpose alternately synchronized in reading and writing by the signal on output 514 of frequency divider 511.
Output 514 of divider 511 is connected to a counting input of counter 52, an input-selecting input of a dual-input multiplexer 53 and an input of logic circuit 512. Counter 52 has a cycle equal to the number N of time slots IT in the frame T, when N is chosen as equal to a power of 2. An output counter bus 520 having n=log.sub.2 N leads supplies the reading addresses of the cells containing the successive identifiers in the frame T to one of the two inputs of multiplexer 53 that passes them onto an address input 500 of memory 50 during the first half-periods of periods .theta. in the frame. A loading pulse shown in a third time chart depicted in FIG. 5 marks the transition between the first and second half-periods of each period .theta.. Each loading pulse has a length equal to .theta./(2e). The loading pulse is supplied by an output 515 of logic circuit 512 to an input of output register 54, and orders loading of the reading addressed identifier from into memory 50 into output register 54, via an e-lead output bus 501 of memory 50.
Logic circuit 512 also delivers an allocation signal into line 61, a clock signal into line 62 and a clock signal on output 516 to transfer the serialized identifier bits from register 54 to line 60. The signals on output 516 and in lines 60, 61 and 62 are shown in fourth, fifth, sixth and first time charts in FIG. 5 respectively. The signals on output 516 and in line 62 result from the clock signal on clock output 513. The allocation signal in line 61 is composed of blanks having a length .theta./2 and interlaced with the identifiers in line 60.
The writing operation for one identifier in memory 50 is decided by central processor 9 upon receipt thereby of a request to connect or a request to disconnect from the corresponding source through the respective star structure link 90.sub.1 to 90.sub.I.
A request to connect from a source 8.sub.i operating with bit rate d.sub.i consists for central processor 9 of writing the source 8.sub.i identifier E.sub.i n.sub.i times in memory 50 in n.sub.i free cells, corresponding therefore to free time slots IT in the frame T. If processor 9 does not find a sufficient number of available words, it refuses the request to connect.
On the contrary, a request to disconnect from source 8.sub.i consists of erasing the source ascribed words in memory 50 that are then each replaced by a predetermined word, containing for example only zero bits, that differs all the identifier words E.sub.1 to E.sub.I.
To prevent processor 9 from going access to memory 50 in reading, the search of free words for connection purposes or of erasable words for disconnection purposes is carried out in a memory analogous to memory 50, located in processor 9. The modifications to said analogous memory are transferred to memory 50. At a given time, certain time slots IT in frame T can contain the predetermined word for which no packetizer-multiplexer is programmed.
The cell writing addresses in memory 50 are fed selectively to addressing input 500 of memory 50 by an n-lead output 91 from processor 9 via a buffer register 55, a second input bus 550 of multiplexer 53 and multiplexer 53. Processor 9 receives the synchronization signal delivered from output 514 of frequency divider 511. During the first half-period of a period .theta., the processor loads the writing address into register 55, on the occasion of a writing cycle being under preparation. During the second half-period of period .theta., the writing address is fed to memory 50, via multiplexer 53. The identifier to be written is supplied from central processor 9 to memory 50 through an e-lead bus 92. A writing signal for memory 50 is provided by a link 93 in the middle of the second half-period in the period .theta.. The signal in link 93 is shown in a last time chart in FIG. 5.
A packetizer-multiplexer 4.sub.i connected to corresponding source 2.sub.i via digital path 7.sub.i is shown in detail in FIG. 6. Path 7.sub.i consists of a digital line 70 carrying a data signal having the bit rate d.sub.i, and a digital line 71 carrying a clock signal having the frequency d.sub.i.
Packetizer-multiplexer 4.sub.i comprises a packetizing circuit 40 for packetizing the bits transmitted from line 70 into data bit groups or packages having k.e=b bits. Circuit 40 comprises a first-in first-out FIFO buffer 400 that receives e-bit words having bits made parallel by a buffer register 401 connected to path 7.sub.i. Writing in buffer 400 is timed by a writing signal having frequency d.sub.i /e, supplied from a divide-by-e frequency divider 402 connected to line 71.
On the side of identifier distributing bus 6, packetizer-multiplexer 4.sub.i comprises an identifier detecting circuit 41 for detecting identifier E.sub.i ascribed to source 2.sub.i, and a data bit group detecting circuit 42.
Label detecting circuit 41 comprises an e-stage input register 410 that successively stores the frame identifiers transmitted from line 60 in bus 6. The identifiers are written in time with the clock signal in line 62, during the allocation times .theta./2 supplied by the allocation signal in line 61, by means of a two-input AND gate 411. The identifiers in line 60 are delivered from an e-lead output bus 412 of register 410 and are fed to a first input of a digital comparator 413. A second input of comparator 413 is connected to an e-lead output bus 414 of a register 415, such as a read only memory REPROM having memorized the identifier E.sub.i. When contents in registers 410 and 415 are equal, output 416 comparator 413 is in state "1", which indicates that a packet having p=b+e bits can be entered in bus 1.
Package detecting circuit 42 detects when k e-bit words have been stored and hence when a package of b bits has been formed in buffer 400. Circuit 42 then indicates that such a package can be transmitted in bus l in response to the detection of an identifier E.sub.i in bus 6. Circuit 42 comprises three flips-flops 420, 421 and 422 that change states under the effect of rise fronts applied to their clock inputs.
Data input D and clock input H of first flip-flop 420 are respectively connected to output 416 of comparator 413 and to line 61 via an inverter 423. Input D and clock input H of second flip-flop 421 are respectively connected to a predetermined output terminal 403 of buffer 400 and to output Q of flip-flop 420. Terminal 403 is at state "1" when buffer 400 contains at least b bits. Input D and clock input H of third flip-flop 422 are respectively connected to output Q of flip-flop 421 and to an output 430 of a clock 43 included in packetizer-multiplexer 4.sub.i. The clock signal from output 430 carries a frequency D equal to the real bit rate in bus 1.
Signals from output 403 of buffer 400, in line 61, from output Q of flip-flop 420, from output 430 of clock 43 and from output 424 of flip-flop 422 are shown in first five time charts in FIG. 7, when an identifier E.sub.i is detected after a b-bit package has been stored in buffer 400. The signal from output 424 of flip-flop 422 indicates the presence of at least b bits in buffer 400 and the allocation of a time slot .theta. in bus 1 in order to enter a package having b bits. The package is transmitted onto bus 1 under the control of a sequence timer 44 via a multiplexing circuit 45 included in packetizer-multiplexer 4.sub.i, as soon as timer 44 is triggered by the signal on output 424 from flip-flop 422.
Multiplexing circuit 45 comprises essentially a multiplexer 450 having two input e-lead buses, and an output e-stage register 451 connected to e-lead output bus 452 of multiplexer 450. In response to the trigger signal on output 424 of third flip-flop 422, timer 44, via a lead 440 in state "0", controls the selection of a first input bus of multiplexer 450 connected to output 414 of identifier E.sub.i register 451 under the effect of a first loading pulse in a lead 441. The k e-bit words grouped in the bottom of FIFO buffer 400 are read successively by timer 44. The timer, via lead 440 in state "1", controls the selection of a second input bus of multiplexer 450 connected to output e-lead bus 404 of buffer 400 such that the k e-bit words are successively loaded in output register 451 as controlled by k loading pulses in lead 441. The loading pulses are equal in length to 1/D and are delivered at a period equal to e/D. The (k+1) e-bit words thus read are transmitted in series in a digital line 10 in bus 1 from the output of register 451 timed by a clock signal delivered in a lead 422 and including (k+1)e pulses having the same frequency as that of clock signal 43 and starting one clock period after signal rise at output 424 of flip-flop 422. The shift clock signal in lead 442 is delayed in a delay circuit 453 by a value .delta. of positioning time of one stage in register 451 and is transmitted in a digital line 11 in bus 1 in sychronism with the (k+1)e bits of the packet transmitted in line 10. Signals in leads 441, 440 and 442 and in line 10 are shown on last four lines in FIG. 7.
When comparator 413 has detected an identifier E.sub.i in line 60 and the bottom of waiting store 400 contains a number of e-bit words less then k, no signal triggering off timer 44 is delivered from output 424 of third flip-flop 422. This condition is due for example to a period of momentary non-transmission of data from source 2.sub.i into line 70 or, generally speaking, to an asynchronism between the transmission of identifiers E.sub.i in line 60 and the appearance of ke bits in buffer 400. Between the detection of the previous identifier E.sub.i not triggering off the timer and the detection of the next identifier E.sub.i in line 60, the level of ke bits in buffer 400 can be exceeded. The capacity of the FIFO buffer must therefore be greater than ke=b bits.
Should the access authorizations to bus 1, i.e. the identifiers E.sub.i, be transmitted into bus 6 in a strictly periodic manner, and the number of identifiers E.sub.i per frame T by strictly equal to d.sub.i /d.sub.m, as indicated by identifiers E.sub.i in the frames in FIG. 2, a constant phase-shift exists between the positive comparisons in comparator 413 and the storage of ke bits in buffer 400. At the worst, the phase-shift can be equal in length to one package. The capacity of FIFO buffer 400 is therefore at least equal to 2b=2ke bits. In practice, the capacity of waiting store 400 is chosen as greater than 2b bits in order to relax the making-up of the frame and, in particular, to allow non-periodic identifier distribution within the frame, as indicated by identifier E.sub.i+3 in the frames in FIG. 2.
The asynchronous digital time-division multiplexing system with distributed bus as in the invention is destined notably for a company local network or a subscriber installation local network to be linked to an integrated service digital network via concentrator 3. Each source consists of data transmitting means included in a local network terminal. The bit rate in each source can be:
equal to a few kbit/s for facsimile data for example; or
between 64 kbit/s and 1 Mbit/s for medium or high frequency audio digital transmission; or
on the order of 100 Mbit/s for moving picture transmission.
By way of a particular embodiment, the values of the parameters defined in the foregoing description are:
length L=x.sub.I -x.sub.l =50 meters;
real bit rate D in bus 1=250 Mbit/s;
propagation time per length unity .tau. in buses 1 and 6=5ns/m;
number e of bits per identifier=8 bits;
number of bits ke per package:
number of bits per packet:
allocation time .theta.=1 .mu.s;
number N of time slots IT in a frame:
maximum source bit rate d.sub.M =b/.theta.=120 Mbit/s;
minimum source bit rate d.sub.m =b/(N.theta.)=14.6 kbit/s.
Claims
What we claim is:
1. An asynchronous digital time-division multiplexing system, comprising (a) plural data sources each having active and inactive states and being identified by respective identifiers, each active source supplying data bits with a corresponding bit rate, and said corresponding bit rates of said active sources being different therebetween; (b) plural access means associated with said data sources, respectively, for linking each associated data source to an identifier bus and to a packet bus, each access means transmitting a packet into said packet bus in response to each identifier of said associated data source detected on said identifier bus, and each transmitted packet consisting of said identifier and a group of data bits delivered by said associated data source; and (c) allocating means linked to said identifier bus for constituting identifier frames and transmitting said frames into said identifier bus; and wherein (d) each said identifier frame has a determined length and is composed of said identifiers corresponding to said active sources; and (e) each identifier is repeated in said identifier frame a number of times approximately proportional to said bit rate of said active source corresponding to said identifier.
2. The system defined in claim 1, wherein said data sources have bit rates between a minimum bit rate d.sub.m and a maximum bit rate N.d.sub.m less than a predetermined bit rate D of said packet bus, where N is an integer, each identifier frame has a length equal to b/d.sub.m and is split into N time slots, where b is a number of bits of said data bit group, each time slot has a period equal to b/(N.d.sub.m) and includes one identifier, and further wherein each identifier has a bit rate d.sub.i and is repeated in said frame n.sub.i times such that n.sub.i =d.sub.i /d.sub.m and n.sub.i =l+(integer part of (d.sub.i /d.sub.m)) when d.sub.i /d.sub.m is equal to and different from an integer, respectively.
3. The system defined in claim 2, wherein said length of each frame time slot is equal to (e+b)/D increased by an amount equal to twice a bit propagation time in said identifier and packet buses between one of said access means nearest said allocating means and one of said access means farthest from said allocating means, where e is a number of bits of said identifier.
4. The system defined in claim 2, wherein said access means associated with said respective data source comprises means for detection said data source identifier in said identifier bus, means for assembling said data bits supplied progressively from said data source into said data bit groups, means for detecting each of said assembled data bit groups to deliver a triggering signal in response to each detected data source identifier following said data bit group assembly, and means for transmitting a packet made up of said data source identifier and said assembled data bit group into said packet bus in response to said triggering signal.
5. The system claimed in claim 4, wherein said assembling means in said access means comprises a first-in first-out (FIFO) buffer having a capacity equal at least to 2b bits.
6. An asynchronous digital time-division multiplexing system, comprising (a) plural data sources each having active and inactive states and being identified by respective identifiers, each active source supplying data bits with a corresponding bit rate, and said corresponding bit rates of said active sources being different therebetween; (b) plural access means associated with said data sources, respectively, for linking each associated data source to an identifier bus and to a packet bus, each access means transmitting a packet into said packet bus in response to each identifier of said associated data source detected on said identifier bus, and each transmitted packet consisting of said identifier and a group of data bits delivered by said associated data source; and (c) allocating means, linked to said identifier bus for constituting identifier frames and transmitting said frames into said identifier bus, each identifier having a determined length and being composed of said identifiers corresponding to said active sources; and wherein (d) said data sources have bit rates between a minimum rate d.sub.m and a maximum bit rate N.d.sub.m less than a predetermined bit rate D of said packet bus, where N is an integer, each identifier frame has a length equal to b/d.sub.m and is split into N time slots, where b is a number of bits of said data bit group, each time slot has a period equal to b/(N.d.sub.m) and includes one identifier, and further wherein each identifier has a bit rate d.sub.i and is repeated in said frame n.sub.i times such that n.sub.i =d.sub.i /d.sub.m and n.sub.i =1+(integer part of (d.sub.i /d.sub.m)) when d.sub.i /d.sub.m is equal to and different from an integer, respectively; and (e) said allocating means comprises means for storing identifiers in N memory-cells to constitute one frame, means for systematically providing N cell addresses to read said stored identifiers during first half-periods of said time slots in said frame, thereby to insert said read identifiers in said second bus during second half-periods of said frame time slots, respectively, and means for selectively providing an identifier writing address during one of the second half-periods of said frame time slots to write said identifier in said storing means during the second half-period of a following time slot.
7. The system defined in claim 6, wherein said length of each frame time slot is equal to (e+b)/D increased by an amount equal to twice a bit propagation time in said identifier and packet buses between one of said access means nearest said allocating means and one of said access means farthest from said allocating means, where e is a number of bits of said identifier.
8. The system defined in claim 6, wherein said access means associated with said respective data source comprises means for detecting said data source identifier in said identifier bus, means for assembling said data bits supplied progressively from said data source into said data bit groups, means for detecting each of said assembled data bit groups to deliver a triggering signal in response to each detected data source identifier following said data bit group assembly, and means for transmitting a packet made up of said data source identifier and said assembled data bit group into said packet bus in response to said triggering signal.
9. The system claimed in claim 8, wherein said assembling means in said access means comprises a first-in first-out (FIFO) buffer having a capacity equal at least to 2b bits.
10. The system claimed in 6, wherein said identifier bus further comprises a digital transmission line for transmiting pulses synchronous with said frame identifiers inserted during said second half-periods of said time slots and provided from said N-reading address providing means.