Digital Delay Unit With Interleaved Memory

1. Field of the Invention

The present invention relates to a digital delay unit, and more particularly, it relates to a digital delay unit for processing, e.g., video signals in a digital television receiver.

2. Description of the Prior Art

Generally employed as a mass storage digital delay means is the so-called digital delay unit for sequentially writing/reading signals in/from memory cells arrayed in the form of a matrix to arbitrarily delay the signals. FIG. 1 is a block diagram showing an example of a conventional digital delay unit. In FIG. 1, an input terminal 1 receives basic clock pulses .phi..sub.S. The unit delay (minimum delay width) in the digital delay unit is equal to one cycle of the basic clock pulses .phi..sub.S. The basic clock pulses .phi..sub.S inputted from the input terminal 1 are supplied to an address counter 2. The address counter 2 is incremented on the leading edges of the basic clock pulses .phi..sub.S, to output X addresses to an X decoder 3 and Y addresses to a Y decoder 4. Outputs from the X decoder 3 are supplied to a memory cell array 5 while those from the Y decoder 4 are supplied to a transfer gate 6.

On the other hand, input terminals 13.sub.1 to 13.sub.n are adapted to receive input data synchronously inputted with the basic clock pulses .phi..sub.S, and are described herein in structure for receiving n-bit input data. The most significant bit (MSB) of the input data is supplied to the terminal 13.sub.1 while the least significant bit (LSB) is supplied to the terminal 13.sub.n. The inupt data are supplied to a write circuit 10 which is controlled by signals WE through an input latch 11. The memory cell array 5 is formed by a group of memory cells arrayed in the form of a matrix, and the storage capacity thereof is M.times.n bits. The transfer gate 6 transfers data read from the memory cell array 5 to a sense amplifier 7 while transferring data from the write circuit 10 to the memory cell array 5. The sense amplifier 7 is controlled by signals SE to amplify the read data. A data latch 8 temporarily stores outputs from the sense amplifier 7. During a period of time when the signals SE are at low levels, the data latch 8 is electrically cut off from the sense amplifier 7. An output latch 9 generates delayed outputs from the data latch 8 in the cycle of the basic clock pulses .phi..sub.S, to supply the same to output terminals 12.sub.1 to 12.sub.n. The MSB of the output data is outputted from the terminal 12.sub.1 while the LSB is outputted from the terminal 12.sub.n.

The basic clock pulses .phi..sub.S received through the input terminal 1 are further supplied to a timing generator 14, which in turn generates the aforementioned signals SE and WE in such timing sequence as shown in FIG. 2. The signals SE are adapted to drive the sense amplifier 7 in high-level periods thereof while the signals WE are adapted to drive the write circuit 10 in high-level periods thereof. The address counter 2 is reset per M cycles by a reset circuit (not shown). The conventional digital delay unit is in the aforementioned structure.

The PAL system television receiver, implemented by the structure as shown in FIG. 1 is a one-line memory for sampling analog video signals at the frequency of 4 f.sub.sc (f.sub.sc : chrominance subcarrier frequency) to generate digital video signals and delay the same by one scanning line (lH) on the following conditions: M=1135, n=8, X addresses=X.sub.0 to X.sub.7, Y addresses=Y.sub.0 to Y.sub.2, and one cycle of the basic clock pulses .phi..sub.S is equal to 56 ns.

Operation of the conventional digital delay unit as shown in FIG. 1 is now described with reference to a timing chart as shown in FIG. 2. In this case, delay of M cycles is obtained by an M.times.n-bit memory having an address space for addresses A.sub.1 to A.sub.M for processing n-bit data in a parallel manner. The memory cell array 5 employed in this digital delay unit is formed by n memory cell groups having M-bit address capacity, and one memory cell in each group corresponds to one address. Therefore, when an address is designated, n memory cells in total are accessed from the n memory cell groups in a parallel manner. In a memory of the so-called byte structure, the number n is equal to 8. In the following description, symbols D.sub.1 to D.sub.M indicate input data newly stored in the addresses A.sub.1 to A.sub.M respectively and symbols PD.sub.1 to PD.sub.M indicate output data read from the addresses A.sub.1 to A.sub.M respectively.

First, the address counter 2 is driven by the basic clock pulses .phi..sub.S to supply X addresses to the X decoder 3 and Y addresses to the Y decoder 4. Then outputted to an I/O line 17 are data of n-bit memory cells in total belonging to columns coupled to the transfer gate 6 selected by the Y decoder 4 within the memory cells belonging to rows selected by the X decoder 3 in the memory cell array 5. For example, when the address A.sub.1 is designated by the output from the address counter 2, data PD.sub.1 on n memory cells in total positioned in respective addresses A.sub.1 of the n memory cell groups are read in parallel through the transfer gate 6. The n-bit data PD.sub.1 thus read are amplified by the sense amplifier 7 in a high-level period of the signal SE, to be fetched in the data latch 8. The data latch 8 is electrically cut off from the sense amplifier 7 on the trailing edge of the signal SE, thereby to hold the read data PD.sub.1 for the low-level period of the signal SE. The read data PD.sub.1 are transferred to the output latch 9, to be outputted from the n output terminals 12.sub.1 to 12.sub.n in a parallel manner. Thus, the data are sequentially read in correspondence to change of the address signals per one cycle of the basic clock pulses .phi..sub.S as shown in FIG. 2.

In the same address designating period after the fall of the signal SE, the write circuit 10 is driven in a high-level period of the signal WE to transfer n-bit input data received from an input latch 11 to the I/O line 17 to reload the data on the currently selected memory cells. For example, immediately after the preceding data PD.sub.1 are read from the address A.sub.1 to be stored in the data latch 8, new data D.sub.1 are written in the memory cells of the address A.sub.1. The data D.sub.l are read when the address A.sub.1 is again designated after M cycles. Thus, read-modified-write operation is performed every M cycles for the memory cells of the respective addresses so that newly written data are outputted after M cycles, thereby to obtain delay of M cycles.

In the conventional digital delay unit, read/write operation must be performed within one cycle of the basic clock pulses .phi..sub.S as hereinabove described. Therefore, the cycle of the basic clock pulses .phi..sub.S must be determined in consideration of read access time to data latch, writing completion time (pulse width of the signals WE), pulse width of the signals SE, timing margins between the address signals and the like, and it has been difficult to attain high-speed operation. For example, a cycle time of 56 ns is required for a digital delay unit applied to a PAL system television receiver, and if the aforementioned structure is employed in conventional process technique, the read-modified-write operation must be performed within the period of 56 ns. Thus, it has been difficult to drive the digital delay unit with sufficient timing margins.

An example of the aforementioned type prior art is disclosed in, e.g., "Television Gakkaishi (The journal of the institute of television engineers of Japan)" Vol. 39, No. 3 (1985) pp. 250 to 252. In this prior art literature, examples as shown in FIGS. 6 and 7 are at low speeds while an example as shown in FIG. 8 is at a high speed whereas the memory capacity is doubled, leading to increase in cost.

An object of the present invention is to provide a digital delay unit which can operate at a higher speed than the conventional digital delay unit through use of conventional process technique, without increasing the cost.

Briefly stated, the present invention provides a digital delay unit comprising a memory cell group arrayed in the form of a matrix divided into two address spaces which are alternately accessed so that data read from the two address spaces are alternately outputted at the clock rate of basic clock pulses and input data received synchronously with the basic clock pulses are alternately written in the two address spaces.

According to the present invention, the respective address spaces are driven substantially at the clock rate for two cycles of the basic clock pulses while data input/output operation is completed virtually in the same cycle as that of the basic clock pulses, whereby the digital delay unit can be driven at a high speed at the clock rate half the minimum operational cycle of each address space while maintaining sufficient timing margins. Thus, there is no need to increase the memory capacity, to effectively prevent increase in cost.

These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.

FIG. l is a block diagram showing an example of a conventional digtal delay unit;

FIG. 2 is a timing chart for illustrating operation of the conventional digital delay unit as shown in FIG. 1;

FIG. 3 is a block diagram showing an embodiment of the present invention;

FIG. 4 is a timing chart for illustrating operation of the embodiment as shown in FIG. 3;

FIG. 5 is a block diagram showing another embodiment of the present invention;

FIG. 6 is a circuit diagram showing an example of a delay latch circuit as shown in FIG. 5; and

FIG. 7 is a timing chart for illustrating operation of the embodiment as shown in FIG. 5.

FIG. 3 is a block diagram showing an embodiment of the present invention. In FIG. 3, a digital delay unit according to the present invention is adapted to delay n-bit input data by M cycles to output the same, and its address space corresponding to the delay amount is divided into two memory cell arrays. A first memory cell array 84 forms an even address plane and a second memory cell array 94 forms an odd address plane, and the memory capacity of each memory cell array is (M/2).times.n bits. Input terminals 90.sub.1 to 90.sub.n are adapted to receive n-bit input data at the clock rate of basic clock pulses .phi..sub.S. The input data are supplied through an input latch 99 to write circuits 88 and 98.

A timing generator 101 receives the basic clock pulses .phi..sub.S from an input terminal 100 to generate various timing signals .phi..sub.EV, .phi..sub.OD, SE.sub.EV, SE.sub.OD, WE.sub.EV, WE.sub.OD, OE.sub.EV and OE.sub.OD on the basis of the basic clock pulses .phi..sub.S, in timing sequence as shown in FIG. 4. One cycle of the basic clock pulses .phi..sub.S is equivalent to the unit delay. The signals .phi..sub.EV are obtained by frequency division of the basic clock pulses .phi..sub.S to be doubled in cycle, and adapted to increment an address counter 81 on the trailing edges thereof. The signals .phi..sub.OD are formed by clocks antiphase to the signals .phi..sub.EV, and increment an address counter 91 on the trailing edges thereof. The signals SE.sub.EV and SE.sub.OD respectively control sense amplifiers 86 and 96 to drive the same in high-level periods thereof. The signals WE.sub.EV and WE.sub.OD respectively control the write circuits 88 and 98 to drive the same in high-level periods thereof. The signals OE.sub.EV control outputs of a data latch 87 while the signals OE.sub.OD control outputs of a data latch 97.

The address counter 81 receives the signals .phi..sub.EV to supply even X address signals to an X decoder 82 and even Y address signals to a Y decoder 83 in the cycle of the signals .phi..sub.EV (i.e., twice that of the basic clock pulses .phi..sub.S). Outputs from the X decoder 82 are supplied to the first memory cell array 84 while outputs from the Y decoder 83 are supplied to a transfer gate 85. In a similar manner, the address counter 91 receives the signals .phi..sub.OD to supply odd address signals to an X decoder 92 and odd Y address signals to a Y decoder 93 in the cycle of the signals .phi..sub.OD (i.e., twice that of the basic clock pulses .phi..sub.S). Outputs from the X decoder 92 are supplied to the second memory cell array 94 while outputs from the Y decoder 93 are supplied to a transfer gate 95. The transfer gate 85 supplies data read from the first memory cell array 84 to the sense amplifier 86 through an I/O line 102, while transferring data from the write circuit 88 received through the I/O line 102 to the first memory cell array 84. In a similar manner, the transfer gate 95 transfers data read from the second memory cell array 94 to the sense amplifier 96 through an I/O line 103, while transferring data from the write circuit 98 received through the I/O line 103 to the second memory cell array 94. The sense amplifier 86 is controlled by the signals SE.sub.EV to amplify the read data thereby to supply the same to the data latch 87, which in turn temporarily stores the outputs from the sense amplifier 86. When the signals SE.sub.EV are at low levels, the data latch 87 is electrically cut off from the sense amplifier 86. Data from the data latch 87 are transferred to the output latch 89 when the signals OE.sub.EV are at high levels. In a similar manner, the sense amplifier 96 is controlled by the signals SE.sub.OD to amplify the read data thereby to supply the same to the data latch 97, which in turn temporarily stores the outputs from the sense amplifier 96. When the signals SE.sub.OD are at low levels, the data latch 97 is electrically cut off from the sense amplifier 96. Further, data from the data latch 97 are transferred to the output latch 89 during when the signals OE.sub.OD are at high levels. The output latch 89 outputs the data delayed by M cycles synchronously with the basic clock pulses .phi..sub.S, to supply the same to output terminals 80.sub.1 to 80.sub.n. The address counters 81 and 91 are respectively provided with reset circuits (not shown), to be reset every M cycles.

FIG. 4 is a timing chart for illustrating operation of the embodiment as shown in FIG. 3. With reference to FIG. 4, description is now made on the operation of the embodiment as shown in FIG. 3. In the following description, symbols D.sub.1 to D.sub.M respectively indicate input data received through input terminals 90.sub.1 to 90.sub.n to be newly stored in respective addresses A.sub.1 to A.sub.M of the memory cell arrays 84 and 94 and symbols PD.sub.1 to PD.sub.M respectively indicate output data read from the respective addresses A.sub.1 to A.sub.M.

The timing generator 101 generates the signals .phi..sub.EV and the signals .phi..sub.OD antiphase thereto by dividing the basic clock pulses .phi..sub.S. The address counter 81 is driven by the signals .phi..sub.EV to generate even address signals Ad.sub.ev in a cycle twice that of the basic clock pulses .phi..sub.S, to output even X address signals to the X decoder 82 and even Y address signals to the Y decoder 83. On the other hand, the address counter 91 is driven by the signals .phi..sub.OD to generate odd address signals Ad.sub.OD twice the basic clock pulses .phi..sub.S in cycle, to output odd X address signals to the X decoder 92 and odd Y address signals to the Y decoder 93. It is to be noted here that the even address signals Ad.sub.EV are phase-shifted from the odd address signals Ad.sub.OD respectively by one cycle of the basic clock pulses .phi..sub.S.

Assuming that the output of the address counter 81 designates the address A.sub.2 in the first memory cell array 84, n memory cells positioned in the address A.sub.2 are accessed by the X and Y decoders 82 and 83, so that n-bit data PD.sub.2 already stored (M-1) cycles ahead are read on the I/O line 102 through the transfer gate 85. The data PD.sub.2 are amplified by the sense amplifier 86 in a high-level period of the signal SE.sub.EV, to be fetched in the data latch 87. The data latch 87 is electrically cut off from the sense amplifier 86 on the trailing edge of the signal SE.sub.EV, thereby to hold the read data PD.sub.2 in the low-level period of the signal SE.sub.EV. The data PD.sub.2 held in the data latch 87 are transferred to the output latch 89 in a high-level period of the signal OE.sub.EV, to be outputted from n output terminals 80.sub.1 to 80.sub.n. On the other hand, the write circuit 88 operates in a high-level period of the signal WE.sub.EV to write new n-bit data D.sub.2 received through the input terminals 90.sub.1 to 90.sub.n to be stored in an input latch 99 in the memory cells of the same address A.sub.2. Thus completed is read-modified-write operation (the series operational period is hereinafter referred to "address cycle") for the address A.sub.2.

In the second memory cell array 94, an address cycle for the address A.sub.3 starts after the lapse of one cycle of the basic clock pulses .phi..sub.S from the start of the address cycle for the address A.sub.2. The output from the address counter 91 designates the address A.sub.3 and n memory cells positioned in the address A.sub.3 are accessed by the X and Y decoders 92 and 93, so that n-bit data PD.sub.3 already stored (M-1) cycles ahead are read on the I/O line 103 through the transfer gate 95. The data PD.sub.3 are amplified by the sense amplifier 96 in a high-level period of the signal SE.sub.OD to be fetched in the data latch 97. The data latch 97 is electrically cut off from the sense amplifier 96 on the trailing edge of the signal SE.sub.OD, thereby to hold the read data PD.sub.3 in the low-level period of the signal SE.sub.OD. Then the signal OE.sub.OD is turned to a high level, whereby the data PD.sub.3 are transferred to the output latch 89 to be outputted from n output terminals 80.sub.1 to 80.sub.n. On the other hand, the write circuit 98 operates when the signal WE.sub.OD is at a high level to write new n-bit data D.sub.3 received through the input terminals 90.sub.1 to 90.sub.n to be stored in the input latch 99 in memory cells of the address A.sub.3. Thus, the address cycle for the address A.sub.3 is completed. After the lapse of one cycle of the basic clock pulses .phi..sub.S from the start of the address cycle for the address A.sub.3, an address cycle for the address A.sub.4 starts in the first memory cell array 84 to read new data PD.sub.4.

As hereinabove described, the input data received at the clock rate of the basic clock pulses .phi..sub.S are alternately written in the first and second memory cell arrays 84 and 94, while being alternately outputted from the output terminals 80.sub.1 to 80.sub.n in delay by M cycles of the basic clock pulses .phi..sub.S from the points of time the read data from the memory cell arrays 84 and 94 are received, at the clock rate of the basic clock pulses .phi..sub.S. Thus, the circuit as shown in FIG. 3 serves as a digital delay unit attaining delay of M cycles.

Although the signals OE.sub.EV and OE.sub.OD are employed for controlling the outputs of the data latches 87 and 97, they may be replaced by the signals .phi..sub.EV and .phi..sub.OD. Further, the signals WE.sub.EV and WE.sub.OD may be replaced by the signals SE.sub.OD and SE.sub.EV.

Although the signals SE.sub.EV are activated in the first half periods (each corresponding to one cycle of the basic clock pulses .phi..sub.S) of the address cycles for the even addresses and the signals WE.sub.EV are activated in the second half periods (each corresponding to one cycle of the basic clock pulses .phi..sub.S), both of the signals SE.sub.EV and WE.sub.EV may be activated in the second half periods of the even address cycles. The point is that the read-modified-write operation is completed within the address cycle for each even address. This also applies to the signals SE.sub.OD and WE.sub.OD in the address cycles for the odd addresses.

Further, although the two memory cell arrays having address spaces of the same storage capacity are accessed to obtain data delay even times the unit delay in the aforementioned embodiment, a means such as a single stage delay circuit (register) may be provided immediately in front or at the back of the output latch 89, in order to attain data delay of odd times.

In addition, the digital delay unit according to the present invention may be implemented by a static memory circuit or a dynamic memory circuit.

FIG. 5 is a block diagram showing another embodiment of the present invention. In FIG. 5, components identical to those of the embodiment as shown in FIG. 3 are indicated by the same reference numerals, and description thereof is omitted. In FIG. 5, a timing generator 104 receives basic clock pulses .phi..sub.S from an input terminal 100, to generate various timing signals .phi..sub.L, SE.sub.EV, SE.sub.OD, WE.sub.EV, WE.sub.OD, OE.sub.EV and OE.sub.OD on the basis of the basic clock pulses .phi..sub.S in timing sequence as shown in FIG. 7. The signals .phi..sub.L are obtained by frequency division of the basic clocks .phi..sub.S to be doubled in cycle and inputted in an address counter 81 and delay latch circuits 105 and 106.

The address counter 81 receives the signals .phi..sub.L to supply even X address signals to an X decoder 82 and even Y address signals to a Y decoder 83 in the cycle of the signals .phi..sub.L. Outputs from the X decoder 82 are supplied to a first memory cell array 84 and a delay latch circuit 106. Outputs from the Y decoder 83 are supplied to a transfer gate 85 and a delay latch circuit 105. Outputs from the delay latch circuit 106 are supplied to a second memory cell array 104 while those from the delay latch circuit 105 are supplied to a transfer gate 95.

The delay latch circuits 105 and 106 are formed by a plurality of parallel latches, which are controlled by the internal clock pulses .phi..sub.L. FIG. 6 shows an example of circuit structure of such a latch. The latch circuit as shown in FIG. 6 is implemented by a well-known CMOS static latch circuit, which is formed by inverters 109 and 110, an NMOS transfer gate 107 and a PMOS transfer gate 108. The inverters 109 and 110 are connected in series to each other so that the NMOS transfer gate 107 transfers outputs from the Y decoder 83 (or X decoder 82) to the inverter 109 and the PMOS transfer gate 108 bridges the input terminal of the inverter 109 and the output terminal of the inverter 110. The outputs of the inverter 110 are supplied to the transfer gate 95 (or memory cell array 94). Further, the transfer gates 107 and 108 receive the clock pulses .phi..sub.L at the gate electrodes thereof. Thus, the delay latch circuits 105 and 106 are formed by a plurality of static latches as shown in FIG. 6 arranged in parallel.

FIG. 7 is a timing chart for illustrating operation of the embodiment as shown in FIG. 5. With reference to FIG. 7, description is now made on the operation of this embodiment. In the following description, symbols D.sub.1 to D.sub.M respectively indicate n-bit input data received in an input latch 99 through input terminals 90.sub.1 to 90.sub.n to be newly stored in respective addresses A.sub.1 to A.sub.M, and symbols PD.sub.1 to PD.sub.M respectively indicate output data read from the respective addresses A.sub.1 to A.sub.M. First, the basic clock pulses .phi..sub.S are divided so that the timing generator 104 generates the internal clock pulses .phi..sub.L. On the trailing edges of the internal clock pulses .phi..sub.L, the address counter 81 is incremented to generate even address signals Ad.sub.EV (see FIG. 7) twice the basic clock pulses .phi..sub.S in cycle thereby to supply even X address signals to the X decoder 82 and even Y address signals to the Y decoder 83. Thus, selected in even address cycles are memory cells in the first memory cell array 84 forming an even address plane by the outputs from the X and Y decoders 82 and 83.

The latch (see FIG. 6) forming the delay latch circuit 106 fetches the outputs from the X decoder 82 on the leading edges of the clock pulses .phi..sub.L, and hence the delay latch circuit 106 delays the outputs from the X decoder 82 respectively by one cycle of the basic clock pulses .phi..sub.S to transfer the same to the second memory cell array 94. Since the latch as shown in FIG. 6 is well known in the art and the operation thereof would be easily understood by those skilled in the art, detailed description is omitted. In a similar manner, the delay latch circuit 105 delays the outputs from the Y decoder 83 respectively by one cycle of the basic clock pulses .phi..sub.S to transmit the same to the transfer gate 95. Thus, selected are memory cells in the second memory cell array 65 forming an odd address plane by the outputs from the delay latch circuits 105 and 106. It is to be noted that odd address cycles are always delayed from the even address cycles respectively by one cycle of the basic clock pulses .phi..sub.S. Thus, this embodiment is equivalent in operation to that shown in FIG. 3.

Although the address counter 81 generates the even address signals to be delayed by the delay latch circuits 105 and 106 thereby to obtain the odd address signals in the embodiment as shown in FIG. 5, the address counter 81 may generate odd address signals, to delay the same respectively by one cycle of the basic clock pulses .phi..sub.S thereby to obtain even address signals.

Further, although the outputs of the data latches 87 and 97 are controlled by the signals OE.sub.EV and OE.sub.OD, they may in place be controlled by the clock pulses .phi..sub.L and inverted signals thereof.

According to the aforementioned embodiment as shown in FIG. 5, the address signals are generated to access the memory cells of either the first or second memory cell array to obtain the address signals for accessing the memory cells of the other memory cell array by delaying the said address signals respectively by one cycle of the basic clock pulses .phi..sub.S, and hence two types of address signals can be obtained by only one address signal generator means, whereby the circuit structure is simplified in comparison with that of the embodiment as shown in FIG. 3.

Although the present invention has been described and illustrated in detail, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the spirit and scope of the present invention being limited only by the terms of the appended claims.