Integrated Dual-Slope Analog to Digital Converter With R/C Variance Compensation

This invention pertains in general to analog-to-digital converters, and more particularly to an integrated dual-slope analog-to-digital converter.

Analog-to-digital (A/D) converters operate to produce a numerical representation of an input voltage. One class of A/D converters is known as "dual-slope" A/D converters. Typically, a dual-slope A/D converter integrates the input voltage from a predetermined starting voltage level to a peak voltage level over a predetermined time period, and deintegrates a reference voltage from the peak voltage level back to the starting voltage level. Conversely, a dual-slope A/D converter may integrate a reference voltage over a predetermined time period and deintegrate the input voltage. The time required for disintegration is compared to the predetermined time-period to determine the ratio of the reference voltage to the input voltage.

Dual-slope analog-to-digital converters are sold in high volumes for use in digital panel meters, voltage meters, and other instrumentation and control applications. Since they can be readily implemented in either bipolar or MOS technology and are capable of resolution well beyond fifteen bits, they have become the industry's standard for a low-speed, high precision A/D conversion. For maximum resolution and reliability, it is desirable to set the peak voltage level corresponding to the maximum allowable input voltage to an optimum level. Unfortunately, previously developed dual-slope A/D converters require a precision resistor and capacitor which cannot be accurately implemented onto an integrated circuit along with the rest of the A/D circuitry.

Variations in the resistive and capacitive values affect the rate of integration, and hence, adversely affect the peak voltage level obtained during integration. Using an external resister and capacitor also presents several problems including additional costs, size, parasitic leakage, noise injection and temperature-related variations. These problems reduce the ability of dual-slope A/D converters to compete with "successive approximation" A/D converters in low resolution (less than ten bits) applications and result in high system costs and poorer performance in high precision applications where dual-slope A/D converters are the only available choice.

Therefore, a need exists in the industry for a dual-slope A/D converter which can be integrated on single chip without reduction in accuracy due to the inherent variance in resistor and capacitor values caused by the manufacturing process.

The present invention disclosed and claimed herein describes a method and apparatus for performing a dual-slope analog-to-digital conversion on an integrated chip which substantially eliminates problems associated with prior dual-slope analog-to-digital converters.

In one aspect of the present invention, a dual slope analog-to-digital converter has an oscillator for generating timing information and an integrator for integrating an input voltage over a predetermined number of oscillations. The oscillator is designed such that its frequency varies proportionally to the rate of integration, thereby offsetting a rate of integration deviating from a desired value. An advantage associated with this aspect of the invention is that a stable peak integration level is maintained despite inaccuracies in the actual rate of integration, or the actual rate of oscillation. Another advantage is that temperature effects on the integrator are similarly offset.

In another aspect of the invention, a fully integrated dual-slope analog-to-digital converter has an input to receive an analog voltage for conversion to a numerical value of the voltage, an oscillator for generating timing information, and an integrator for integrating the input voltage over a predetermined time interval and integrating a reference voltage over a measured time interval. The oscillator generates the timing information at a rate inversely proportional to the RC time constant determined by multiplying the values of the oscillator's resistor and capacitor. The rate of integration is inversely proportional to the integrator's resistor and capacitor. By manufacturing the integrator's resistor substantially simultaneously and in close proximity with the oscillator's resistor and manufacturing the integrator's capacitor in close proximity with the oscillator's capacitor, the proportional variations in the values of the resistive and capacitive elements from their desired value can be made substantially identical in both the integrator and the oscillator. This aspect of the invention has the advantage that an optimum peak voltage level for a full scale input voltage can be achieved despite substantial variations in the values of the resistive and capacitive values from designed levels. Because all the critical leakage nodes are internal to the integrated circuit, parasitic effects can be accounted for and controlled. Also, special cleaning and coating of the printed circuit boards is not necessary since the leakage nodes are internal.

For a more complete understanding of the present invention and the advantages thereof, reference is now made to the following description taken in conjunction with the accompanying Drawings in which:

FIG. 1 illustrates a dual-slope A/D converter;

FIG. 2 illustrates the integrator output of the circuit of FIG. 1;

FIG. 3 illustrates an oscillator circuit;

FIG. 4 is a top plan of the integrator and oscillator sections of an integrated dual-slope A/D converter; and

FIG. 5 is a cross-sectional view of the resistive and capacitive components of the integrated circuit of FIG. 4.

The preferred embodiment of the present invention is best understood by referring to FIGS. 1-5 of the drawings, like numerals being used for like and corresponding parts of the various drawings.

A circuit for implementing a dual-slope analog-to-digital converter 10 (hereinafter "A/D" 10) is illustrated in FIG. 1. An oscillator 12 having a resistor, R.sub.O 14, and a capacitor, C.sub.O 16, is connected to a control logic and counter section 18. The control logic and counter section 18 outputs a signal to a multiplexer 20 which has a input voltage 22 and a reference voltage 24 as inputs. The output of the multiplexer 20 is connected to an integrator 26 which has a resistor, R.sub.1 28 and a capacitor, C.sub.I 30. The output 31 of the integrator 26 is connected to the input of a comparator 32. The output of the comparator 32 is connected to the control logic and counter section 18.

The operation of the A/D 10 will be discussed in connection with the graph of FIG. 2. The comparator 32 outputs a signal when the voltage input to the comparator 32 from the integrator 26 equals a preset starting voltage 34. When the voltage at the output 31 of the integrator 26 equals the preset starting voltage 34, a signal, such as a logical 1, is output from the comparator 32 to the control logic and counter section 18. The integrator 26 integrates the voltage at its input over time. The rate of integration is determined by R.sub.I 28 and C.sub.I 30.

Initially, the output 31 of the integrator 26 is set to the preset starting level 34. In the preferred embodiment, the multiplexer 20 is set to allow the reference voltage 24 to pass to the input of the integrator 26. The reference voltage 24 is a negative voltage, causing a continuous reduction in the voltage present at the output 31 of the integrator 26. When the output 31 reaches the preset starting level 34, the comparator 32 outputs a signal to the control logic and counter section 18. This signifies that an initial condition has been reached and the analog-to-digital conversion may be begin.

It will be understood that the present invention also encompasses a variation using an "auto-zero" phase to set the output 31 to a present level. In this variation, the output of the comparator 32 is looped back to the input of the integrator 30 to reach the preset starting level 34.

After receiving the signal from the comparator 32, the control logic and counter section 18 outputs a signal to the multiplexer 20 indicating that the input voltage 22 should be passed to the integrator 26. Simultaneously, a counter in the control logic and counter section 18 begins counting oscillations output from the oscillator 12. The input voltage 22 is integrated over a predetermined number of oscillations. In the illustrated embodiment of FIG. 1, the time period associated with each oscillation is determined by the RC time constant associated with the particular values of R.sub.O 14 and C.sub.O 16 used in the oscillator 12; alternatively, some oscillators used a crystal to determine the time period of each oscillation. A predetermined time period, illustrated in FIG. 2 as T.sub.f 36, can be determined by multiplying the time period associated with each oscillation by the predetermined number of oscillations counted during the integration period.

Again referring to FIG. 2, the integration of the input voltage is illustrated. Beginning at starting point 38 (i.e., the time at which the initial preset voltage 34 is reached), the input voltage 22 is integrated over the fixed time, T.sub.f 36. By the end of T.sub.f 36, the output 31 of the integrator 26 has reached a value of V.sub.peak 40. Assuming a fixed oscillation rate, and a fixed rate of integration, V.sub.peak will vary proportionally with the input voltage 22.

Once the predetermined number of oscillations have been counted, the control logic and counter section 18 reverses the signal to the multiplexer 20, resulting in the reference voltage 24 being passed to the input of the integrator 26. The reference voltage 24 is integrated until the preset starting voltage 34 is reached. During integration, the number of oscillations are counted, rendering the time needed to "deintegrate" V.sub.peak 40. This measured time period is indicated as T.sub.m 42. When the initial preset voltage 34 is reached, the comparator 32 will output a signal to the control logic and counter section 18 indicating that the output 31 is equal to the preset voltage.

Although the illustrated embodiment shows a dual-slope A/D with a single reference voltage, it may be desirable to have both positive and negative reference voltages; the negative reference voltage being used for deintegrating positive input voltages, and the positive reference voltage being used to deintegrate negative input voltages. The polarity of the input signal may be determined by use of a comparator after integration of the input signal.

The level of the input voltage 22 may be determined by the following equation:

Equivalently, the input voltage 22 can be determined using the number of oscillations counted during integration by the following equation:

where N.sub.f equals the predetermined number of oscillations counted during integration of the input voltage and N.sub.m equals the number of oscillations counted during integration of the reference voltage.

Hence, it would appear from equation (2) that a dual-slope A/D converter can determine the input voltage 22 independently of the rate of integration or the time period associated with the oscillations. However, to provide the maximum resolution, it is important the V.sub.peak approximate an optimum value at the maximum allowable input voltage 22 (hereinafter "full scale input"). If V.sub.peak substantially exceeds the ideal voltage at a full scale input, then the output 31 of the integrator 26 will saturate prior to reaching the actual value of V.sub.peak, resulting in an errant calculation of the input voltage 22. On the other hand, if V.sub.peak 40 is substantially below the ideal voltage at full scale input, then the incremental voltage associated with the number of bits of resolution will be smaller than the optimum incremental voltage. If the incremental voltage is too small, input noise to the integrator 26 and comparator 32 will affect the readings, particularly at low input voltages 22. Also, power supply feedthrough noise, such as inductive voltage spikes at the power supply and ground pins, may cause inconsistent readings at low incremental voltages. Therefore, it is desirable to stabilize V.sub.peak at or close to an ideal peak voltage. The ideal peak voltage at full scale input (hereinafter "V.sub.peakman ") will depend on the technology used to implement the A/D converter, but should be set within a few hundred millivolts of the positive supply rail in order to optimize the A/D's noise immunity. Also, it is important that V.sub.peakmax remain stable over temperature variations.

Thus, the oscillation time period and the rate of integration must be coordinated such that an ideal V.sub.peakmax is obtained at full scale input. To a certain extent, different rates of oscillation and rates of integration may be used to achieve an ideal V.sub.peakmax. For example, a longer oscillation period may be compensated for a slower rate of integration. Also, the number of oscillations counted during the T.sub.f period 36 may be varied, to accommodate a certain rate of oscillation. However, a longer T.sub.f period 36 will result in a slower response time, while a reduction of the number of oscillations counted during the T.sub.f period 36 will result in less accuracy in calculating the value of the input voltage 22.

Once the rate of integration and the rate of oscillation have been decided upon, a resistor and capacitor combination for both the oscillator 12 and the integrator 26 must be determined to implement the desired rates. Once the values of R.sub.O 14, C.sub.O 16, R.sub.I 28 and C.sub.I 30 have been determined, it is important that the resistive and capacitive values used in the circuit match the desired values; otherwise, the rate of integration in/or the rate of oscillation may affect the desired value of V.sub.peakmax.

The need for precise accuracy in implementing resistive and capacitive values in the A/D converter 10 has heretofore prevented integration of these components along with the rest of the A/D circuitry. While oxide and oxide/nitride capacitors provide a high quality capacitor, and polysilicon and thin-film resistors provide high quality resistors, the accuracy with which the resistive and capacitive values can be controlled in manufacturing is relatively poor. Typical ranges of parameter variation may vary from 15-35 percent from the predetermined desired values.

Assuming that T.sub.f can be accurately controlled, the V.sub.peakmax can be shown to be proportional to the reciprocal of the R.sub.I C.sub.I product by the following equation:

Using values typical in the industry, the R.sub.I C.sub.I product can vary from -40% to +80%. Hence, V.sub.peakmax will also vary by -40% to +80%. If no trimming of the A/D is allowed after manufacturing, the nominal design value for V.sub.peakmax will have to be set at around 50% of the optimal value, resulting in worst-case units set at approximately 80% below the optimal design level. Consequently, this variation will cost 2-3 bits of converter precision, making the fully integrated dual-slope A/D essentially unrealizable for high precision instrumentation applications. Furthermore, is such a converter was constructed, its performance would vary widely from one manufacturing lot to the next. This would be objectionable at any resolution level.

Referring now to FIG. 3, the preferred embodiment for an oscillator circuit 44 is illustrated. By implementing the oscillator circuit 44 in conjunction with the other components of the A/D 10 on an integrated chip, an A/D converter which is essentially immune to variations in the accuracy of the resistive and capacitive elements can be obtained.

The oscillator 44 has a first supply voltage 46 and a second supply voltage 48 input to a first comparator 50 and a second comparator 52, respectively. The inputs 50a and 52a of the comparators 50 and 52 are connected to a node 53 between the resistor R.sub.O 14 and capacitor C.sub.O 16. The output of the first comparator 50 is connected to the "reset" input of an RS flip-flop 54 and the output of the second comparator 52 is connected to the "set" input of the RS flip-flop 54. The output of the RS flip-flop is connected to a first inverter 56. The output of the first inverter 56 is connected to the input of the second inverter 58. The output of the second inverter 58 is connected to one end of the resistor R.sub.O 14. The other end of the resistor R.sub.O 14 is connected to the node 53, which is also connected to one plate of the capacitor C.sub.O 16. The other plate of the capacitor C.sub.O 16 is connected to ground.

In operation, the first supply voltage 46 is set to a value higher than the second supply voltage 48. Assuming an initial output voltage at the node 53, the second comparator 52 is tripped, setting the RS flip-flop 54, i.e., causing a high output of the RS flip-flop 54. After propagating through the two inverters 56 and 58, a high signal will appear at R.sub.O 14, thus charging the capacitor C.sub.O 16. The voltage at the node 53 will continue to increase until it reaches a value equal to the first supply voltage 46 at which time the first comparator 50 will trip, thus resetting the RS flip-flop 54. With the output of the RS flip-flop 54 at a low signal, the voltage at the node 53 will decrease until such time that the voltage at the node 53 is equal to the second supply voltage 48, which will cause the cycle to repeat. Hence, the node 53 will oscillate in voltage at a rate determined by R.sub.O 14 and C.sub.O 16.

In the preferred embodiment, the first and second supply voltages 46 and 48 are derived from the power supply through a resistive divider. For example, the first and second supply voltages 46 and 48 could be set at two-thirds of the power supply voltage and one-third of the power supply voltage respectively. This embodiment has the advantage that the oscillation frequency becomes independent of the power supply voltage.

An advantage of the oscillator circuit 44 is that it can be implemented on an integrated circuit such that the frequency of the oscillator will compensate for a deviation in the rate of integration due to varying resistive and capacitive values. Since T.sub.f =(a)(R.sub.O C.sub.O), where (a) is a constant, equation (3) can be rewritten as:

V.sub.peakmax =(a) (R.sub.O C.sub.O).times.full scale input.times.(1R.sub.I C.sub.I)= (a).times.full scale input.times.(R.sub.O /R.sub.I) (C.sub.O /C.sub.I) (4)

Since (a) and the full scale input are constants, V.sub.peakmax can be controlled by maintaining a constant ratio of R.sub.O to R.sub.I and a constant ratio of C.sub.O to C.sub.I. In other words, R.sub.I can vary from an ideal value so long as R.sub.O varies in the same proportion. Similarly, C.sub.I can vary from the ideal, if C.sub.O varies accordingly. Using this technique, V.sub.peakmax can be stabilized to within a few percent of its optimum level, thus allowing for consistent, high performance of the A/D 10.

In the preferred embodiment, a relaxation type oscillator, such as illustrated in FIG. 3, is used. However, other types of oscillators, such as phase shift oscillators, may also be used, so long as the frequency of the oscillator varies inversely with the RC time constant.

Referring now to FIG. 4, a top plan of the integrated circuit is illustrated which allows the resistors and capacitors of the integrator and oscillator to maintain predetermined ratios despite manufacturing inaccuracies. The integrated circuit 60 has its input electronics 62 (including the multiplexer 20, the reference voltage source 24 and the input electronics for the input voltage 22) connected to one end of an integrator resistor 64 corresponding to the integrator resistor R.sub.I 28. The other end of the integrator resistor 64 is connected to one input of the integrator amplifier 66 and to the top plate 68b of the integrator capacitor 68. The other input of the integrator amplifier 66 is connected to the analog common. The output of the integrator amplifier 66 is connected to the bottom plate 68a of the integrator capacitor 68 and to one input of the comparator 32. With regards to implementation of the oscillator 12, an oscillator resistor 70 and an oscillator capacitor 72 having bottom and top plates 72a and b and are connected to the oscillator active circuitry 74. The output of oscillator active circuitry 74 is connected to the control logic and counter section 18.

In the preferred embodiment, implanted polysilicon resistors are used to implement the integrator and oscillator resistors 64 and 70. In this embodiment a polysilicon layer is formed and implanted to reduce its sheet resistance. In another embodiment, thin film technology could be used to implement the resistors. Less preferably, diffused resistors could be used.

In the illustrated embodiment, serpentine resistors are used. Alternatively, the polysilicon can be formed in stripes and interconnected by metal contacts to create a resistive path.

In processing integrated circuits, the sheet resistance of a polysilicon resistor depends primarily on its implant dose and implant energy. By placing two resistors closely together on an integrated circuit, the implant dose and implant energy will be the same for both resistors. Thus, the resistor ratio is set by physically forming one resistor longer than the other. For example, if on a given chip, the integrator resistor is 25% high, then the oscillator resistor will also be approximately 25% high as well. Thus, on a given chip, if the integrating resistor 64 is in close proximity to the oscillator resistor 70, the ratio of the resistor values will vary within a few percent of the ideal resistor ratio value and will not significantly affect the value of V.sub.peakmax. Although the particular resistive values of the integrator resistor 64 and the oscillator resistor 70 may vary widely from lot to lot, the ratio of the sheet resistance of the resistors will remain relatively constant.

In the preferred embodiment, a constant resistor ratio is further enhanced by orienting the resistors in the same direction, i.e., forming the resistor stripes in a parallel fashion. An advantage of this embodiment is that any direction component, such as implant strength, thickness, etching, or doping, remains the same for each resistor.

Also, in the preferred embodiment, the stripes of both resistors 64 and 70 have a uniform width, with the resistivity increased by lengthening the transistor. This embodiment has the advantage of decreasing etching bias.

Similarly, the capacitors are placed within closed proximity to each other such that the polysilicon (or other material used) will have essentially the same density in each respective plate of the capacitor. In the preferred embodiment, the capacitor plates are placed on the same levels, i.e., the bottom plates of the capacitors 68a and 72a should be formed on the same layer, and the top plates of the capacitors 68b and 72b are formed on the same layer. Once again, the ratio between the values of the capacitor will value only within a few percent and will not significantly affect the value of V.sub.peakmax.

Another advantage in placing the resistors and capacitors in close proximity is that the corresponding pairs will be similarly affected by temperature changes on the chip, and the effect of the temperature change will be substantially nullified.

As well as providing smaller size, lower cost, and higher performance, implementing the dual-slope A/D converter on an integrated circuit has the advantage of allowing the designer of the chip to compensate for parasitic voltage and current effects without concern for unknown effects of circuitry outside of the chip. Also, since all critical leakage nodes are internal to the chip, special cleaning and coating of the printed circuit boards is not necessary.

Referring now to FIG. 5, a cross-sectional view of the integrated circuit 60 across line A--A of FIG. 4 is shown. A P- substrate 76 has an N- well region 78. An N+ contact region 80 connects the N- well 78 to metal contact 82. The metal contact 82 is connected to analog common. A thick oxide layer 84 is placed over the N- well region 78. The oxide layer 84 is etched in the region above the N+ contact region 80 to allow connection with the metal contact 82. On top of the oxide layer 84, a polysilicon resistor layer (shown as the integrator resistor 64) is deposited and etched to form the resistor. The polysilicon layer undergoes a light implant to set its resistivity at a desired level. Also, the bottom plate 68a of the integrator capacitor 68 is deposited on top of the oxide layer 84. A second oxide layer 86 is grown or deposited on top of the first plate 68a. On top of the second oxide layer 86, the top plate 68b of the capacitor 68 is deposited.

The N- well region 78 creates a reversed biased pn junction between the N- well 78 and the P-substrate 76. This configuration has the technical advantage that substrate noise will not be capacitively coupled with the capacitor bottom plates 68a and 72a.

In the preferred embodiment, a polysilicon-polysilicon technology is used to fabricate the capacitors 68 and 72. Using this technology, the plates of the capacitors are formed as polysilicon layers, and subsequently implanted to reduce their resistivity. Less preferably, other technologies such as polysilicondiffusion, metal-diffusion, or metal-polysilicon can be employed to implement the capacitors.

It should be noted that FIG. 5 applies to N-well CMOS, P-well CMOS, and twin-well CMOS, other processes can be used with other processes, such as standard MOS and bipolar to implement the inventive concepts described herein.

Although a preferred embodiment of the invention has been described in detail, it should be understood that the various changes, substitutions and alterations can be made therein without departing from the spirit and scope of the invention as defined by the appended claims