US 4,847,906 AGrant
Linear Predictive Speech Coding Arrangement
Issue Date:1989-07-11
•3 Claims
•6 Drawing Sheets
Abstract
A speech analyzer is adapted to produce speech parameter signals from a Pth order autocorrelation analysis of a speech pattern in a digital signal processor. The analyzer includes a plurality of memories of predetermined arrangement to store feature vector signals used in the analysis, a single set of coded signals for controlling the analysis, and a memory address processor for addressing the feature vector signal memories. In each iteration of the analysis, at least one speech parameter signal is produced by the digital signal processor responsive to the same set of control signals and the feature vector memory addressing signals.
Metadata
Assignee
- American Telephone and Telegraph Company, AT&T Bell Laboratories
Inventor
- John G. Ackenhusen
Application Information
Application Number:US 8454477
Filing Date:1986-03-28
Priority Date:1986-03-28
Art Unit:231
Classifications
IPC:
G01L 100G01L 500
Field of Search:
38136441;46 MS;36;37 MS513.5 MS
Patent Drawings (6 sheets)
Description
Technical Field
The invention relates to speech analysis and more particularly to arrangements for generating signals representative of acoustic features of speech patterns.
Background of the Invention
Linear predictive coding (LPC) is extensively used in digital speech transmission, automatic speech recognition, and speech synthesis. One such digital speech coding system is disclosed in U.S. Pat. No. 3,624,302 issued to B. S. Atal, Nov. 30, 1971. The arrangement therein includes a linear prediction analysis of input speech in which the speech is partitioned into successive time frame intervals of 5 to 20 milliseconds duration, and a set of parameters representative of the time interval speech is generated. The parameter signal set includes linear prediction coefficient signals representative of the spectral envelope of the speech in the time interval, and pitch and voicing signals corresponding to the speech excitation. These parameter signals are encoded at a much lower bit rate than the speech signal waveform itself and a replica of the input speech signal is formed from the parameter signal codes by synthesis. The synthesizer arrangement comprises a model of the vocal tract in which the excitation pulses of each successive interval are modified by the interval spectral envelope prediction coefficients in an all pole predictive filter.
One well known method for generating speech feature signals involves speech analysis in which the autocorrelation of a time frame portion of a speech pattern are formed. The autocorrelation signals are then processed in accordance with the technique known as Durbin's recursion to generate signals that correspond to LPC coefficients, reflection coefficients, and the prediction residual energy of the time frame interval. While Durbin's recursion signal processing may be readily implemented in large general purpose computers, it is particularly useful to perform these processing operations in a single programmable digital signal processor (DSP) integrated circuit so that the processing equipment is small and economical. As is commonly known, however, the storage capacity in available DSP devices is generally small, and the DSP memory addressing capabilities are severely limited.
Transformation of an autocorrelation vector signal to a representation based on prior art linear prediction coding by the method of Durbin's recursion requires that operands be accessed from three single-dimension vectors and a two-dimension array. These requirements generally exceed the limited arithmetic addressing capability of a typical digital signal processor. As a result, it is necessary to store the signal processing instructions for each iteration of Durbin's recursion separately. Thus, a distinct set of instruction code signals is required for each iteration processing and the distinct sets are stored separately in the control memory of the digital signal processor. This stringing of the separate iteration instruction codes uses a large portion of the program memory and limits the utility of the DSP for speech processing applications. If all iterations required for Durbin's recursion could be performed by a single set of instruction code signals, processing of all iterations could be done by transferring control to a single subroutine occupying a predetermined number of control memory locations whereby DSP speech processing is rendered more efficient and more economical. It is an object of the invention to provide improved digital speech signal processing in real time digital signal processors.
Brief Summary of the Invention
The foregoing object is achieved by utilizing a plurality of data signal memories of predetermined size and arrangement determined by the order of the speech analysis, and sequentially addressing the locations of the signal memories during each iteration of the speech parameter processing. In this way, the memory addressing is performed in single increments and decrements within each iteration by sequentially addressing the location of the data signal memories so that a single set of coded instruction signals may be used for all iterations. As a result, the control memory size is substantially reduced and the memory requirements are independent of the order of the speech pattern analysis.
The invention is directed to an arrangement for analyzing a speech pattern to generate speech parameter signals representative thereof in which a set of speech pattern autocorrelation signals R(i), i=1, 2, . . . , P are formed for each successive time frame interval of a speech pattern. The arrangement includes a memory for storing a fixed number of control signals, a signal processor responsive to said autocorrelation signals and said fixed number of control signals for generating speech parameter signals corresponding to a Pth order analysis of each successive time frame interval speech portion, and a plurality of memories each for storing at least P speech parameter data signals in P successive locations. The signal processor generates a succession of i=1, 2, . . . , P iteration index signals. Responsive to each successive iteration index signal, addressing signals are produced for each of said plurality of memories. The speech parameter data signals are combined responsive to said set of control signals and said addressing signals to form at least one Pth order speech parameter signal.
Brief Description of the Drawing
FIG. 1 depicts a block diagram of a speech analysis arrangement illustrative of the invention;
FIGS. 2 and 3 show tables illustrating the addressing of the stores in the arrangement of FIG. 1; and
FIGS. 4, 5 and 6 show flow charts illustrating the operation of the arrangement of FIG. 1 to generate speech parameter signals.
Detailed Description
As is well known in the art, speech may be coded in terms of linear predictive parameters by forming a set of autocorrelation signals for each successive time frame interval, e.g., 5 to 20 millisecond period, and processing the autocorrelation signals in accordance with Durbin's recursion. The recursion is performed in a sequence of iterations, each of which results in the generation of speech parameter signals corresponding to the order of the iteration. The processing for each iteration i, i=1, 2, . . . , P, transforms a P.sup.th -order autocorrelation vector R(n), n=0, 1, 2, . . . , P, into a residual energy signal E.sup.(i), a reflection coefficient signal k.sub.i, intermediate vector signals .alpha..sub.j.sup.(i), j=1 to i-1, and LPC coefficient signal a.sub.j. Durbin's recursion includes the initial formation of a signal:
For successive iterations i=1, 2, . . . , P, signals corresponding to Equations 2-5 are formed. ##EQU1## (For i=1 the summation from 1 to 0 is skipped) ##EQU2## for j=1 to i-1: ##EQU3## Then the residual energy and LPC coefficient signals of the ith order are generated according to Equations 6-8: ##EQU4##
As is readily seen from the foregoing equations, each successive iteration differs significantly from the preceding iteration. Consequently, according to prior art arrangements each iteration is processed under control of a different set of stored instruction signals. In particular, the processing corresponding to Equations 2 and 5 requires a different number of steps for each iteration since the number of computations increases for each successive iteration. Equation 2 may be rearranged in the form of a sum of products, ##EQU5## which may be preceded by the series
since the sum of this series is zero.
Thus, the sum of Equation 2 can be formed for any iteration i.ltoreq.P by reversing the order of the terms of Equation 9 and generating a vector signal corresponding to: ##EQU6##
This summation expression uses two vector signals of length P of coefficients ordered sequentially in fixed size memory, one beginning with ##EQU7## the other beginning with R(1): ##EQU8##
Vector signal [.alpha..sub.j.sup.(i-1), j=i-1, i-2, . . . , 1] has appended thereto the vector signal [1, 0, . . . , 0] to provide a fixed number of P elements. With this memory arrangement, the summation of Equation 2 becomes the simple scalar product of vector signals [.alpha..sub.j.sup.(i-1) ] and [R(i)], independent of the iteration count i. The reciprocal of E.sup.(i-1) required in Equation 3 may be performed by well-known processing techniques.
The use of data signal memories in accordance with the invention is illustrated with reference to the table of FIG. 2. For purposes of illustration, it is assumed that a signal processor having two operand source address pointers, p1 and p2, and a destination address pointer p3 is utilized. Source address pointers p1 and p2 may be incremented or decremented and point to a multiplier and a multiplicand in memory, respectively. Destination address p3 points to a result storage location and may also be incremented. Section 201 of the leftmost column corresponds to the locations in a memory of predetermined size that stores autocorrelation signals R(0), R(1), . . . , R(P). Section 205 of the leftmost column corresponds to the locations in another memory of predetermined size storing intermediate data signals ##EQU9## . . . , -.alpha..sub.1.sup.(i-1), 1, 0, . . . , 0.
For a typical time frame interval iteration P=8, i=5 in FIG. 2, the successive processing of the terms of Equation 2 as j is decremented from i-1=4 progresses left to right across from column 210 to column 245. Source address pointer p1 is initially set at R(1) and source address pointer p2 is initially set at -.alpha..sub.4.sup.(4) to obtain the partial result -.alpha..sub.4.sup.(4). R(1) shown at the bottom of the j=4 column 210 in FIG. 2. The source address pointers are then incremented to address the R(2) and -.alpha..sub.3.sup.(4) locations of the two fixed size memories as indicated in the j=3 column 215. The regular sequential progression of source address pointers p1 and p2 for processing signals according to Equation 10 is readily seen in the illustration of FIG. 2. The processing indicated in columns 235, 240 and 241 are multiplications using zero valued locations of the .alpha. parameter memory to achieve a uniform iteration processing. In accordance with the invention, specified memories are assigned to data vector signals to render the generation of predictive parameter signals independent of the particular iteration being processed.
With respect to the signal processing for Equation 5, FIG. 3 illustrates the arrangement of the invention to make the processing uniform for every iteration whereby a single set of instruction code signals may be used. For purposes of illustration, assume an eighth order predictive parameter analysis for a time frame interval in which the fifth iteration is performed. Equation 5 may be transformed as shown in Equations 12-15. These equations are written in reverse order of the index j, j=i-1, i-2, . . . , 1: ##EQU10##
In Equations 12-15, the values of [.alpha..sub.j.sup.(i) ] on the left sides of the equations are addressed in storage in descending order of j and the values of [.alpha..sub.j.sup.(i-1) ] are addressed in ascending order of j for the first right side term (product with k.sub.5) and are addressed in descending order of j in the second right side term. Although only i-1 calculations are required for Equation 5, dummy calculations are appended as with respect to Equation 10 to achieve a regular structure requiring only a single set of instruction code signals. This is done by prefixing the array [.alpha..sub.j.sup.(i-1) ] with [0, 0, . . . , 0] and postfixing the array [.alpha..sub.j.sup.(i-1) ] with [1, 0, 0, . . . , 0]. The processing according to Equation 5 is started with one source address pointer set at ##EQU11## at the top of the array and the other source address pointer set at the other end of the array (.alpha..sub.1.sup.(i-1)). The destination pointer is set to address the second location of the destination array for storing the [.alpha..sub.j.sup.(i) ] values on the left of Equations 12-15. The iterations of Equation 5 are then performed by incrementing the first address pointer, decrementing the second address pointer and incrementing the destination pointer. The offset between these two source address pointers is i-2 and is the only portion of the recursion that changes with iteration index i. For i=1, this pointer actually points one location above the top -.alpha. entry of the array memory.
Referring to FIG. 3, the leftmost column is divided into sections 301 and 310. Section 301 corresponds to the successive locations of the .alpha. vector signal in store 125 of FIG. 1 at the beginning of the P=8, i=5 iteration. Section 310 corresponds to destination memory 130 for storing the resulting signals of the iteration. The descending succession of j columns 320 through 345 shows the placement of the p1 and p2 source address pointer signals with reference to the memory of section 301. Address pointer signal p3 in the j columns illustrates the addressing of the resulting signal store 130. The bottom row of FIG. 3 indicates the term processed in the j column.
As the iteration progresses through the j=4, 3, 2, 1 sequence, processing corresponding to Equations 12-15 is performed. For any iteration i, the processing begins with p1 pointing i-2 locations into the array. In j=4 column 320 illustrated in FIG. 3 where iteration index i=5, address pointer p1 points to 5-2=3 locations beyond p2. The addressing of column section 301 of FIG. 3 is sequential where address pointer p1 decrements while address pointer p2 increments as the processing proceeds from left to right. The resulting elements of [.alpha..sub.j.sup.(i-1) ] are entered sequentially in column section 310 as addressed indicated by destination address pointer p3. Constant pointer c provides operand signal k for all values of j.
As shown in FIG. 3, the resultant array in column section 310, [.alpha..sub.j.sup.(5) ], is appended with the sequence [1, 0, 0, . . . ] so that the array is aligned with the array of FIG. 2. The P-element array [.alpha..sub.j.sup.(5) ] is transferred to the memory locations occupied by [.alpha..sub.j.sup.(4) ] in column section 301 at the end of the iteration. The other processing steps of the recursion iteration after those for Equations 2 and 5 are performed only once for each iteration. The processing continues after the double vertical line to fill the resultant memory locations addressed by pointer p3 with 1, 0, . . . , 0 responsive to the locations of section 301 addressed by pointers p1 and p2.
FIG. 1 depicts a circuit arrangement adapted to form linear predictive coding parameter signals for a speech pattern that is illustrative of the invention and FIGS. 4 through 6 depict flow charts illustrating the operation of the arrangement of FIG. 1. Appendix A is a listing in DSP20 language form of the program instruction signals of the control memory of FIG. 1 corresponding to the steps in the flow charts of FIGS. 4-6. The circuit of FIG. 1 may comprise the DSP20 digital signal processor described in the special issue on the "Digital Signal Processor", Bell System Technical Journal, Vol. 60, No. 7, Part 2 (September 1981), pp. 1431-1709. In FIG. 1, speech is applied to electro-acoustic transducer 101 wherein it is converted into an electrical signal representative of the speech waveform. The speech signal from transducer 101 is transformed into a sequence of digital codes corresponding to the speech wave form by digitizer 105. The digitizer may, as is well known in the art, comprise a low pass filter to limit the bandwidth of the speech signal, a sampler operative to sample the filtered signal at a predetermined rate and an analog-to-digital converter adapted to produce a digital code for each speech signal sample.
The sequence of speech sample codes from digitizer 105 is partitioned into overlapping time frame intervals each of which may be 45 milliseconds in duration with a 15 millisecond overlap in autocorrelation signal generator 110. A set of autocorrelation signals R(0), R(1), . . . , R(P) are formed for the time frame interval as indicated in step 401 of the flow chart of FIG. 4 and signals R(1), R(2), . . . , R(P) are output to the successive locations 0 to P-1 of the P location autocorrelation store 115 under control of control processor 155. .alpha. store 125 is a fixed size 2P location store adapted to store the .alpha. parameter vector signals of the time frame interval speech parameter processing. Signal store 130 is a fixed size P location store to store the parameter vector signals of the time frame interval speech parameter processing. Stores 115, 125, and 130 may be in successive locations sections of a common random access data signal memory as shown in FIG. 1 or may be separate memories. The addressing of the locations of stores 115, 125, and 130 is controlled by memory address processor 135 which generates address pointer signals p1, p2, p3, and c to select data signal locations during each iteration of the Durbin's recursion processing.
Arithmetic processor and accumulator 140 receives data signals from memories 115, 125, and 130 as addressed by pointer signals p1, p2 and p3 and forms parameter signals in accordance with Equations 2-8 as controlled by control memory 150. Arithmetic processor 140 includes an accumulator that temporarily stores arithmetic operation results as is well known in the art. The output of processor 140 is sent to parameter store 145 for use in later steps of the recursion processing. Control memory includes a single fixed set of instruction code signals that is applied to control processor 155 to control each iteration of the recursion processing. Instead of storing a different set of control instruction codes for each iteration, the arrangement of FIG. 1 in accordance with the invention uses the same set of instruction codes for every recursion iteration. In this way, the size of the control memory is substantially reduced with the limited data signal memory addressing facilities of economical digital signal processors.
Referring to FIG. 4, the first P locations of .alpha. store 125, locations P to 2P-1, are initially set to zero as per step 405; the last P locations of .alpha. store 125, locations 2P to 3P-1, are set to 1, 0, . . . , 0 as per step 410; and the P locations of .beta. parameter store 130, locations 3P to 4P-1 are set to zero as per step 415. Residual energy register 145-2 at location 4P+1 and sum register 145-1 at location 4P of parameter signal store 145 are set to R(0) and zero, respectively (steps 420 and 425). Iteration index register 145-4 at location 4P+3 is also set to i=1 corresponding to the first iteration of the recursion (step 430).
After the initialization of the recursion memories and registers of steps 405 through 435, the memory addressing pointer signals are initially set to to enable arithmetic processor 140 to generate sum signals s(i) for the current iteration i (step 501 of FIG. 5), in accordance with Equation 10. Source pointer signal p1 which addresses autocorrelation memory 115 is set to zero corresponding to the location in which R(1) is stored. Source address pointer signal p2 which addresses the .alpha. vector signal in memory 125 is set to location 2P in which the signal ##EQU12## is stored. For the first iteration (i=1), this location has been initialized to 1. Destination pointer signal p3 which addresses .beta. store 130 is set to the first location 3P of .beta. store 130. The accumulator of processor 140 is set to zero (step 505) and the loop including steps 510 through 520 is entered to generate a scalar product signal according to Equation 10.
In step 510, the signal in the location of autocorrelation store 115 addressed by pointer signal p2 (denoted as (*p2)) and the signal in the location of .alpha. store 125 addressed by pointer signal p1 (denoted as (*p1)) are applied to arithmetic processor 140 wherein the product signal (*p1).multidot.(*p2) is formed. This product signal representative of ##EQU13## is then added to the signal s(i) which is in the accumulator of processor 140. Source pointer signals p1 and p2 are incremented as per step 515 and steps 510 and 515 are repeated until pointer signal p1 has reached the P location of the autocorrelation signal store at which time the processing corresponding to Equation 10 for the current iteration is complete. Step 525 is then entered via decision step 520 and the sum signal s(i) is transferred from the accumulator of processor 140 to sum register 145-1 at address 4P of parameter store 145.
Autocorrelation signal store 115 stores the signals
in locations 0, 1, . . . , P-1 and the second half of .alpha. store 125 contains signals ##EQU14## corresponding to a P element vector signal. The operations of the loop from step 510 through 520 generate the scalar product signal of Equation 10. In accordance with the invention, the arrangement of memory 125 prefixed by 0, . . . , 0, and appended with 1, 0, . . . , 0 values makes the sum signal formation uniform for all iterations i so that the instruction code signals therefor form a single subroutine in control memory 150.
The ith order reflection coefficient signal k(i) is produced by dividing the sum signal in register 145-1 of parameter store 145 by the residual energy signal E(i-1) of the preceding iteration i-1 in control processor 155 (step 528). For this operation, the sum signal in location 4P+1 and the residual energy signal stored in location 4P of parameter store 145 are applied to processor 140. The resulting reflection coefficient signal k(i) from the processor is then stored in location 3P of store 130 (step 528) and in location 4P+2 of store 145 (step 530). At this time, destination pointer signal p3 is incremented to address the next location in memory 130. Source pointer signal p2 is set to address location 2P in store 125 (step 538) and source pointer signal p1 is set to address the i-2 location into store 125 (step 540). The loop including steps 545 through 560 is iterated to generate the P element vector signal ##EQU15##
In the first pass through step 545, (*p1) is the signal ##EQU16## (*p2) is the signal ##EQU17## and the signal k(i) is in register 145-3 at location 4P+2. These signals are applied to arithmetic processor 140 and the resulting signal ##EQU18## therefrom is stored in the location p3=3P+1. Pointer signals p2 and p3 are incremented as per steps 550. Address pointer signal p1 is decremented (555) and address pointer p2 is tested to determine if address 3P-1 has been reached (step 560). These operations are performed in address processor 135 under control of instruction code signals from control memory 140. When p2=3P-1, the P element vector signal
is stored in memory 130 and step 601 of FIG. 6 is entered to generate the residual energy signal E(i+1) of the current time frame interval. The E(i+1) signal is formed in arithmetic processor 140 in accordance with
where location 4P+1 of parameter store 145 contains the residual energy signal E(i) and location 4P+3 of the parameter store contains the reflection coefficient signal k(i). The signals in store 130 corresponding to the results of the current iteration i are then transferred to locations 2P to 3P-1 of store 125 (step 605) preparatory to the next iteration. Iteration index signal i is then incremented (step 610) and the incremented index signal is checked to determine if the final iteration of the time frame interval has been completed (step 615). If not, step 501 of FIG. 5 is reentered for the next iteration. Upon completion of the iterations for the current time frame interval, the final iteration result signals are transferred from store 130 to utilization device 180 which may comprise a speech coder, speech synthesizer or speech recognizer of the types well known in the art (step 620) and the circuit of FIG. 1 is placed in a wait state until the start of the next time frame interval (step 625).
Consider the operation of the arrangement of FIG. 1 in the generation of the LPC parameters of an LPC model of order P=3 for a single time frame interval. The time frame speech pattern portion is transformed into a set of autocorrelation signals R(0), R(1), R(2), R(3). After the initialization steps shown in FIG. 4, autocorrelation store 115 contains signals R(1), R(2), R(3) and does not change during the iteration processing. The first P locations of parameter store 125 are reset to 0, 0, 0 and remain in this state throughout the iterations. The last P locations of parameter store 125 are set to 1, 0, 0. Parameter store 130 is reset to 0, 0, 0. Residual energy store 145-2 contains signal R(0), and iteration index signal store i is set to one.
Just prior to step 545 of FIG. 5 in the first iteration i=1, sum register 145-1 contains the signal s(1). Reflection coefficient register 145-3 stores signal k(1)=.alpha..sub.1.sup.(1). Parameter store 125 contains the vector signal 0, 0, 0, 1, 0, 0. Address pointer signals p1 and p2 are set to locations 2P-1 and 2P, of parameter store 125, respectively. The reflection coefficient signal -k(1) is in the first location of .beta. store 130 and address pointer signal p3 is set to the second location of store 130.
When step 545 is entered for the iteration i=2, parameter store 125 has been changed to 0, 0, 0, -.alpha..sub.1.sup.(1), 1, 0 and .beta. store 130 contains the signal -k(2)=-.alpha..sub.2.sup.(2) in its first location. Address pointer signals p1 and p2 are both set to the first location of parameter store 125 while pointer signal p3 is set to the second location of store 130. At the same point in the operation of the circuit of FIG. 1 for iteration i=3, store 125 contains the vector signal -.alpha..sub.2.sup.(2), -.alpha..sub.1.sup.(2), 1 while the first location store 130 has the signal-k(3)=-.alpha..sub.3.sup.(3). Address pointer signals p1 and p2 are set to the first and second locations of store 125, respectively, and pointer signal p3 is set to the second location of store 130. At the end of the last iteration, i=4, just prior to step 610 of FIG. 6, parameter store 125 contains the vector signal 0, 0, 0,-.alpha..sub.3.sup.(3), -.alpha..sub.2.sup.(3), -.alpha..sub.1.sup.(3), the last P values of which correspond to the LPC coefficients of the time frame interval.
The invention has been described with reference to illustrative embodiments thereof. It is apparent, however, to one skilled in the art that various modifications and changes may be made without departing from the spirit and scope of the invention. ##SPC1##
Claims
What is claimed is:
1. A method of speech analysis, of the type comprising the steps: receiving successive time frame interval portions of a speech pattern; generating a set of autocorrelation signals R(0), R(1), . . . , R(P) corresponding to the present time frame interval speech pattern portion in response to the present time frame interval portion of said speech pattern; and generating a set of linear predictive parameter signals for said present time frame interval in response to said autocorrelation signal set; said linear predictive parameter signal set generating step comprising; employing Durbin's recursion, as follows: for successive iterations i=1, 2, . . . , P, generating signals ##EQU19## where j is a subordinate index varying from 1 to i-1 within each iteration, and .alpha..sub.j.sup.(i-1) is an intermediate signal initially generated from a initial reflection coefficient k, where k=s.sub.i /E.sup.(i-1) and e.sup.(i-1) is a residual energy signal from the previous iteration which intermediate signal is to be iteratively developed into a linear predictive coefficient .alpha..sub.j =.alpha..sub.j.sup.(P) and ##EQU20## said method being particularly characterized in that the generating step includes generating signals for appended calculations to make each portion of each iteration repetitive of a set of arithmetic operations, so that j varies from P to 1 in each iteration, the generating step (as in FIG. 2) including storing the autocorrelation signals for successive access for each change of the value j from P to 1 for the first signal s.sub.i ; storing (as in FIG. 3) the intermediate values in the order of generation in the previous iteration and continuing through appended values equal in number to P minus the i value for said previous iteration but having P appended values equal to zero in sequence from the first value and in the opposite order, the intermediate values being sequentially accessed in the order of generation for the generation of the first term of the second signal and being sequentially accessed in the inverse order of generation for the generation of the second term of the second signal for values of j from P to 1 in each iteration; said storing step including replacing the stored intermediate values with new values for the next iteration involving the next higher value of i in like order without affecting (P-i) nearest appended values preceding the first generated value for the previous iteration, where i is the i value of the previous iteration; and separately accessing (as in FIG. 2) the values of the intermediate signals in the order of generation in the previous iteration and continuing through appended values equal in number to P minus the i value for said previous iteration, said appended values being appropriate for successive access for each change of the value j from P to 1 in each iteration for the generation of the first signal s.sub.i, the separately accessing step including replacing said stored intermediate values with new values in the order of generation after each completion iteration for a particular value of i, so that one less appended value is stored at the start of each new iteration.
2. A method of the type claimed in claim 1, said method being further characterized in that the first intermediate value signal storing step comprises storing, as the appended values, the values 1, 0, 0, . . . 0, where the zeros number P+1-i.
Patent Citations (6)
Non-Patent Literature (1)
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